ARM-specific instruction creation convenience macros. More...
Macros | |
| #define | OPND_CREATE_ABSMEM(addr, size) opnd_create_rel_addr(addr, size) |
| #define | OPND_CREATE_NEG_REG(reg) opnd_create_reg_ex(reg, 0, DR_OPND_NEGATED) |
| #define | OPND_CREATE_INT(val) OPND_CREATE_INTPTR(val) |
| #define | OPND_CREATE_INT_MSR_NZCVQ() opnd_create_immed_int(EFLAGS_MSR_NZCVQ, OPSZ_4b) |
| #define | OPND_CREATE_INT_MSR_G() opnd_create_immed_int(EFLAGS_MSR_G, OPSZ_4b) |
| #define | OPND_CREATE_INT_MSR_NZCVQG() opnd_create_immed_int(EFLAGS_MSR_NZCVQG, OPSZ_4b) |
| #define | OPND_CREATE_MEMLIST(base) opnd_create_base_disp(base, DR_REG_NULL, 0, 0, OPSZ_VAR_REGLIST) |
| #define | INSTR_CREATE_pop(dc, Rd) |
| #define | INSTR_CREATE_pop_list(dc, list_len, ...) INSTR_CREATE_ldm_wb((dc), OPND_CREATE_MEMLIST(DR_REG_XSP), list_len, __VA_ARGS__) |
| #define | INSTR_CREATE_push(dc, Rt) |
| #define | INSTR_CREATE_push_list(dc, list_len, ...) INSTR_CREATE_stmdb_wb((dc), OPND_CREATE_MEMLIST(DR_REG_XSP), list_len, __VA_ARGS__) |
| #define | INSTR_CREATE_neg(dc, Rd, Rn) INSTR_CREATE_rsb((dc), (Rd), (Rn), OPND_CREATE_INT16(0)) |
Platform-independent macros | |
| #define | XINST_CREATE_debug_instr(dc) INSTR_CREATE_bkpt((dc), OPND_CREATE_INT8(1)) |
| #define | XINST_CREATE_load(dc, r, m) INSTR_CREATE_ldr((dc), (r), (m)) |
| #define | XINST_CREATE_load_1byte_zext4(dc, r, m) INSTR_CREATE_ldrb((dc), (r), (m)) |
| #define | XINST_CREATE_load_1byte(dc, r, m) INSTR_CREATE_ldrb((dc), (r), (m)) |
| #define | XINST_CREATE_load_2bytes(dc, r, m) INSTR_CREATE_ldrh((dc), (r), (m)) |
| #define | XINST_CREATE_store(dc, m, r) INSTR_CREATE_str((dc), (m), (r)) |
| #define | XINST_CREATE_store_1byte(dc, m, r) INSTR_CREATE_strb((dc), (m), (r)) |
| #define | XINST_CREATE_store_2bytes(dc, m, r) INSTR_CREATE_strh((dc), (m), (r)) |
| #define | XINST_CREATE_store_pair(dc, m, r1, r2) INSTR_CREATE_strd((dc), (m), (r1), (r2)) |
| #define | XINST_CREATE_load_pair(dc, r1, r2, m) INSTR_CREATE_ldrd((dc), (r1), (r2), (m)) |
| #define | XINST_CREATE_move(dc, d, s) INSTR_CREATE_mov((dc), (d), (s)) |
| #define | XINST_CREATE_load_simd(dc, r, m) INSTR_CREATE_vldr((dc), (r), (m)) |
| #define | XINST_CREATE_store_simd(dc, m, r) INSTR_CREATE_vstr((dc), (m), (r)) |
| #define | XINST_CREATE_jump_mem(dc, m) INSTR_CREATE_ldr((dc), opnd_create_reg(DR_REG_PC), (m)) |
| #define | XINST_CREATE_jump_reg(dc, r) INSTR_CREATE_bx((dc), (r)) |
| #define | XINST_CREATE_load_int(dc, r, i) |
| #define | XINST_CREATE_return(dc) INSTR_CREATE_pop(dc, opnd_create_reg(DR_REG_PC)) |
| #define | XINST_CREATE_jump(dc, t) INSTR_CREATE_b((dc), (t)) |
| #define | XINST_CREATE_call(dc, t) INSTR_CREATE_bl((dc), (t)) |
| #define | XINST_CREATE_jump_short(dc, t) |
| #define | XINST_CREATE_jump_cond(dc, pred, t) (INSTR_PRED(INSTR_CREATE_b((dc), (t)), (pred))) |
| #define | XINST_CREATE_add(dc, d, s) INSTR_CREATE_add((dc), (d), (d), (s)) |
| #define | XINST_CREATE_add_2src(dc, d, s1, s2) INSTR_CREATE_add((dc), (d), (s1), (s2)) |
| #define | XINST_CREATE_add_sll(dc, d, s1, s2_toshift, shift_amount) |
| #define | XINST_CREATE_add_s(dc, d, s) INSTR_CREATE_adds((dc), (d), (d), (s)) |
| #define | XINST_CREATE_sub(dc, d, s) INSTR_CREATE_sub((dc), (d), (d), (s)) |
| #define | XINST_CREATE_sub_s(dc, d, s) INSTR_CREATE_subs((dc), (d), (d), (s)) |
| #define | XINST_CREATE_and_s(dc, d, s) INSTR_CREATE_ands((dc), (d), (d), (s)) |
| #define | XINST_CREATE_slr_s(dc, d, s) INSTR_CREATE_lsrs((dc), (d), (d), (s)) |
| #define | XINST_CREATE_cmp(dc, s1, s2) INSTR_CREATE_cmp((dc), (s1), (s2)) |
| #define | XINST_CREATE_interrupt(dc, i) INSTR_CREATE_svc(dc, (i)) |
| #define | XINST_CREATE_nop(dc) INSTR_CREATE_nop(dc) |
| #define | XINST_CREATE_call_reg(dc, r) INSTR_CREATE_blx_ind(dc, r) |
Signature: (pc) | |
| #define | INSTR_CREATE_b_short(dc, pc) instr_create_0dst_1src((dc), OP_b_short, (pc)) |
| #define | INSTR_CREATE_b(dc, pc) instr_create_0dst_1src((dc), OP_b, (pc)) |
| #define | INSTR_CREATE_b_short(dc, pc) instr_create_0dst_1src((dc), OP_b_short, (pc)) |
| #define | INSTR_CREATE_bl(dc, pc) instr_create_1dst_1src((dc), OP_bl, opnd_create_reg(DR_REG_LR), (pc)) |
| #define | INSTR_CREATE_blx(dc, pc) instr_create_1dst_1src((dc), OP_blx, opnd_create_reg(DR_REG_LR), (pc)) |
Signature: () | |
| #define | INSTR_CREATE_clrex(dc) instr_create_0dst_0src((dc), OP_clrex) |
| #define | INSTR_CREATE_dcps1(dc) instr_create_0dst_0src((dc), OP_dcps1) |
| #define | INSTR_CREATE_dcps2(dc) instr_create_0dst_0src((dc), OP_dcps2) |
| #define | INSTR_CREATE_dcps3(dc) instr_create_0dst_0src((dc), OP_dcps3) |
| #define | INSTR_CREATE_enterx(dc) instr_create_0dst_0src((dc), OP_enterx) |
| #define | INSTR_CREATE_eret(dc) instr_create_0dst_1src((dc), OP_eret, opnd_create_reg(DR_REG_LR)) |
| #define | INSTR_CREATE_leavex(dc) instr_create_0dst_0src((dc), OP_leavex) |
| #define | INSTR_CREATE_nop(dc) instr_create_0dst_0src((dc), OP_nop) |
| #define | INSTR_CREATE_sev(dc) instr_create_0dst_0src((dc), OP_sev) |
| #define | INSTR_CREATE_sevl(dc) instr_create_0dst_0src((dc), OP_sevl) |
| #define | INSTR_CREATE_wfe(dc) instr_create_0dst_0src((dc), OP_wfe) |
| #define | INSTR_CREATE_wfi(dc) instr_create_0dst_0src((dc), OP_wfi) |
| #define | INSTR_CREATE_yield(dc) instr_create_0dst_0src((dc), OP_yield) |
Signature: (Rd) | |
| #define | INSTR_CREATE_vmrs(dc, Rd) instr_create_1dst_1src((dc), OP_vmrs, (Rd), opnd_create_reg(DR_REG_FPSCR)) |
Signature: (Rm) | |
| #define | INSTR_CREATE_blx_ind(dc, Rm) instr_create_1dst_1src((dc), OP_blx_ind, opnd_create_reg(DR_REG_LR), (Rm)) |
| #define | INSTR_CREATE_bx(dc, Rm) instr_create_0dst_1src((dc), OP_bx, (Rm)) |
| #define | INSTR_CREATE_bxj(dc, Rm) instr_create_0dst_1src((dc), OP_bxj, (Rm)) |
Signature: (Rt) | |
| #define | INSTR_CREATE_vmsr(dc, Rt) instr_create_1dst_1src((dc), OP_vmsr, opnd_create_reg(DR_REG_FPSCR), (Rt)) |
Signature: (Rd, Rm) | |
| #define | INSTR_CREATE_clz(dc, Rd, Rm) instr_create_1dst_1src((dc), OP_clz, (Rd), (Rm)) |
| #define | INSTR_CREATE_rbit(dc, Rd, Rm) instr_create_1dst_1src((dc), OP_rbit, (Rd), (Rm)) |
| #define | INSTR_CREATE_rev(dc, Rd, Rm) instr_create_1dst_1src((dc), OP_rev, (Rd), (Rm)) |
| #define | INSTR_CREATE_rev16(dc, Rd, Rm) instr_create_1dst_1src((dc), OP_rev16, (Rd), (Rm)) |
| #define | INSTR_CREATE_revsh(dc, Rd, Rm) instr_create_1dst_1src((dc), OP_revsh, (Rd), (Rm)) |
| #define | INSTR_CREATE_rrx(dc, Rd, Rm) instr_create_1dst_1src((dc), OP_rrx, (Rd), (Rm)) |
| #define | INSTR_CREATE_rrxs(dc, Rd, Rm) instr_create_1dst_1src((dc), OP_rrxs, (Rd), (Rm)) |
Signature: (Rd, Rn) | |
| #define | INSTR_CREATE_sxtb(dc, Rd, Rn) instr_create_1dst_1src((dc), OP_sxtb, (Rd), (Rn)) |
| #define | INSTR_CREATE_sxth(dc, Rd, Rn) instr_create_1dst_1src((dc), OP_sxth, (Rd), (Rn)) |
| #define | INSTR_CREATE_uxtb(dc, Rd, Rn) instr_create_1dst_1src((dc), OP_uxtb, (Rd), (Rn)) |
| #define | INSTR_CREATE_uxth(dc, Rd, Rn) instr_create_1dst_1src((dc), OP_uxth, (Rd), (Rn)) |
Signature: (pc, Rn) | |
| #define | INSTR_CREATE_cbnz(dc, pc, Rn) instr_create_0dst_2src((dc), OP_cbnz, (pc), (Rn)) |
| #define | INSTR_CREATE_cbz(dc, pc, Rn) instr_create_0dst_2src((dc), OP_cbz, (pc), (Rn)) |
Signature: (Rd, statreg) | |
| #define | INSTR_CREATE_mrs(dc, Rd, statreg) instr_create_1dst_1src((dc), OP_mrs, (Rd), (statreg)) |
Signature: (Rd, Rm, Rn) | |
| #define | INSTR_CREATE_qsub(dc, Rd, Rm, Rn) instr_create_1dst_2src((dc), OP_qsub, (Rd), (Rm), (Rn)) |
Signature: (Rd, Rn, Rm) | |
| #define | INSTR_CREATE_crc32b(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_crc32b, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_crc32cb(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_crc32cb, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_crc32ch(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_crc32ch, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_crc32cw(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_crc32cw, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_crc32h(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_crc32h, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_crc32w(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_crc32w, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_mul(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_mul, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_muls(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_muls, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_qadd(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_qadd, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_qadd16(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_qadd16, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_qadd8(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_qadd8, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_qasx(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_qasx, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_qdadd(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_qdadd, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_qdsub(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_qdsub, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_qsax(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_qsax, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_qsub16(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_qsub16, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_qsub8(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_qsub8, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_sadd16(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_sadd16, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_sadd8(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_sadd8, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_sasx(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_sasx, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_sdiv(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_sdiv, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_sel(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_sel, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_shadd16(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_shadd16, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_shadd8(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_shadd8, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_shasx(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_shasx, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_shsax(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_shsax, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_shsub16(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_shsub16, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_shsub8(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_shsub8, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_smmul(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_smmul, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_smmulr(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_smmulr, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_smuad(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_smuad, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_smuadx(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_smuadx, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_smulbb(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_smulbb, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_smulbt(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_smulbt, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_smultb(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_smultb, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_smultt(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_smultt, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_smulwb(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_smulwb, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_smulwt(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_smulwt, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_smusd(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_smusd, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_smusdx(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_smusdx, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_ssax(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_ssax, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_ssub16(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_ssub16, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_ssub8(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_ssub8, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_uadd16(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_uadd16, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_uadd8(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_uadd8, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_uasx(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_uasx, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_udiv(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_udiv, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_uhadd16(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_uhadd16, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_uhadd8(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_uhadd8, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_uhasx(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_uhasx, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_uhsax(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_uhsax, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_uhsub16(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_uhsub16, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_uhsub8(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_uhsub8, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_uqadd16(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_uqadd16, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_uqadd8(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_uqadd8, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_uqasx(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_uqasx, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_uqsax(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_uqsax, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_uqsub16(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_uqsub16, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_uqsub8(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_uqsub8, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_usad8(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_usad8, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_usax(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_usax, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_usub16(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_usub16, (Rd), (Rn), (Rm)) |
| #define | INSTR_CREATE_usub8(dc, Rd, Rn, Rm) instr_create_1dst_2src((dc), OP_usub8, (Rd), (Rn), (Rm)) |
Signature: (Rd, Rn, Rm, Ra) | |
| #define | INSTR_CREATE_mla(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_mla, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_mlas(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_mlas, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_mls(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_mls, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_smlabb(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_smlabb, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_smlabt(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_smlabt, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_smlad(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_smlad, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_smladx(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_smladx, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_smlatb(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_smlatb, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_smlatt(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_smlatt, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_smlawb(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_smlawb, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_smlawt(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_smlawt, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_smlsd(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_smlsd, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_smlsdx(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_smlsdx, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_smmla(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_smmla, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_smmlar(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_smmlar, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_smmls(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_smmls, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_smmlsr(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_smmlsr, (Rd), (Rn), (Rm), (Ra)) |
| #define | INSTR_CREATE_usada8(dc, Rd, Rn, Rm, Ra) instr_create_1dst_3src((dc), OP_usada8, (Rd), (Rn), (Rm), (Ra)) |
Signature: (Rd, Rd2, Rn, Rm) | |
| #define | INSTR_CREATE_smlal(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_4src((dc), OP_smlal, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_smlalbb(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_4src((dc), OP_smlalbb, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_smlalbt(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_4src((dc), OP_smlalbt, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_smlald(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_4src((dc), OP_smlald, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_smlaldx(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_4src((dc), OP_smlaldx, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_smlals(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_4src((dc), OP_smlals, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_smlaltb(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_4src((dc), OP_smlaltb, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_smlaltt(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_4src((dc), OP_smlaltt, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_smlsld(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_4src((dc), OP_smlsld, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_smlsldx(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_4src((dc), OP_smlsldx, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_smull(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_2src((dc), OP_smull, (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_smulls(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_2src((dc), OP_smulls, (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_umaal(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_4src((dc), OP_umaal, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_umlal(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_4src((dc), OP_umlal, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_umlals(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_4src((dc), OP_umlals, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_umull(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_2src((dc), OP_umull, (Rd), (Rd2), (Rn), (Rm)) |
| #define | INSTR_CREATE_umulls(dc, Rd, Rd2, Rn, Rm) instr_create_2dst_2src((dc), OP_umulls, (Rd), (Rd2), (Rn), (Rm)) |
Signature: (imm) | |
| #define | INSTR_CREATE_bkpt(dc, imm) instr_create_0dst_1src((dc), OP_bkpt, (imm)) |
| #define | INSTR_CREATE_cps(dc, imm) instr_create_0dst_1src((dc), OP_cps, (imm)) |
| #define | INSTR_CREATE_cpsid(dc, imm) instr_create_0dst_1src((dc), OP_cpsid, (imm)) |
| #define | INSTR_CREATE_cpsie(dc, imm) instr_create_0dst_1src((dc), OP_cpsie, (imm)) |
| #define | INSTR_CREATE_dbg(dc, imm) instr_create_0dst_1src((dc), OP_dbg, (imm)) |
| #define | INSTR_CREATE_dmb(dc, imm) instr_create_0dst_1src((dc), OP_dmb, (imm)) |
| #define | INSTR_CREATE_dsb(dc, imm) instr_create_0dst_1src((dc), OP_dsb, (imm)) |
| #define | INSTR_CREATE_eret_imm(dc, imm) instr_create_0dst_2src((dc), OP_eret, opnd_create_reg(DR_REG_LR), (imm)) |
| #define | dr_ir_macros_arm_hlt(dc, imm) instr_create_0dst_1src((dc), OP_hlt, (imm)) |
| #define | dr_ir_macros_arm_hvc(dc, imm) instr_create_0dst_1src((dc), OP_hvc, (imm)) |
| #define | INSTR_CREATE_isb(dc, imm) instr_create_0dst_1src((dc), OP_isb, (imm)) |
| #define | INSTR_CREATE_setend(dc, imm) instr_create_0dst_1src((dc), OP_setend, (imm)) |
| #define | INSTR_CREATE_smc(dc, imm) instr_create_0dst_1src((dc), OP_smc, (imm)) |
| #define | INSTR_CREATE_svc(dc, imm) instr_create_0dst_1src((dc), OP_svc, (imm)) |
| #define | INSTR_CREATE_udf(dc, imm) instr_create_0dst_1src((dc), OP_udf, (imm)) |
Signature: (Rd, imm) | |
| #define | INSTR_CREATE_movt(dc, Rd, imm) instr_create_1dst_1src((dc), OP_movt, (Rd), (imm)) |
| #define | INSTR_CREATE_movw(dc, Rd, imm) instr_create_1dst_1src((dc), OP_movw, (Rd), (imm)) |
| #define | INSTR_CREATE_mrs_priv(dc, Rd, imm) instr_create_1dst_1src((dc), OP_mrs_priv, (Rd), (imm)) |
| #define | INSTR_CREATE_vmrs_imm(dc, Rd, imm) instr_create_1dst_1src((dc), OP_vmrs, (Rd), (imm)) |
Signature: (Rt, imm) | |
| #define | INSTR_CREATE_vmsr_imm(dc, Rt, imm) instr_create_0dst_2src((dc), OP_vmsr, (Rt), (imm)) |
Signature: (imm, Rm) | |
| #define | INSTR_CREATE_msr_priv(dc, imm, Rm) instr_create_0dst_2src((dc), OP_msr_priv, (imm), (Rm)) |
Signature: (imm, imm2) | |
| #define | INSTR_CREATE_cpsid_noflags(dc, imm, imm2) instr_create_0dst_2src((dc), OP_cpsid, (imm), (imm2)) |
| #define | INSTR_CREATE_cpsie_noflags(dc, imm, imm2) instr_create_0dst_2src((dc), OP_cpsie, (imm), (imm2)) |
| #define | INSTR_CREATE_it(dc, imm, imm2) instr_create_0dst_2src((dc), OP_it, (imm), (imm2)) |
Signature: (Rd, Rm_or_imm) | |
| #define | INSTR_CREATE_mov(dc, Rd, Rm_or_imm) instr_create_1dst_1src((dc), OP_mov, (Rd), (Rm_or_imm)) |
| #define | INSTR_CREATE_movs(dc, Rd, Rm_or_imm) instr_create_1dst_1src((dc), OP_movs, (Rd), (Rm_or_imm)) |
| #define | INSTR_CREATE_mvn(dc, Rd, Rm_or_imm) |
| #define | INSTR_CREATE_mvns(dc, Rd, Rm_or_imm) |
Signature: (Rn, Rm_or_imm) | |
| #define | INSTR_CREATE_cmn(dc, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_cmp(dc, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_teq(dc, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_tst(dc, Rn, Rm_or_imm) |
Signature: (Rd, Rm, imm) | |
| #define | INSTR_CREATE_sxtb16(dc, Rd, Rm, imm) instr_create_1dst_2src((dc), OP_sxtb16, (Rd), (Rm), (imm)) |
| #define | INSTR_CREATE_sxtb_imm(dc, Rd, Rm, imm) instr_create_1dst_2src((dc), OP_sxtb, (Rd), (Rm), (imm)) |
| #define | INSTR_CREATE_sxth_imm(dc, Rd, Rm, imm) instr_create_1dst_2src((dc), OP_sxth, (Rd), (Rm), (imm)) |
| #define | INSTR_CREATE_uxtb16(dc, Rd, Rm, imm) instr_create_1dst_2src((dc), OP_uxtb16, (Rd), (Rm), (imm)) |
| #define | INSTR_CREATE_uxtb_imm(dc, Rd, Rm, imm) instr_create_1dst_2src((dc), OP_uxtb, (Rd), (Rm), (imm)) |
| #define | INSTR_CREATE_uxth_imm(dc, Rd, Rm, imm) instr_create_1dst_2src((dc), OP_uxth, (Rd), (Rm), (imm)) |
Signature: (Rd, Rn, imm) | |
| #define | INSTR_CREATE_addw(dc, Rd, Rn, imm) instr_create_1dst_2src((dc), OP_addw, (Rd), (Rn), (imm)) |
| #define | INSTR_CREATE_subw(dc, Rd, Rn, imm) instr_create_1dst_2src((dc), OP_subw, (Rd), (Rn), (imm)) |
Signature: (Rd, imm, Rm) | |
| #define | INSTR_CREATE_ssat16(dc, Rd, imm, Rm) instr_create_1dst_2src((dc), OP_ssat16, (Rd), (imm), (Rm)) |
| #define | INSTR_CREATE_usat16(dc, Rd, imm, Rm) instr_create_1dst_2src((dc), OP_usat16, (Rd), (imm), (Rm)) |
Signature: (Rd, imm, imm2) | |
| #define | INSTR_CREATE_bfc(dc, Rd, imm, imm2) instr_create_1dst_3src((dc), OP_bfc, (Rd), (imm), (imm2), (Rd)) |
Signature: (Rd, Rn, Rm_or_imm) | |
| #define | INSTR_CREATE_adc(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_adcs(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_add(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_adds(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_and(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_ands(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_asr(dc, Rd, Rn, Rm_or_imm) instr_create_1dst_2src((dc), OP_asr, (Rd), (Rn), (Rm_or_imm)) |
| #define | INSTR_CREATE_asrs(dc, Rd, Rn, Rm_or_imm) instr_create_1dst_2src((dc), OP_asrs, (Rd), (Rn), (Rm_or_imm)) |
| #define | INSTR_CREATE_bic(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_bics(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_eor(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_eors(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_lsl(dc, Rd, Rn, Rm_or_imm) instr_create_1dst_2src((dc), OP_lsl, (Rd), (Rn), (Rm_or_imm)) |
| #define | INSTR_CREATE_lsls(dc, Rd, Rn, Rm_or_imm) instr_create_1dst_2src((dc), OP_lsls, (Rd), (Rn), (Rm_or_imm)) |
| #define | INSTR_CREATE_lsr(dc, Rd, Rn, Rm_or_imm) instr_create_1dst_2src((dc), OP_lsr, (Rd), (Rn), (Rm_or_imm)) |
| #define | INSTR_CREATE_lsrs(dc, Rd, Rn, Rm_or_imm) instr_create_1dst_2src((dc), OP_lsrs, (Rd), (Rn), (Rm_or_imm)) |
| #define | INSTR_CREATE_orn(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_orns(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_orr(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_orrs(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_ror(dc, Rd, Rn, Rm_or_imm) instr_create_1dst_2src((dc), OP_ror, (Rd), (Rn), (Rm_or_imm)) |
| #define | INSTR_CREATE_rors(dc, Rd, Rn, Rm_or_imm) instr_create_1dst_2src((dc), OP_rors, (Rd), (Rn), (Rm_or_imm)) |
| #define | INSTR_CREATE_rsb(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_rsbs(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_rsc(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_rscs(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_sbc(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_sbcs(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_sub(dc, Rd, Rn, Rm_or_imm) |
| #define | INSTR_CREATE_subs(dc, Rd, Rn, Rm_or_imm) |
Signature: (Rd, statreg, imm) | |
| #define | INSTR_CREATE_mrs_priv_spsr(dc, Rd, statreg, imm) instr_create_1dst_2src((dc), OP_mrs_priv, (Rd), (statreg), (imm)) |
Signature: (statreg, imm, Rm) | |
| #define | INSTR_CREATE_msr_priv_spsr(dc, statreg, imm, Rm) instr_create_1dst_2src((dc), OP_msr_priv, (statreg), (imm), (Rm)) |
Signature: (statreg, imm, imm2) | |
| #define | INSTR_CREATE_msr_imm(dc, statreg, imm, imm2) instr_create_1dst_2src((dc), OP_msr, (statreg), (imm), (imm2)) |
Signature: (statreg, imm_msr, Rm) | |
| #define | INSTR_CREATE_msr(dc, statreg, imm_msr, Rm) instr_create_1dst_2src((dc), OP_msr, (statreg), (imm_msr), (Rm)) |
Signature: (Rd, Rn, Rm, imm) | |
| #define | INSTR_CREATE_sxtab(dc, Rd, Rn, Rm, imm) instr_create_1dst_3src((dc), OP_sxtab, (Rd), (Rn), (Rm), (imm)) |
| #define | INSTR_CREATE_sxtab16(dc, Rd, Rn, Rm, imm) instr_create_1dst_3src((dc), OP_sxtab16, (Rd), (Rn), (Rm), (imm)) |
| #define | INSTR_CREATE_sxtah(dc, Rd, Rn, Rm, imm) instr_create_1dst_3src((dc), OP_sxtah, (Rd), (Rn), (Rm), (imm)) |
| #define | INSTR_CREATE_uxtab(dc, Rd, Rn, Rm, imm) instr_create_1dst_3src((dc), OP_uxtab, (Rd), (Rn), (Rm), (imm)) |
| #define | INSTR_CREATE_uxtab16(dc, Rd, Rn, Rm, imm) instr_create_1dst_3src((dc), OP_uxtab16, (Rd), (Rn), (Rm), (imm)) |
| #define | INSTR_CREATE_uxtah(dc, Rd, Rn, Rm, imm) instr_create_1dst_3src((dc), OP_uxtah, (Rd), (Rn), (Rm), (imm)) |
Signature: (Rd, Rm, imm, imm2) | |
| #define | INSTR_CREATE_bfi(dc, Rd, Rm, imm, imm2) instr_create_1dst_4src((dc), OP_bfi, (Rd), (Rm), (imm), (imm2), (Rd)) |
| #define | INSTR_CREATE_sbfx(dc, Rd, Rm, imm, imm2) instr_create_1dst_3src((dc), OP_sbfx, (Rd), (Rm), (imm), (imm2)) |
| #define | INSTR_CREATE_ubfx(dc, Rd, Rm, imm, imm2) instr_create_1dst_3src((dc), OP_ubfx, (Rd), (Rm), (imm), (imm2)) |
Signature: (Rd, Rm, shift, Rs) | |
| #define | INSTR_CREATE_mvn_shreg(dc, Rd, Rm, shift, Rs) |
| #define | INSTR_CREATE_mvns_shreg(dc, Rd, Rm, shift, Rs) |
Signature: (Rn, Rm, shift, Rs) | |
| #define | INSTR_CREATE_cmn_shreg(dc, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_cmp_shreg(dc, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_teq_shreg(dc, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_tst_shreg(dc, Rn, Rm, shift, Rs) |
Signature: (Rd, Rn, Rm, shift, Rs) | |
| #define | INSTR_CREATE_adc_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_adcs_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_add_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_adds_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_and_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_ands_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_bic_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_bics_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_eor_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_eors_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_orr_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_orrs_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_rsb_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_rsbs_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_rsc_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_rscs_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_sbc_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_sbcs_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_sub_shreg(dc, Rd, Rn, Rm, shift, Rs) |
| #define | INSTR_CREATE_subs_shreg(dc, Rd, Rn, Rm, shift, Rs) |
Signature: (Rd, Rm, shift, imm) | |
| #define | INSTR_CREATE_mvn_shimm(dc, Rd, Rm, shift, imm) |
| #define | INSTR_CREATE_mvns_shimm(dc, Rd, Rm, shift, imm) |
Signature: (Rn, Rm, shift, imm) | |
| #define | INSTR_CREATE_cmn_shimm(dc, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_cmp_shimm(dc, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_teq_shimm(dc, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_tst_shimm(dc, Rn, Rm, shift, imm) |
Signature: (Rd, Rn, Rm, shift, imm) | |
| #define | INSTR_CREATE_adc_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_adcs_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_add_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_adds_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_and_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_ands_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_bic_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_bics_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_eor_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_eors_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_orn_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_orns_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_orr_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_orrs_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_pkhbt_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_pkhtb_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_rsb_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_rsbs_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_rsc_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_rscs_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_sbc_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_sbcs_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_sub_shimm(dc, Rd, Rn, Rm, shift, imm) |
| #define | INSTR_CREATE_subs_shimm(dc, Rd, Rn, Rm, shift, imm) |
Signature: (Rd, imm, Rm, shift, imm2) | |
| #define | INSTR_CREATE_ssat_shimm(dc, Rd, imm, Rm, shift, imm2) |
| #define | INSTR_CREATE_usat_shimm(dc, Rd, imm, Rm, shift, imm2) |
Signature: (mem) | |
| #define | INSTR_CREATE_pld(dc, mem) instr_create_0dst_1src((dc), OP_pld, (mem)) |
| #define | INSTR_CREATE_pldw(dc, mem) instr_create_0dst_1src((dc), OP_pldw, (mem)) |
| #define | INSTR_CREATE_pli(dc, mem) instr_create_0dst_1src((dc), OP_pli, (mem)) |
| #define | INSTR_CREATE_tbb(dc, mem) instr_create_0dst_1src((dc), OP_tbb, (mem)) |
| #define | INSTR_CREATE_tbh(dc, mem) instr_create_0dst_1src((dc), OP_tbh, (mem)) |
Signature: (Rd, mem) | |
| #define | INSTR_CREATE_lda(dc, Rd, mem) instr_create_1dst_1src((dc), OP_lda, (Rd), (mem)) |
| #define | INSTR_CREATE_ldab(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldab, (Rd), (mem)) |
| #define | INSTR_CREATE_ldaex(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldaex, (Rd), (mem)) |
| #define | INSTR_CREATE_ldaexb(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldaexb, (Rd), (mem)) |
| #define | INSTR_CREATE_ldaexh(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldaexh, (Rd), (mem)) |
| #define | INSTR_CREATE_ldah(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldah, (Rd), (mem)) |
| #define | INSTR_CREATE_ldr(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldr, (Rd), (mem)) |
| #define | INSTR_CREATE_ldrb(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldrb, (Rd), (mem)) |
| #define | INSTR_CREATE_ldrbt(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldrbt, (Rd), (mem)) |
| #define | INSTR_CREATE_ldrex(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldrex, (Rd), (mem)) |
| #define | INSTR_CREATE_ldrexb(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldrexb, (Rd), (mem)) |
| #define | INSTR_CREATE_ldrexh(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldrexh, (Rd), (mem)) |
| #define | INSTR_CREATE_ldrh(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldrh, (Rd), (mem)) |
| #define | INSTR_CREATE_ldrht(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldrht, (Rd), (mem)) |
| #define | INSTR_CREATE_ldrsb(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldrsb, (Rd), (mem)) |
| #define | INSTR_CREATE_ldrsbt(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldrsbt, (Rd), (mem)) |
| #define | INSTR_CREATE_ldrsh(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldrsh, (Rd), (mem)) |
| #define | INSTR_CREATE_ldrsht(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldrsht, (Rd), (mem)) |
| #define | INSTR_CREATE_ldrt(dc, Rd, mem) instr_create_1dst_1src((dc), OP_ldrt, (Rd), (mem)) |
Signature: (mem, Rm) | |
| #define | INSTR_CREATE_stl(dc, mem, Rm) instr_create_1dst_1src((dc), OP_stl, (mem), (Rm)) |
| #define | INSTR_CREATE_stlb(dc, mem, Rm) instr_create_1dst_1src((dc), OP_stlb, (mem), (Rm)) |
| #define | INSTR_CREATE_stlh(dc, mem, Rm) instr_create_1dst_1src((dc), OP_stlh, (mem), (Rm)) |
Signature: (mem, Rt) | |
| #define | INSTR_CREATE_str(dc, mem, Rt) instr_create_1dst_1src((dc), OP_str, (mem), (Rt)) |
| #define | INSTR_CREATE_strb(dc, mem, Rt) instr_create_1dst_1src((dc), OP_strb, (mem), (Rt)) |
| #define | INSTR_CREATE_strbt(dc, mem, Rt) instr_create_1dst_1src((dc), OP_strbt, (mem), (Rt)) |
| #define | INSTR_CREATE_strh(dc, mem, Rt) instr_create_1dst_1src((dc), OP_strh, (mem), (Rt)) |
| #define | INSTR_CREATE_strht(dc, mem, Rt) instr_create_1dst_1src((dc), OP_strht, (mem), (Rt)) |
| #define | INSTR_CREATE_strt(dc, mem, Rt) instr_create_1dst_1src((dc), OP_strt, (mem), (Rt)) |
Signature: (statreg, mem) | |
| #define | INSTR_CREATE_rfe(dc, statreg, mem) instr_create_1dst_1src((dc), OP_rfe, (statreg), (mem)) |
| #define | INSTR_CREATE_rfe_wb(dc, statreg, mem) |
| #define | INSTR_CREATE_rfeda(dc, statreg, mem) instr_create_1dst_1src((dc), OP_rfeda, (statreg), (mem)) |
| #define | INSTR_CREATE_rfeda_wb(dc, statreg, mem) |
| #define | INSTR_CREATE_rfedb(dc, statreg, mem) instr_create_1dst_1src((dc), OP_rfedb, (statreg), (mem)) |
| #define | INSTR_CREATE_rfedb_wb(dc, statreg, mem) |
| #define | INSTR_CREATE_rfeib(dc, statreg, mem) instr_create_1dst_1src((dc), OP_rfeib, (statreg), (mem)) |
| #define | INSTR_CREATE_rfeib_wb(dc, statreg, mem) |
Signature: (Rd, Rd2, mem) | |
| #define | INSTR_CREATE_ldaexd(dc, Rd, Rd2, mem) instr_create_2dst_1src((dc), OP_ldaexd, (Rd), (Rd2), (mem)) |
| #define | INSTR_CREATE_ldrd(dc, Rd, Rd2, mem) instr_create_2dst_1src((dc), OP_ldrd, (Rd), (Rd2), (mem)) |
| #define | INSTR_CREATE_ldrexd(dc, Rd, Rd2, mem) instr_create_2dst_1src((dc), OP_ldrexd, (Rd), (Rd2), (mem)) |
Signature: (Rd, mem, Rm) | |
| #define | INSTR_CREATE_ldrh_wbreg(dc, Rd, mem, Rm) |
| #define | INSTR_CREATE_ldrht_wbreg(dc, Rd, mem, Rm) |
| #define | INSTR_CREATE_ldrsb_wbreg(dc, Rd, mem, Rm) |
| #define | INSTR_CREATE_ldrsbt_wbreg(dc, Rd, mem, Rm) |
| #define | INSTR_CREATE_ldrsh_wbreg(dc, Rd, mem, Rm) |
| #define | INSTR_CREATE_ldrsht_wbreg(dc, Rd, mem, Rm) |
| #define | INSTR_CREATE_swp(dc, Rd, mem, Rm) instr_create_2dst_2src((dc), OP_swp, (mem), (Rd), (mem), (Rm)) |
| #define | INSTR_CREATE_swpb(dc, Rd, mem, Rm) instr_create_2dst_2src((dc), OP_swpb, (mem), (Rd), (mem), (Rm)) |
Signature: (mem, Rd, Rm) | |
| #define | INSTR_CREATE_stlex(dc, mem, Rd, Rm) instr_create_2dst_1src((dc), OP_stlex, (mem), (Rd), (Rm)) |
| #define | INSTR_CREATE_stlexb(dc, mem, Rd, Rm) instr_create_2dst_1src((dc), OP_stlexb, (mem), (Rd), (Rm)) |
| #define | INSTR_CREATE_stlexh(dc, mem, Rd, Rm) instr_create_2dst_1src((dc), OP_stlexh, (mem), (Rd), (Rm)) |
| #define | INSTR_CREATE_strex(dc, mem, Rd, Rm) instr_create_2dst_1src((dc), OP_strex, (mem), (Rd), (Rm)) |
| #define | INSTR_CREATE_strexb(dc, mem, Rd, Rm) instr_create_2dst_1src((dc), OP_strexb, (mem), (Rd), (Rm)) |
| #define | INSTR_CREATE_strexh(dc, mem, Rd, Rm) instr_create_2dst_1src((dc), OP_strexh, (mem), (Rd), (Rm)) |
Signature: (mem, Rt, Rm) | |
| #define | INSTR_CREATE_strh_wbreg(dc, mem, Rt, Rm) |
| #define | INSTR_CREATE_strht_wbreg(dc, mem, Rt, Rm) |
Signature: (mem, Rt, Rt2) | |
| #define | INSTR_CREATE_strd(dc, mem, Rt, Rt2) instr_create_1dst_2src((dc), OP_strd, (mem), (Rt), (Rt2)) |
Signature: (Rd, Rd2, mem, Rm) | |
| #define | INSTR_CREATE_ldrd_wbreg(dc, Rd, Rd2, mem, Rm) |
Signature: (mem, Rd, Rt, Rt2) | |
| #define | INSTR_CREATE_stlexd(dc, mem, Rd, Rt, Rt2) instr_create_2dst_2src((dc), OP_stlexd, (mem), (Rd), (Rt), (Rt2)) |
| #define | INSTR_CREATE_strexd(dc, mem, Rd, Rt, Rt2) instr_create_2dst_2src((dc), OP_strexd, (mem), (Rd), (Rt), (Rt2)) |
Signature: (mem, Rt, Rt2, Rm) | |
| #define | INSTR_CREATE_strd_wbreg(dc, mem, Rt, Rt2, Rm) |
Signature: (Rd, mem, imm) | |
| #define | INSTR_CREATE_ldr_wbimm(dc, Rd, mem, imm) |
| #define | INSTR_CREATE_ldrb_wbimm(dc, Rd, mem, imm) |
| #define | INSTR_CREATE_ldrbt_wbimm(dc, Rd, mem, imm) |
| #define | INSTR_CREATE_ldrh_wbimm(dc, Rd, mem, imm) |
| #define | INSTR_CREATE_ldrht_wbimm(dc, Rd, mem, imm) |
| #define | INSTR_CREATE_ldrsb_wbimm(dc, Rd, mem, imm) |
| #define | INSTR_CREATE_ldrsbt_wbimm(dc, Rd, mem, imm) |
| #define | INSTR_CREATE_ldrsh_wbimm(dc, Rd, mem, imm) |
| #define | INSTR_CREATE_ldrsht_wbimm(dc, Rd, mem, imm) |
| #define | INSTR_CREATE_ldrt_wbimm(dc, Rd, mem, imm) |
Signature: (mem, Rt, imm) | |
| #define | INSTR_CREATE_str_wbimm(dc, mem, Rt, imm) |
| #define | INSTR_CREATE_strb_wbimm(dc, mem, Rt, imm) |
| #define | INSTR_CREATE_strbt_wbimm(dc, mem, Rt, imm) |
| #define | INSTR_CREATE_strh_wbimm(dc, mem, Rt, imm) |
| #define | INSTR_CREATE_strht_wbimm(dc, mem, Rt, imm) |
| #define | INSTR_CREATE_strt_wbimm(dc, mem, Rt, imm) |
Signature: (mem, imm, statreg) | |
| #define | INSTR_CREATE_srs(dc, mem, imm, statreg) |
| #define | INSTR_CREATE_srs_wbimm(dc, mem, imm, statreg) |
| #define | INSTR_CREATE_srsda(dc, mem, imm, statreg) |
| #define | INSTR_CREATE_srsda_wbimm(dc, mem, imm, statreg) |
| #define | INSTR_CREATE_srsdb(dc, mem, imm, statreg) |
| #define | INSTR_CREATE_srsdb_wbimm(dc, mem, imm, statreg) |
| #define | INSTR_CREATE_srsib(dc, mem, imm, statreg) |
| #define | INSTR_CREATE_srsib_wbimm(dc, mem, imm, statreg) |
Signature: (Rd, Rd2, mem, imm) | |
| #define | INSTR_CREATE_ldrd_wbimm(dc, Rd, Rd2, mem, imm) |
Signature: (mem, Rt, Rt2, imm) | |
| #define | INSTR_CREATE_strd_wbimm(dc, mem, Rt, Rt2, imm) |
Signature: (Rd, mem, Rm, shift, imm) | |
| #define | INSTR_CREATE_ldr_wbreg(dc, Rd, mem, Rm, shift, imm) |
| #define | INSTR_CREATE_ldrb_wbreg(dc, Rd, mem, Rm, shift, imm) |
| #define | INSTR_CREATE_ldrbt_wbreg(dc, Rd, mem, Rm, shift, imm) |
| #define | INSTR_CREATE_ldrt_wbreg(dc, Rd, mem, Rm, shift, imm) |
Signature: (mem, Rt, Rm, shift, imm) | |
| #define | INSTR_CREATE_str_wbreg(dc, mem, Rt, Rm, shift, imm) |
| #define | INSTR_CREATE_strb_wbreg(dc, mem, Rt, Rm, shift, imm) |
| #define | INSTR_CREATE_strbt_wbreg(dc, mem, Rt, Rm, shift, imm) |
| #define | INSTR_CREATE_strt_wbreg(dc, mem, Rt, Rm, shift, imm) |
Signature: (mem, list_len, ...) | |
| #define | INSTR_CREATE_ldm(dc, mem, list_len, ...) instr_create_Ndst_Msrc_vardst((dc), OP_ldm, 0, 1, list_len, 0, (mem), __VA_ARGS__) |
| #define | INSTR_CREATE_ldm_priv(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_ldm_priv_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_ldm_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_ldmda(dc, mem, list_len, ...) instr_create_Ndst_Msrc_vardst((dc), OP_ldmda, 0, 1, list_len, 0, (mem), __VA_ARGS__) |
| #define | INSTR_CREATE_ldmda_priv(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_ldmda_priv_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_ldmda_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_ldmdb(dc, mem, list_len, ...) instr_create_Ndst_Msrc_vardst((dc), OP_ldmdb, 0, 1, list_len, 0, (mem), __VA_ARGS__) |
| #define | INSTR_CREATE_ldmdb_priv(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_ldmdb_priv_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_ldmdb_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_ldmib(dc, mem, list_len, ...) instr_create_Ndst_Msrc_vardst((dc), OP_ldmib, 0, 1, list_len, 0, (mem), __VA_ARGS__) |
| #define | INSTR_CREATE_ldmib_priv(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_ldmib_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_stm(dc, mem, list_len, ...) instr_create_Ndst_Msrc_varsrc((dc), OP_stm, 1, 0, list_len, 0, (mem), __VA_ARGS__) |
| #define | INSTR_CREATE_stm_priv(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_stm_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_stmda(dc, mem, list_len, ...) instr_create_Ndst_Msrc_varsrc((dc), OP_stmda, 1, 0, list_len, 0, (mem), __VA_ARGS__) |
| #define | INSTR_CREATE_stmda_priv(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_stmda_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_stmdb(dc, mem, list_len, ...) instr_create_Ndst_Msrc_varsrc((dc), OP_stmdb, 1, 0, list_len, 0, (mem), __VA_ARGS__) |
| #define | INSTR_CREATE_stmdb_priv(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_stmdb_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_stmib(dc, mem, list_len, ...) instr_create_Ndst_Msrc_varsrc((dc), OP_stmib, 1, 0, list_len, 0, (mem), __VA_ARGS__) |
| #define | INSTR_CREATE_stmib_priv(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_stmib_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_vld1_dup_8(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_vld1_dup_8_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_vld2_dup_8(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_vld2_dup_8_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_vld3_dup_8(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_vld3_dup_8_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_vld4_dup_8(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_vld4_dup_8_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_vldm(dc, mem, list_len, ...) instr_create_Ndst_Msrc_vardst((dc), OP_vldm, 0, 1, list_len, 0, (mem), __VA_ARGS__) |
| #define | INSTR_CREATE_vldm_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_vldmdb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_vstm(dc, mem, list_len, ...) instr_create_Ndst_Msrc_varsrc((dc), OP_vstm, 1, 0, list_len, 0, (mem), __VA_ARGS__) |
| #define | INSTR_CREATE_vstm_wb(dc, mem, list_len, ...) |
| #define | INSTR_CREATE_vstmdb(dc, mem, list_len, ...) |
Signature: (mem, Rm, list_len, ...) | |
| #define | INSTR_CREATE_vld1_dup_8_wbreg(dc, mem, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld2_dup_8_wbreg(dc, mem, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld3_dup_8_wbreg(dc, mem, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld4_dup_8_wbreg(dc, mem, Rm, list_len, ...) |
Signature: (mem, imm, list_len, ...) | |
| #define | INSTR_CREATE_vld1_16(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld1_16_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld1_32(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld1_32_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld1_64(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld1_64_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld1_8(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld1_8_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld1_dup_16(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld1_dup_16_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld1_dup_32(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld1_dup_32_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld2_16(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld2_16_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld2_32(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld2_32_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld2_8(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld2_8_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld2_dup_16(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld2_dup_16_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld2_dup_32(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld2_dup_32_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld2_lane_8(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld2_lane_8_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld3_16(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld3_16_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld3_32(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld3_32_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld3_8(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld3_8_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld3_dup_16(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld3_dup_16_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld3_dup_32(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld3_dup_32_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld3_lane_8(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld3_lane_8_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld4_16(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld4_16_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld4_32(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld4_32_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld4_8(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld4_8_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld4_dup_16(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld4_dup_16_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld4_dup_32(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld4_dup_32_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld4_lane_8(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vld4_lane_8_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst1_16(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst1_16_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst1_32(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst1_32_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst1_64(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst1_64_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst1_8(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst1_8_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst2_16(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst2_16_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst2_32(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst2_32_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst2_8(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst2_8_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst3_16(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst3_16_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst3_32(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst3_32_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst3_8(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst3_8_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst3_lane_16(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst3_lane_16_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst3_lane_32(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst3_lane_32_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst3_lane_8(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst3_lane_8_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst4_16(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst4_16_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst4_32(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst4_32_wbimm(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst4_8(dc, mem, imm, list_len, ...) |
| #define | INSTR_CREATE_vst4_8_wbimm(dc, mem, imm, list_len, ...) |
Signature: (mem, imm, Rm, list_len, ...) | |
| #define | INSTR_CREATE_vld1_16_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld1_32_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld1_64_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld1_8_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld1_dup_16_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld1_dup_32_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld2_16_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld2_32_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld2_8_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld2_dup_16_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld2_dup_32_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld2_lane_8_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld3_16_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld3_32_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld3_8_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld3_dup_16_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld3_dup_32_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld3_lane_8_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld4_16_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld4_32_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld4_8_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld4_dup_16_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld4_dup_32_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld4_lane_8_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst1_16_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst1_32_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst1_64_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst1_8_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst2_16_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst2_32_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst2_8_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst3_16_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst3_32_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst3_8_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst3_lane_16_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst3_lane_32_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst3_lane_8_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst4_16_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst4_32_wbreg(dc, mem, imm, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst4_8_wbreg(dc, mem, imm, Rm, list_len, ...) |
Signature: (mem, imm, imm2, list_len, ...) | |
| #define | INSTR_CREATE_vld2_lane_16(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vld2_lane_16_wbimm(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vld2_lane_32(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vld2_lane_32_wbimm(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vld3_lane_16(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vld3_lane_16_wbimm(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vld3_lane_32(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vld3_lane_32_wbimm(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vld4_lane_16(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vld4_lane_16_wbimm(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vld4_lane_32(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vld4_lane_32_wbimm(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vst2_lane_16(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vst2_lane_16_wbimm(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vst2_lane_32(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vst2_lane_32_wbimm(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vst2_lane_8(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vst2_lane_8_wbimm(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vst4_lane_16(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vst4_lane_16_wbimm(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vst4_lane_32(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vst4_lane_32_wbimm(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vst4_lane_8(dc, mem, imm, imm2, list_len, ...) |
| #define | INSTR_CREATE_vst4_lane_8_wbimm(dc, mem, imm, imm2, list_len, ...) |
Signature: (mem, imm, imm2, Rm, list_len, ...) | |
| #define | INSTR_CREATE_vld2_lane_16_wbreg(dc, mem, imm, imm2, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld2_lane_32_wbreg(dc, mem, imm, imm2, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld3_lane_16_wbreg(dc, mem, imm, imm2, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld3_lane_32_wbreg(dc, mem, imm, imm2, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld4_lane_16_wbreg(dc, mem, imm, imm2, Rm, list_len, ...) |
| #define | INSTR_CREATE_vld4_lane_32_wbreg(dc, mem, imm, imm2, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst2_lane_16_wbreg(dc, mem, imm, imm2, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst2_lane_32_wbreg(dc, mem, imm, imm2, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst2_lane_8_wbreg(dc, mem, imm, imm2, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst4_lane_16_wbreg(dc, mem, imm, imm2, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst4_lane_32_wbreg(dc, mem, imm, imm2, Rm, list_len, ...) |
| #define | INSTR_CREATE_vst4_lane_8_wbreg(dc, mem, imm, imm2, Rm, list_len, ...) |
Signature: (Ra, Rd, imm, imm2, cpreg) | |
| #define | INSTR_CREATE_mrrc(dc, Ra, Rd, imm, imm2, cpreg) instr_create_2dst_3src((dc), OP_mrrc, (Ra), (Rd), (imm), (imm2), (cpreg)) |
| #define | INSTR_CREATE_mrrc2(dc, Ra, Rd, imm, imm2, cpreg) instr_create_2dst_3src((dc), OP_mrrc2, (Ra), (Rd), (imm), (imm2), (cpreg)) |
Signature: (cpreg, Rn, Rt, imm, imm2) | |
| #define | INSTR_CREATE_mcrr(dc, cpreg, Rn, Rt, imm, imm2) instr_create_1dst_4src((dc), OP_mcrr, (cpreg), (Rn), (Rt), (imm), (imm2)) |
| #define | INSTR_CREATE_mcrr2(dc, cpreg, Rn, Rt, imm, imm2) instr_create_1dst_4src((dc), OP_mcrr2, (cpreg), (Rn), (Rt), (imm), (imm2)) |
Signature: (cpreg, cpreg2, imm, imm2, Rt) | |
| #define | INSTR_CREATE_mcr2(dc, cpreg, cpreg2, imm, imm2, Rt) instr_create_2dst_3src((dc), OP_mcr2, (cpreg), (cpreg2), (imm), (imm2), (Rt)) |
Signature: (cpreg, imm, imm2, cpreg2, cpreg3) | |
| #define | INSTR_CREATE_cdp2(dc, cpreg, imm, imm2, cpreg2, cpreg3) instr_create_1dst_4src((dc), OP_cdp2, (cpreg), (imm), (imm2), (cpreg2), (cpreg3)) |
Signature: (Rd, imm, imm2, cpreg, cpreg2, imm3) | |
| #define | INSTR_CREATE_mrc(dc, Rd, imm, imm2, cpreg, cpreg2, imm3) instr_create_1dst_5src((dc), OP_mrc, (Rd), (imm), (imm2), (cpreg), (cpreg2), (imm3)) |
| #define | INSTR_CREATE_mrc2(dc, Rd, imm, imm2, cpreg, cpreg2, imm3) instr_create_1dst_5src((dc), OP_mrc2, (Rd), (imm), (imm2), (cpreg), (cpreg2), (imm3)) |
Signature: (cpreg, cpreg2, imm, imm2, Rt, imm3) | |
| #define | INSTR_CREATE_mcr(dc, cpreg, cpreg2, imm, imm2, Rt, imm3) instr_create_2dst_4src((dc), OP_mcr, (cpreg), (cpreg2), (imm), (imm2), (Rt), (imm3)) |
Signature: (cpreg, imm, imm2, cpreg2, cpreg3, imm3) | |
| #define | INSTR_CREATE_cdp(dc, cpreg, imm, imm2, cpreg2, cpreg3, imm3) |
Signature: (cpreg, mem, imm) | |
| #define | INSTR_CREATE_ldc(dc, cpreg, mem, imm) instr_create_1dst_2src((dc), OP_ldc, (cpreg), (mem), (imm)) |
| #define | INSTR_CREATE_ldcl(dc, cpreg, mem, imm) instr_create_1dst_2src((dc), OP_ldcl, (cpreg), (mem), (imm)) |
Signature: (mem, imm, cpreg, imm2) | |
| #define | INSTR_CREATE_stc(dc, mem, imm, cpreg, imm2) instr_create_1dst_3src((dc), OP_stc, (mem), (imm), (cpreg), (imm2)) |
| #define | INSTR_CREATE_stc2(dc, mem, imm, cpreg, imm2) instr_create_1dst_3src((dc), OP_stc2, (mem), (imm), (cpreg), (imm2)) |
| #define | INSTR_CREATE_stc2_wbimm(dc, mem, imm, cpreg, imm2) |
| #define | INSTR_CREATE_stc2l(dc, mem, imm, cpreg, imm2) instr_create_1dst_3src((dc), OP_stc2l, (mem), (imm), (cpreg), (imm2)) |
| #define | INSTR_CREATE_stc2l_wbimm(dc, mem, imm, cpreg, imm2) |
| #define | INSTR_CREATE_stc_wbimm(dc, mem, imm, cpreg, imm2) |
| #define | INSTR_CREATE_stcl(dc, mem, imm, cpreg, imm2) instr_create_1dst_3src((dc), OP_stcl, (mem), (imm), (cpreg), (imm2)) |
| #define | INSTR_CREATE_stcl_wbimm(dc, mem, imm, cpreg, imm2) |
Signature: (cpreg, mem, imm, imm2) | |
| #define | INSTR_CREATE_ldc2_option(dc, cpreg, mem, imm, imm2) instr_create_1dst_3src((dc), OP_ldc2, (cpreg), (mem), (imm), (imm2)) |
| #define | INSTR_CREATE_ldc2_wbimm(dc, cpreg, mem, imm, imm2) |
| #define | INSTR_CREATE_ldc2l_option(dc, cpreg, mem, imm, imm2) instr_create_1dst_3src((dc), OP_ldc2l, (cpreg), (mem), (imm), (imm2)) |
| #define | INSTR_CREATE_ldc2l_wbimm(dc, cpreg, mem, imm, imm2) |
| #define | INSTR_CREATE_ldc_option(dc, cpreg, mem, imm, imm2) instr_create_1dst_3src((dc), OP_ldc, (cpreg), (mem), (imm), (imm2)) |
| #define | INSTR_CREATE_ldc_wbimm(dc, cpreg, mem, imm, imm2) |
| #define | INSTR_CREATE_ldcl_option(dc, cpreg, mem, imm, imm2) instr_create_1dst_3src((dc), OP_ldcl, (cpreg), (mem), (imm), (imm2)) |
| #define | INSTR_CREATE_ldcl_wbimm(dc, cpreg, mem, imm, imm2) |
Signature: (Rd, Vn) | |
| #define | INSTR_CREATE_vmov_s2g(dc, Rd, Vn) instr_create_1dst_1src((dc), OP_vmov, (Rd), (Vn)) |
Signature: (Vd, Vm) | |
| #define | INSTR_CREATE_aesd_8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_aesd_8, (Vd), (Vm)) |
| #define | INSTR_CREATE_aese_8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_aese_8, (Vd), (Vm)) |
| #define | INSTR_CREATE_aesimc_8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_aesimc_8, (Vd), (Vm)) |
| #define | INSTR_CREATE_aesmc_8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_aesmc_8, (Vd), (Vm)) |
| #define | INSTR_CREATE_sha1h_32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_sha1h_32, (Vd), (Vm)) |
| #define | INSTR_CREATE_sha1su1_32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_sha1su1_32, (Vd), (Vm)) |
| #define | INSTR_CREATE_sha256su0_32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_sha256su0_32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vabs_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vabs_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vabs_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vabs_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vabs_s16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vabs_s16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vabs_s32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vabs_s32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vabs_s8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vabs_s8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcls_s16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcls_s16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcls_s32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcls_s32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcls_s8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcls_s8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vclz_i16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vclz_i16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vclz_i32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vclz_i32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vclz_i8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vclz_i8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcnt_8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcnt_8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvt_f16_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvt_f16_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvt_f32_f16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvt_f32_f16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvt_f32_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvt_f32_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvt_f32_s32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvt_f32_s32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvt_f32_u32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvt_f32_u32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvt_f64_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvt_f64_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvt_f64_s32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvt_f64_s32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvt_f64_u32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvt_f64_u32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvt_s32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvt_s32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvt_s32_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvt_s32_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvt_u32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvt_u32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvt_u32_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvt_u32_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvta_s32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvta_s32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvta_s32_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvta_s32_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvta_u32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvta_u32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvta_u32_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvta_u32_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtb_f16_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtb_f16_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtb_f16_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtb_f16_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtb_f32_f16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtb_f32_f16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtb_f64_f16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtb_f64_f16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtm_s32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtm_s32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtm_s32_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtm_s32_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtm_u32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtm_u32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtm_u32_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtm_u32_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtn_s32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtn_s32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtn_s32_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtn_s32_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtn_u32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtn_u32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtn_u32_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtn_u32_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtp_s32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtp_s32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtp_s32_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtp_s32_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtp_u32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtp_u32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtp_u32_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtp_u32_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtr_s32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtr_s32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtr_s32_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtr_s32_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtr_u32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtr_u32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtr_u32_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtr_u32_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtt_f16_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtt_f16_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtt_f16_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtt_f16_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtt_f32_f16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtt_f32_f16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vcvtt_f64_f16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vcvtt_f64_f16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vmovl_s16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vmovl_s16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vmovl_s32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vmovl_s32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vmovl_s8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vmovl_s8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vmovl_u16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vmovl_u16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vmovl_u32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vmovl_u32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vmovl_u8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vmovl_u8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vmovn_i16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vmovn_i16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vmovn_i32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vmovn_i32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vmovn_i64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vmovn_i64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vmvn(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vmvn, (Vd), (Vm)) |
| #define | INSTR_CREATE_vneg_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vneg_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vneg_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vneg_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vneg_s16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vneg_s16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vneg_s32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vneg_s32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vneg_s8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vneg_s8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vpadal_s16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vpadal_s16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vpadal_s32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vpadal_s32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vpadal_s8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vpadal_s8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vpadal_u16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vpadal_u16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vpadal_u32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vpadal_u32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vpadal_u8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vpadal_u8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vpaddl_s16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vpaddl_s16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vpaddl_s32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vpaddl_s32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vpaddl_s8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vpaddl_s8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vpaddl_u16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vpaddl_u16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vpaddl_u32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vpaddl_u32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vpaddl_u8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vpaddl_u8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vqabs_s16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vqabs_s16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vqabs_s32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vqabs_s32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vqabs_s8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vqabs_s8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vqmovn_s16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vqmovn_s16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vqmovn_s32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vqmovn_s32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vqmovn_s64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vqmovn_s64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vqmovn_u16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vqmovn_u16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vqmovn_u32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vqmovn_u32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vqmovn_u64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vqmovn_u64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vqmovun_s16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vqmovun_s16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vqmovun_s32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vqmovun_s32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vqmovun_s64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vqmovun_s64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vqneg_s16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vqneg_s16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vqneg_s32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vqneg_s32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vqneg_s8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vqneg_s8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrecpe_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrecpe_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrecpe_u32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrecpe_u32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrev16_16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrev16_16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrev16_8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrev16_8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrev32_16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrev32_16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrev32_32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrev32_32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrev32_8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrev32_8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrev64_16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrev64_16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrev64_32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrev64_32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrev64_8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrev64_8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrinta_f32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrinta_f32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrinta_f64_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrinta_f64_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrintm_f32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrintm_f32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrintm_f64_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrintm_f64_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrintn_f32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrintn_f32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrintn_f64_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrintn_f64_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrintp_f32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrintp_f32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrintp_f64_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrintp_f64_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrintr_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrintr_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrintr_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrintr_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrintx_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrintx_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrintx_f32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrintx_f32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrintx_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrintx_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrintz_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrintz_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrintz_f32_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrintz_f32_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrintz_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrintz_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrsqrte_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrsqrte_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vrsqrte_u32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vrsqrte_u32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vsqrt_f32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vsqrt_f32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vsqrt_f64(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vsqrt_f64, (Vd), (Vm)) |
| #define | INSTR_CREATE_vswp(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vswp, (Vd), (Vm)) |
| #define | INSTR_CREATE_vtrn_16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vtrn_16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vtrn_32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vtrn_32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vtrn_8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vtrn_8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vuzp_16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vuzp_16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vuzp_32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vuzp_32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vuzp_8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vuzp_8, (Vd), (Vm)) |
| #define | INSTR_CREATE_vzip_16(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vzip_16, (Vd), (Vm)) |
| #define | INSTR_CREATE_vzip_32(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vzip_32, (Vd), (Vm)) |
| #define | INSTR_CREATE_vzip_8(dc, Vd, Vm) instr_create_1dst_1src((dc), OP_vzip_8, (Vd), (Vm)) |
Signature: (Vd, Rt) | |
| #define | INSTR_CREATE_vdup_16(dc, Vd, Rt) instr_create_1dst_1src((dc), OP_vdup_16, (Vd), (Rt)) |
| #define | INSTR_CREATE_vdup_32(dc, Vd, Rt) instr_create_1dst_1src((dc), OP_vdup_32, (Vd), (Rt)) |
| #define | INSTR_CREATE_vdup_8(dc, Vd, Rt) instr_create_1dst_1src((dc), OP_vdup_8, (Vd), (Rt)) |
| #define | INSTR_CREATE_vmov_g2s(dc, Vd, Rt) instr_create_1dst_1src((dc), OP_vmov, (Vd), (Rt)) |
Signature: (Ra, Rd, Vm) | |
| #define | INSTR_CREATE_vmov_s2gg(dc, Ra, Rd, Vm) instr_create_2dst_1src((dc), OP_vmov, (Ra), (Rd), (Vm)) |
Signature: (Vd, Vn, Vm) | |
| #define | INSTR_CREATE_sha1c_32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_sha1c_32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_sha1m_32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_sha1m_32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_sha1p_32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_sha1p_32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_sha1su0_32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_sha1su0_32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_sha256h2_32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_sha256h2_32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_sha256h_32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_sha256h_32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_sha256su1_32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_sha256su1_32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaba_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaba_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaba_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaba_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaba_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaba_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaba_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaba_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaba_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaba_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaba_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaba_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabal_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabal_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabal_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabal_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabal_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabal_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabal_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabal_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabal_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabal_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabal_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabal_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabd_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabd_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabd_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabd_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabd_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabd_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabd_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabd_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabd_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabd_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabd_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabd_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabdl_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabdl_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabdl_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabdl_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabdl_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabdl_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabdl_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabdl_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabdl_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabdl_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vabdl_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vabdl_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vacge_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vacge_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vacgt_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vacgt_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vadd_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vadd_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vadd_f64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vadd_f64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vadd_i16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vadd_i16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vadd_i32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vadd_i32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vadd_i64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vadd_i64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vadd_i8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vadd_i8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaddhn_i16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaddhn_i16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaddhn_i32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaddhn_i32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaddhn_i64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaddhn_i64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaddl_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaddl_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaddl_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaddl_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaddl_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaddl_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaddl_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaddl_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaddl_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaddl_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaddl_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaddl_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaddw_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaddw_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaddw_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaddw_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaddw_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaddw_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaddw_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaddw_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaddw_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaddw_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vaddw_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vaddw_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vand(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vand, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vbic(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vbic, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vbif(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vbif, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vbit(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vbit, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vbsl(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vbsl, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vcge_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vcge_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vcge_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vcge_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vcge_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vcge_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vcgt_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vcgt_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vcgt_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vcgt_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vcgt_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vcgt_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vdiv_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vdiv_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vdiv_f64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vdiv_f64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_veor(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_veor, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vfma_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vfma_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vfma_f64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vfma_f64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vfms_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vfms_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vfms_f64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vfms_f64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vfnma_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vfnma_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vfnma_f64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vfnma_f64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vfnms_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vfnms_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vfnms_f64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vfnms_f64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vhadd_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vhadd_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vhadd_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vhadd_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vhadd_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vhadd_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vhadd_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vhadd_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vhadd_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vhadd_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vhadd_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vhadd_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vhsub_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vhsub_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vhsub_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vhsub_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vhsub_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vhsub_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vhsub_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vhsub_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vhsub_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vhsub_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vhsub_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vhsub_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmax_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmax_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmax_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmax_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmax_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmax_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmax_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmax_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmax_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmax_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmax_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmax_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmax_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmax_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmaxnm_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmaxnm_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmaxnm_f64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmaxnm_f64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmin_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmin_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmin_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmin_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmin_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmin_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmin_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmin_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmin_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmin_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmin_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmin_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmin_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmin_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vminnm_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vminnm_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vminnm_f64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vminnm_f64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmla_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmla_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmla_f64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmla_f64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmla_i16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmla_i16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmla_i32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmla_i32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmla_i8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmla_i8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmlal_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmlal_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmlal_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmlal_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmlal_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmlal_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmlal_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmlal_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmlal_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmlal_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmlal_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmlal_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmls_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmls_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmls_f64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmls_f64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmls_i16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmls_i16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmls_i32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmls_i32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmls_i8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmls_i8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmlsl_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmlsl_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmlsl_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmlsl_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmlsl_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmlsl_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmlsl_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmlsl_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmlsl_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmlsl_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmlsl_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmlsl_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmul_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmul_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmul_f64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmul_f64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmul_i16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmul_i16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmul_i32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmul_i32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmul_i8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmul_i8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmul_p32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmul_p32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmul_p8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmul_p8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmull_p32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmull_p32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmull_p8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmull_p8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmull_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmull_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmull_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmull_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmull_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmull_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmull_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmull_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmull_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmull_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vmull_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vmull_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vnmla_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vnmla_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vnmla_f64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vnmla_f64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vnmls_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vnmls_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vnmls_f64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vnmls_f64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vnmul_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vnmul_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vnmul_f64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vnmul_f64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vorn(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vorn, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vorr(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vorr, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpadd_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpadd_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpadd_i16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpadd_i16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpadd_i32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpadd_i32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpadd_i8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpadd_i8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpmax_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpmax_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpmax_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpmax_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpmax_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpmax_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpmax_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpmax_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpmax_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpmax_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpmax_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpmax_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpmax_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpmax_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpmin_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpmin_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpmin_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpmin_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpmin_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpmin_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpmin_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpmin_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpmin_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpmin_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpmin_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpmin_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vpmin_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vpmin_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqadd_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqadd_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqadd_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqadd_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqadd_s64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqadd_s64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqadd_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqadd_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqadd_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqadd_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqadd_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqadd_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqadd_u64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqadd_u64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqadd_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqadd_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqdmlal_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqdmlal_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqdmlal_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqdmlal_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqdmlsl_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqdmlsl_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqdmlsl_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqdmlsl_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqdmulh_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqdmulh_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqdmulh_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqdmulh_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqdmull_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqdmull_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqdmull_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqdmull_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqrdmulh_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqrdmulh_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqrdmulh_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqrdmulh_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqrshl_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqrshl_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqrshl_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqrshl_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqrshl_s64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqrshl_s64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqrshl_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqrshl_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqrshl_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqrshl_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqrshl_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqrshl_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqrshl_u64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqrshl_u64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqrshl_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqrshl_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqsub_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqsub_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqsub_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqsub_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqsub_s64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqsub_s64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqsub_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqsub_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqsub_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqsub_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqsub_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqsub_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqsub_u64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqsub_u64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vqsub_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vqsub_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vraddhn_i16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vraddhn_i16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vraddhn_i32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vraddhn_i32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vraddhn_i64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vraddhn_i64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrecps_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrecps_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrhadd_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrhadd_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrhadd_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrhadd_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrhadd_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrhadd_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrhadd_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrhadd_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrhadd_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrhadd_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrhadd_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrhadd_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrshl_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrshl_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrshl_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrshl_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrshl_s64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrshl_s64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrshl_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrshl_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrshl_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrshl_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrshl_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrshl_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrshl_u64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrshl_u64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrshl_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrshl_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrsqrts_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrsqrts_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrsubhn_i16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrsubhn_i16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrsubhn_i32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrsubhn_i32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vrsubhn_i64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vrsubhn_i64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vshl_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vshl_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vshl_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vshl_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vshl_s64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vshl_s64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vshl_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vshl_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vshl_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vshl_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vshl_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vshl_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vshl_u64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vshl_u64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vshl_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vshl_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsub_f32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsub_f32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsub_f64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsub_f64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsub_i16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsub_i16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsub_i32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsub_i32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsub_i64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsub_i64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsub_i8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsub_i8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsubhn_i16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsubhn_i16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsubhn_i32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsubhn_i32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsubhn_i64(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsubhn_i64, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsubl_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsubl_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsubl_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsubl_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsubl_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsubl_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsubl_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsubl_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsubl_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsubl_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsubl_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsubl_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsubw_s16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsubw_s16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsubw_s32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsubw_s32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsubw_s8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsubw_s8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsubw_u16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsubw_u16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsubw_u32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsubw_u32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsubw_u8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vsubw_u8, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vtst_16(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vtst_16, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vtst_32(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vtst_32, (Vd), (Vn), (Vm)) |
| #define | INSTR_CREATE_vtst_8(dc, Vd, Vn, Vm) instr_create_1dst_2src((dc), OP_vtst_8, (Vd), (Vn), (Vm)) |
Signature: (Vd, Rt, Rt2) | |
| #define | INSTR_CREATE_vmov_gg2s(dc, Vd, Rt, Rt2) instr_create_1dst_2src((dc), OP_vmov, (Vd), (Rt), (Rt2)) |
Signature: (Rd, Rd2, Vt, Vt2) | |
| #define | INSTR_CREATE_vmov_ss2gg(dc, Rd, Rd2, Vt, Vt2) instr_create_2dst_2src((dc), OP_vmov, (Rd), (Rd2), (Vt), (Vt2)) |
Signature: (Vd, Vd2, Rt, Rt2) | |
| #define | INSTR_CREATE_vmov_gg2ss(dc, Vd, Vd2, Rt, Rt2) instr_create_2dst_2src((dc), OP_vmov, (Vd), (Vd2), (Rt), (Rt2)) |
Signature: (Vd, imm) | |
| #define | INSTR_CREATE_vbic_i16(dc, Vd, imm) instr_create_1dst_1src((dc), OP_vbic_i16, (Vd), (imm)) |
| #define | INSTR_CREATE_vbic_i32(dc, Vd, imm) instr_create_1dst_1src((dc), OP_vbic_i32, (Vd), (imm)) |
| #define | INSTR_CREATE_vmov_i16(dc, Vd, imm) instr_create_1dst_1src((dc), OP_vmov_i16, (Vd), (imm)) |
| #define | INSTR_CREATE_vmov_i32(dc, Vd, imm) instr_create_1dst_1src((dc), OP_vmov_i32, (Vd), (imm)) |
| #define | INSTR_CREATE_vmov_i64(dc, Vd, imm) instr_create_1dst_1src((dc), OP_vmov_i64, (Vd), (imm)) |
| #define | INSTR_CREATE_vmov_i8(dc, Vd, imm) instr_create_1dst_1src((dc), OP_vmov_i8, (Vd), (imm)) |
| #define | INSTR_CREATE_vmvn_i16(dc, Vd, imm) instr_create_1dst_1src((dc), OP_vmvn_i16, (Vd), (imm)) |
| #define | INSTR_CREATE_vmvn_i32(dc, Vd, imm) instr_create_1dst_1src((dc), OP_vmvn_i32, (Vd), (imm)) |
| #define | INSTR_CREATE_vorr_i16(dc, Vd, imm) instr_create_1dst_1src((dc), OP_vorr_i16, (Vd), (imm)) |
| #define | INSTR_CREATE_vorr_i32(dc, Vd, imm) instr_create_1dst_1src((dc), OP_vorr_i32, (Vd), (imm)) |
Signature: (Vd, Vm_or_imm) | |
| #define | INSTR_CREATE_vmov_f32(dc, Vd, Vm_or_imm) instr_create_1dst_1src((dc), OP_vmov_f32, (Vd), (Vm_or_imm)) |
| #define | INSTR_CREATE_vmov_f64(dc, Vd, Vm_or_imm) instr_create_1dst_1src((dc), OP_vmov_f64, (Vd), (Vm_or_imm)) |
Signature: (Vt, Vm_or_imm) | |
| #define | INSTR_CREATE_vcmp_f32(dc, Vt, Vm_or_imm) |
| #define | INSTR_CREATE_vcmp_f64(dc, Vt, Vm_or_imm) |
| #define | INSTR_CREATE_vcmpe_f32(dc, Vt, Vm_or_imm) |
| #define | INSTR_CREATE_vcmpe_f64(dc, Vt, Vm_or_imm) |
Signature: (Rd, Vn, imm) | |
| #define | INSTR_CREATE_vmov_32_s2g(dc, Rd, Vn, imm) instr_create_1dst_2src((dc), OP_vmov_32, (Rd), (Vn), (imm)) |
| #define | INSTR_CREATE_vmov_s16(dc, Rd, Vn, imm) instr_create_1dst_2src((dc), OP_vmov_s16, (Rd), (Vn), (imm)) |
| #define | INSTR_CREATE_vmov_s8(dc, Rd, Vn, imm) instr_create_1dst_2src((dc), OP_vmov_s8, (Rd), (Vn), (imm)) |
| #define | INSTR_CREATE_vmov_u16(dc, Rd, Vn, imm) instr_create_1dst_2src((dc), OP_vmov_u16, (Rd), (Vn), (imm)) |
| #define | INSTR_CREATE_vmov_u8(dc, Rd, Vn, imm) instr_create_1dst_2src((dc), OP_vmov_u8, (Rd), (Vn), (imm)) |
Signature: (Vd, Vm, imm) | |
| #define | INSTR_CREATE_vcle_f32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcle_f32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcle_s16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcle_s16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcle_s32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcle_s32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcle_s8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcle_s8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vclt_f32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vclt_f32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vclt_s16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vclt_s16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vclt_s32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vclt_s32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vclt_s8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vclt_s8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_f32_s16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_f32_s16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_f32_s32_imm(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_f32_s32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_f32_u16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_f32_u16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_f32_u32_imm(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_f32_u32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_f64_s16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_f64_s16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_f64_s32_imm(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_f64_s32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_f64_u16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_f64_u16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_f64_u32_imm(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_f64_u32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_s16_f32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_s16_f32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_s16_f64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_s16_f64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_s32_f32_imm(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_s32_f32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_s32_f64_imm(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_s32_f64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_u16_f32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_u16_f32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_u16_f64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_u16_f64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_u32_f32_imm(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_u32_f32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vcvt_u32_f64_imm(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vcvt_u32_f64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vdup_16_imm(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vdup_16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vdup_32_imm(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vdup_32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vdup_8_imm(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vdup_8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqrshrn_s16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqrshrn_s16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqrshrn_s32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqrshrn_s32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqrshrn_s64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqrshrn_s64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqrshrn_u16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqrshrn_u16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqrshrn_u32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqrshrn_u32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqrshrn_u64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqrshrn_u64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqrshrun_s16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqrshrun_s16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqrshrun_s32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqrshrun_s32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqrshrun_s64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqrshrun_s64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqshlu_s16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqshlu_s16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqshlu_s32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqshlu_s32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqshlu_s64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqshlu_s64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqshlu_s8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqshlu_s8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqshrn_s16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqshrn_s16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqshrn_s32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqshrn_s32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqshrn_s64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqshrn_s64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqshrn_u16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqshrn_u16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqshrn_u32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqshrn_u32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqshrn_u64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqshrn_u64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqshrun_s16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqshrun_s16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqshrun_s32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqshrun_s32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vqshrun_s64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vqshrun_s64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrshr_s16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrshr_s16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrshr_s32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrshr_s32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrshr_s64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrshr_s64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrshr_s8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrshr_s8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrshr_u16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrshr_u16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrshr_u32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrshr_u32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrshr_u64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrshr_u64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrshr_u8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrshr_u8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrshrn_i16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrshrn_i16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrshrn_i32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrshrn_i32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrshrn_i64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrshrn_i64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrsra_s16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrsra_s16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrsra_s32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrsra_s32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrsra_s64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrsra_s64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrsra_s8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrsra_s8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrsra_u16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrsra_u16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrsra_u32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrsra_u32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrsra_u64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrsra_u64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vrsra_u8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vrsra_u8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshl_i16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshl_i16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshl_i32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshl_i32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshl_i64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshl_i64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshl_i8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshl_i8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshll_i16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshll_i16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshll_i32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshll_i32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshll_i8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshll_i8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshll_s16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshll_s16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshll_s32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshll_s32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshll_s8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshll_s8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshll_u16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshll_u16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshll_u32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshll_u32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshll_u8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshll_u8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshr_s16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshr_s16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshr_s32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshr_s32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshr_s64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshr_s64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshr_s8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshr_s8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshr_u16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshr_u16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshr_u32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshr_u32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshr_u64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshr_u64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshr_u8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshr_u8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshrn_i16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshrn_i16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshrn_i32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshrn_i32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vshrn_i64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vshrn_i64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsli_16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsli_16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsli_32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsli_32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsli_64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsli_64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsli_8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsli_8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsra_s16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsra_s16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsra_s32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsra_s32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsra_s64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsra_s64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsra_s8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsra_s8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsra_u16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsra_u16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsra_u32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsra_u32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsra_u64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsra_u64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsra_u8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsra_u8, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsri_16(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsri_16, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsri_32(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsri_32, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsri_64(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsri_64, (Vd), (Vm), (imm)) |
| #define | INSTR_CREATE_vsri_8(dc, Vd, Vm, imm) instr_create_1dst_2src((dc), OP_vsri_8, (Vd), (Vm), (imm)) |
Signature: (Vd, Rt, imm) | |
| #define | INSTR_CREATE_vmov_16(dc, Vd, Rt, imm) instr_create_1dst_2src((dc), OP_vmov_16, (Vd), (Rt), (imm)) |
| #define | INSTR_CREATE_vmov_32_g2s(dc, Vd, Rt, imm) instr_create_1dst_2src((dc), OP_vmov_32, (Vd), (Rt), (imm)) |
| #define | INSTR_CREATE_vmov_8(dc, Vd, Rt, imm) instr_create_1dst_2src((dc), OP_vmov_8, (Vd), (Rt), (imm)) |
Signature: (Vd, Vn, Vm_or_imm) | |
| #define | INSTR_CREATE_vceq_f32(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vceq_f32, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vceq_i16(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vceq_i16, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vceq_i32(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vceq_i32, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vceq_i8(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vceq_i8, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vcge_f32(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vcge_f32, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vcge_s16(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vcge_s16, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vcge_s32(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vcge_s32, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vcge_s8(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vcge_s8, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vcgt_f32(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vcgt_f32, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vcgt_s16(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vcgt_s16, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vcgt_s32(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vcgt_s32, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vcgt_s8(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vcgt_s8, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vqshl_s16(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vqshl_s16, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vqshl_s32(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vqshl_s32, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vqshl_s64(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vqshl_s64, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vqshl_s8(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vqshl_s8, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vqshl_u16(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vqshl_u16, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vqshl_u32(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vqshl_u32, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vqshl_u64(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vqshl_u64, (Vd), (Vn), (Vm_or_imm)) |
| #define | INSTR_CREATE_vqshl_u8(dc, Vd, Vn, Vm_or_imm) instr_create_1dst_2src((dc), OP_vqshl_u8, (Vd), (Vn), (Vm_or_imm)) |
Signature: (Vd, Vn, Vm, imm) | |
| #define | INSTR_CREATE_vext(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vext, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmla_f32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmla_f32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmla_i16_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmla_i16, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmla_i32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmla_i32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmlal_s16_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmlal_s16, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmlal_s32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmlal_s32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmlal_u16_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmlal_u16, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmlal_u32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmlal_u32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmls_f32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmls_f32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmls_i16_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmls_i16, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmls_i32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmls_i32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmlsl_s16_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmlsl_s16, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmlsl_s32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmlsl_s32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmlsl_u16_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmlsl_u16, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmlsl_u32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmlsl_u32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmul_f32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmul_f32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmul_i16_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmul_i16, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmul_i32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmul_i32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmull_s16_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmull_s16, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmull_s32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmull_s32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmull_u16_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmull_u16, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vmull_u32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vmull_u32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vqdmlal_s16_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vqdmlal_s16, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vqdmlal_s32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vqdmlal_s32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vqdmlsl_s16_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vqdmlsl_s16, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vqdmlsl_s32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vqdmlsl_s32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vqdmulh_s16_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vqdmulh_s16, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vqdmulh_s32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vqdmulh_s32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vqdmull_s16_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vqdmull_s16, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vqdmull_s32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vqdmull_s32, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vqrdmulh_s16_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vqrdmulh_s16, (Vd), (Vn), (Vm), (imm)) |
| #define | INSTR_CREATE_vqrdmulh_s32_imm(dc, Vd, Vn, Vm, imm) instr_create_1dst_3src((dc), OP_vqrdmulh_s32, (Vd), (Vn), (Vm), (imm)) |
Signature: (Vd, imm, Vn, Vm) | |
| #define | INSTR_CREATE_vsel_eq_f32(dc, Vd, imm, Vn, Vm) instr_create_1dst_3src((dc), OP_vsel_eq_f32, (Vd), (imm), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsel_eq_f64(dc, Vd, imm, Vn, Vm) instr_create_1dst_3src((dc), OP_vsel_eq_f64, (Vd), (imm), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsel_ge_f32(dc, Vd, imm, Vn, Vm) instr_create_1dst_3src((dc), OP_vsel_ge_f32, (Vd), (imm), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsel_ge_f64(dc, Vd, imm, Vn, Vm) instr_create_1dst_3src((dc), OP_vsel_ge_f64, (Vd), (imm), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsel_gt_f32(dc, Vd, imm, Vn, Vm) instr_create_1dst_3src((dc), OP_vsel_gt_f32, (Vd), (imm), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsel_gt_f64(dc, Vd, imm, Vn, Vm) instr_create_1dst_3src((dc), OP_vsel_gt_f64, (Vd), (imm), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsel_vs_f32(dc, Vd, imm, Vn, Vm) instr_create_1dst_3src((dc), OP_vsel_vs_f32, (Vd), (imm), (Vn), (Vm)) |
| #define | INSTR_CREATE_vsel_vs_f64(dc, Vd, imm, Vn, Vm) instr_create_1dst_3src((dc), OP_vsel_vs_f64, (Vd), (imm), (Vn), (Vm)) |
Signature: (Vd, mem) | |
| #define | INSTR_CREATE_vldr(dc, Vd, mem) instr_create_1dst_1src((dc), OP_vldr, (Vd), (mem)) |
Signature: (mem, Vt) | |
| #define | INSTR_CREATE_vstr(dc, mem, Vt) instr_create_1dst_1src((dc), OP_vstr, (mem), (Vt)) |
Signature: (Vd, mem, imm) | |
| #define | INSTR_CREATE_vld1_lane_8(dc, Vd, mem, imm) instr_create_1dst_2src((dc), OP_vld1_lane_8, (Vd), (mem), (imm)) |
| #define | INSTR_CREATE_vld1_lane_8_wbimm(dc, Vd, mem, imm) |
Signature: (mem, Vt, imm) | |
| #define | INSTR_CREATE_vst1_lane_8(dc, mem, Vt, imm) instr_create_1dst_2src((dc), OP_vst1_lane_8, (mem), (Vt), (imm)) |
| #define | INSTR_CREATE_vst1_lane_8_wbimm(dc, mem, Vt, imm) |
Signature: (Vd, mem, imm, Rm) | |
| #define | INSTR_CREATE_vld1_lane_8_wbreg(dc, Vd, mem, imm, Rm) |
Signature: (Vd, mem, imm, imm2) | |
| #define | INSTR_CREATE_vld1_lane_16(dc, Vd, mem, imm, imm2) instr_create_1dst_3src((dc), OP_vld1_lane_16, (Vd), (mem), (imm), (imm2)) |
| #define | INSTR_CREATE_vld1_lane_16_wbimm(dc, Vd, mem, imm, imm2) |
| #define | INSTR_CREATE_vld1_lane_32(dc, Vd, mem, imm, imm2) instr_create_1dst_3src((dc), OP_vld1_lane_32, (Vd), (mem), (imm), (imm2)) |
| #define | INSTR_CREATE_vld1_lane_32_wbimm(dc, Vd, mem, imm, imm2) |
Signature: (mem, Vt, imm, Rm) | |
| #define | INSTR_CREATE_vst1_lane_8_wbreg(dc, mem, Vt, imm, Rm) |
Signature: (mem, Vt, imm, imm2) | |
| #define | INSTR_CREATE_vst1_lane_16(dc, mem, Vt, imm, imm2) instr_create_1dst_3src((dc), OP_vst1_lane_16, (mem), (Vt), (imm), (imm2)) |
| #define | INSTR_CREATE_vst1_lane_16_wbimm(dc, mem, Vt, imm, imm2) |
| #define | INSTR_CREATE_vst1_lane_32(dc, mem, Vt, imm, imm2) instr_create_1dst_3src((dc), OP_vst1_lane_32, (mem), (Vt), (imm), (imm2)) |
| #define | INSTR_CREATE_vst1_lane_32_wbimm(dc, mem, Vt, imm, imm2) |
Signature: (Vd, mem, imm, imm2, Rm) | |
| #define | INSTR_CREATE_vld1_lane_16_wbreg(dc, Vd, mem, imm, imm2, Rm) |
| #define | INSTR_CREATE_vld1_lane_32_wbreg(dc, Vd, mem, imm, imm2, Rm) |
Signature: (mem, Vt, imm, imm2, Rm) | |
| #define | INSTR_CREATE_vst1_lane_16_wbreg(dc, mem, Vt, imm, imm2, Rm) |
| #define | INSTR_CREATE_vst1_lane_32_wbreg(dc, mem, Vt, imm, imm2, Rm) |
Signature: (Vd, Vm, list_len, ...) | |
| #define | INSTR_CREATE_vtbl_8(dc, Vd, Vm, list_len, ...) |
| #define | INSTR_CREATE_vtbx_8(dc, Vd, Vm, list_len, ...) |
ARM-specific instruction creation convenience macros.
| #define dr_ir_macros_arm_hlt | ( | dc, | |
| imm | |||
| ) | instr_create_0dst_1src((dc), OP_hlt, (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define dr_ir_macros_arm_hvc | ( | dc, | |
| imm | |||
| ) | instr_create_0dst_1src((dc), OP_hvc, (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_adc | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_adc_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_adc_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_adcs | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_adcs_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_adcs_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_add | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_add_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_add_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_adds | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_adds_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_adds_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_addw | ( | dc, | |
| Rd, | |||
| Rn, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_addw, (Rd), (Rn), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_aesd_8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_aesd_8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_aese_8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_aese_8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_aesimc_8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_aesimc_8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_aesmc_8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_aesmc_8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_and | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_and_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_and_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_ands | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ands_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ands_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_asr | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_asr, (Rd), (Rn), (Rm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_asrs | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_asrs, (Rd), (Rn), (Rm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_b | ( | dc, | |
| pc | |||
| ) | instr_create_0dst_1src((dc), OP_b, (pc)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_b_short | ( | dc, | |
| pc | |||
| ) | instr_create_0dst_1src((dc), OP_b_short, (pc)) |
| #define INSTR_CREATE_b_short | ( | dc, | |
| pc | |||
| ) | instr_create_0dst_1src((dc), OP_b_short, (pc)) |
| #define INSTR_CREATE_bfc | ( | dc, | |
| Rd, | |||
| imm, | |||
| imm2 | |||
| ) | instr_create_1dst_3src((dc), OP_bfc, (Rd), (imm), (imm2), (Rd)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_bfi | ( | dc, | |
| Rd, | |||
| Rm, | |||
| imm, | |||
| imm2 | |||
| ) | instr_create_1dst_4src((dc), OP_bfi, (Rd), (Rm), (imm), (imm2), (Rd)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_bic | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_bic_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_bic_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_bics | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_bics_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_bics_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_bkpt | ( | dc, | |
| imm | |||
| ) | instr_create_0dst_1src((dc), OP_bkpt, (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_bl | ( | dc, | |
| pc | |||
| ) | instr_create_1dst_1src((dc), OP_bl, opnd_create_reg(DR_REG_LR), (pc)) |
| #define INSTR_CREATE_blx | ( | dc, | |
| pc | |||
| ) | instr_create_1dst_1src((dc), OP_blx, opnd_create_reg(DR_REG_LR), (pc)) |
| #define INSTR_CREATE_blx_ind | ( | dc, | |
| Rm | |||
| ) | instr_create_1dst_1src((dc), OP_blx_ind, opnd_create_reg(DR_REG_LR), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_bx | ( | dc, | |
| Rm | |||
| ) | instr_create_0dst_1src((dc), OP_bx, (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_bxj | ( | dc, | |
| Rm | |||
| ) | instr_create_0dst_1src((dc), OP_bxj, (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_cbnz | ( | dc, | |
| pc, | |||
| Rn | |||
| ) | instr_create_0dst_2src((dc), OP_cbnz, (pc), (Rn)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_cbz | ( | dc, | |
| pc, | |||
| Rn | |||
| ) | instr_create_0dst_2src((dc), OP_cbz, (pc), (Rn)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_cdp | ( | dc, | |
| cpreg, | |||
| imm, | |||
| imm2, | |||
| cpreg2, | |||
| cpreg3, | |||
| imm3 | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| cpreg | The coprocessor register opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| cpreg2 | The second coprocessor register opnd_t operand. |
| cpreg3 | The third coprocessor register opnd_t operand. |
| imm3 | The third integer constant opnd_t operand. |
| #define INSTR_CREATE_cdp2 | ( | dc, | |
| cpreg, | |||
| imm, | |||
| imm2, | |||
| cpreg2, | |||
| cpreg3 | |||
| ) | instr_create_1dst_4src((dc), OP_cdp2, (cpreg), (imm), (imm2), (cpreg2), (cpreg3)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| cpreg | The coprocessor register opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| cpreg2 | The second coprocessor register opnd_t operand. |
| cpreg3 | The third coprocessor register opnd_t operand. |
| #define INSTR_CREATE_clrex | ( | dc | ) | instr_create_0dst_0src((dc), OP_clrex) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| #define INSTR_CREATE_clz | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src((dc), OP_clz, (Rd), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_cmn | ( | dc, | |
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_cmn_shimm | ( | dc, | |
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_cmn_shreg | ( | dc, | |
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_cmp | ( | dc, | |
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_cmp_shimm | ( | dc, | |
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_cmp_shreg | ( | dc, | |
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_cps | ( | dc, | |
| imm | |||
| ) | instr_create_0dst_1src((dc), OP_cps, (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_cpsid | ( | dc, | |
| imm | |||
| ) | instr_create_0dst_1src((dc), OP_cpsid, (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_cpsid_noflags | ( | dc, | |
| imm, | |||
| imm2 | |||
| ) | instr_create_0dst_2src((dc), OP_cpsid, (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_cpsie | ( | dc, | |
| imm | |||
| ) | instr_create_0dst_1src((dc), OP_cpsie, (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_cpsie_noflags | ( | dc, | |
| imm, | |||
| imm2 | |||
| ) | instr_create_0dst_2src((dc), OP_cpsie, (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_crc32b | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_crc32b, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_crc32cb | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_crc32cb, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_crc32ch | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_crc32ch, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_crc32cw | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_crc32cw, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_crc32h | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_crc32h, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_crc32w | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_crc32w, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_dbg | ( | dc, | |
| imm | |||
| ) | instr_create_0dst_1src((dc), OP_dbg, (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_dcps1 | ( | dc | ) | instr_create_0dst_0src((dc), OP_dcps1) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| #define INSTR_CREATE_dcps2 | ( | dc | ) | instr_create_0dst_0src((dc), OP_dcps2) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| #define INSTR_CREATE_dcps3 | ( | dc | ) | instr_create_0dst_0src((dc), OP_dcps3) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| #define INSTR_CREATE_dmb | ( | dc, | |
| imm | |||
| ) | instr_create_0dst_1src((dc), OP_dmb, (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_dsb | ( | dc, | |
| imm | |||
| ) | instr_create_0dst_1src((dc), OP_dsb, (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_enterx | ( | dc | ) | instr_create_0dst_0src((dc), OP_enterx) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| #define INSTR_CREATE_eor | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_eor_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_eor_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_eors | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_eors_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_eors_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_eret | ( | dc | ) | instr_create_0dst_1src((dc), OP_eret, opnd_create_reg(DR_REG_LR)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| #define INSTR_CREATE_eret_imm | ( | dc, | |
| imm | |||
| ) | instr_create_0dst_2src((dc), OP_eret, opnd_create_reg(DR_REG_LR), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_isb | ( | dc, | |
| imm | |||
| ) | instr_create_0dst_1src((dc), OP_isb, (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_it | ( | dc, | |
| imm, | |||
| imm2 | |||
| ) | instr_create_0dst_2src((dc), OP_it, (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_lda | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_lda, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldab | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldab, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldaex | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldaex, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldaexb | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldaexb, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldaexd | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| mem | |||
| ) | instr_create_2dst_1src((dc), OP_ldaexd, (Rd), (Rd2), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldaexh | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldaexh, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldah | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldah, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldc | ( | dc, | |
| cpreg, | |||
| mem, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_ldc, (cpreg), (mem), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldc2_option | ( | dc, | |
| cpreg, | |||
| mem, | |||
| imm, | |||
| imm2 | |||
| ) | instr_create_1dst_3src((dc), OP_ldc2, (cpreg), (mem), (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldc2_wbimm | ( | dc, | |
| cpreg, | |||
| mem, | |||
| imm, | |||
| imm2 | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldc2l_option | ( | dc, | |
| cpreg, | |||
| mem, | |||
| imm, | |||
| imm2 | |||
| ) | instr_create_1dst_3src((dc), OP_ldc2l, (cpreg), (mem), (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldc2l_wbimm | ( | dc, | |
| cpreg, | |||
| mem, | |||
| imm, | |||
| imm2 | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldc_option | ( | dc, | |
| cpreg, | |||
| mem, | |||
| imm, | |||
| imm2 | |||
| ) | instr_create_1dst_3src((dc), OP_ldc, (cpreg), (mem), (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldc_wbimm | ( | dc, | |
| cpreg, | |||
| mem, | |||
| imm, | |||
| imm2 | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldcl | ( | dc, | |
| cpreg, | |||
| mem, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_ldcl, (cpreg), (mem), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldcl_option | ( | dc, | |
| cpreg, | |||
| mem, | |||
| imm, | |||
| imm2 | |||
| ) | instr_create_1dst_3src((dc), OP_ldcl, (cpreg), (mem), (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldcl_wbimm | ( | dc, | |
| cpreg, | |||
| mem, | |||
| imm, | |||
| imm2 | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldm | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) | instr_create_Ndst_Msrc_vardst((dc), OP_ldm, 0, 1, list_len, 0, (mem), __VA_ARGS__) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldm_priv | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldm_priv_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldm_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldmda | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) | instr_create_Ndst_Msrc_vardst((dc), OP_ldmda, 0, 1, list_len, 0, (mem), __VA_ARGS__) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldmda_priv | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldmda_priv_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldmda_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldmdb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) | instr_create_Ndst_Msrc_vardst((dc), OP_ldmdb, 0, 1, list_len, 0, (mem), __VA_ARGS__) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldmdb_priv | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldmdb_priv_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldmdb_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldmib | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) | instr_create_Ndst_Msrc_vardst((dc), OP_ldmib, 0, 1, list_len, 0, (mem), __VA_ARGS__) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldmib_priv | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldmib_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldr | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldr, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldr_wbimm | ( | dc, | |
| Rd, | |||
| mem, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldr_wbreg | ( | dc, | |
| Rd, | |||
| mem, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrb | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldrb, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrb_wbimm | ( | dc, | |
| Rd, | |||
| mem, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrb_wbreg | ( | dc, | |
| Rd, | |||
| mem, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrbt | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldrbt, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrbt_wbimm | ( | dc, | |
| Rd, | |||
| mem, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrbt_wbreg | ( | dc, | |
| Rd, | |||
| mem, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrd | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| mem | |||
| ) | instr_create_2dst_1src((dc), OP_ldrd, (Rd), (Rd2), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrd_wbimm | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| mem, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrd_wbreg | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| mem, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrex | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldrex, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrexb | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldrexb, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrexd | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| mem | |||
| ) | instr_create_2dst_1src((dc), OP_ldrexd, (Rd), (Rd2), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrexh | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldrexh, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrh | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldrh, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrh_wbimm | ( | dc, | |
| Rd, | |||
| mem, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrh_wbreg | ( | dc, | |
| Rd, | |||
| mem, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrht | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldrht, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrht_wbimm | ( | dc, | |
| Rd, | |||
| mem, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrht_wbreg | ( | dc, | |
| Rd, | |||
| mem, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrsb | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldrsb, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrsb_wbimm | ( | dc, | |
| Rd, | |||
| mem, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrsb_wbreg | ( | dc, | |
| Rd, | |||
| mem, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrsbt | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldrsbt, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrsbt_wbimm | ( | dc, | |
| Rd, | |||
| mem, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrsbt_wbreg | ( | dc, | |
| Rd, | |||
| mem, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrsh | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldrsh, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrsh_wbimm | ( | dc, | |
| Rd, | |||
| mem, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrsh_wbreg | ( | dc, | |
| Rd, | |||
| mem, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrsht | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldrsht, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrsht_wbimm | ( | dc, | |
| Rd, | |||
| mem, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrsht_wbreg | ( | dc, | |
| Rd, | |||
| mem, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrt | ( | dc, | |
| Rd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldrt, (Rd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrt_wbimm | ( | dc, | |
| Rd, | |||
| mem, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ldrt_wbreg | ( | dc, | |
| Rd, | |||
| mem, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_leavex | ( | dc | ) | instr_create_0dst_0src((dc), OP_leavex) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| #define INSTR_CREATE_lsl | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_lsl, (Rd), (Rn), (Rm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_lsls | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_lsls, (Rd), (Rn), (Rm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_lsr | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_lsr, (Rd), (Rn), (Rm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_lsrs | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_lsrs, (Rd), (Rn), (Rm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mcr | ( | dc, | |
| cpreg, | |||
| cpreg2, | |||
| imm, | |||
| imm2, | |||
| Rt, | |||
| imm3 | |||
| ) | instr_create_2dst_4src((dc), OP_mcr, (cpreg), (cpreg2), (imm), (imm2), (Rt), (imm3)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| cpreg | The coprocessor register opnd_t operand. |
| cpreg2 | The second coprocessor register opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| Rt | The source register opnd_t operand. |
| imm3 | The third integer constant opnd_t operand. |
| #define INSTR_CREATE_mcr2 | ( | dc, | |
| cpreg, | |||
| cpreg2, | |||
| imm, | |||
| imm2, | |||
| Rt | |||
| ) | instr_create_2dst_3src((dc), OP_mcr2, (cpreg), (cpreg2), (imm), (imm2), (Rt)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mcrr | ( | dc, | |
| cpreg, | |||
| Rn, | |||
| Rt, | |||
| imm, | |||
| imm2 | |||
| ) | instr_create_1dst_4src((dc), OP_mcrr, (cpreg), (Rn), (Rt), (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mcrr2 | ( | dc, | |
| cpreg, | |||
| Rn, | |||
| Rt, | |||
| imm, | |||
| imm2 | |||
| ) | instr_create_1dst_4src((dc), OP_mcrr2, (cpreg), (Rn), (Rt), (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mla | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_mla, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mlas | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_mlas, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mls | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_mls, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mov | ( | dc, | |
| Rd, | |||
| Rm_or_imm | |||
| ) | instr_create_1dst_1src((dc), OP_mov, (Rd), (Rm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_movs | ( | dc, | |
| Rd, | |||
| Rm_or_imm | |||
| ) | instr_create_1dst_1src((dc), OP_movs, (Rd), (Rm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_movt | ( | dc, | |
| Rd, | |||
| imm | |||
| ) | instr_create_1dst_1src((dc), OP_movt, (Rd), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_movw | ( | dc, | |
| Rd, | |||
| imm | |||
| ) | instr_create_1dst_1src((dc), OP_movw, (Rd), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mrc | ( | dc, | |
| Rd, | |||
| imm, | |||
| imm2, | |||
| cpreg, | |||
| cpreg2, | |||
| imm3 | |||
| ) | instr_create_1dst_5src((dc), OP_mrc, (Rd), (imm), (imm2), (cpreg), (cpreg2), (imm3)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| cpreg | The coprocessor register opnd_t operand. |
| cpreg2 | The second coprocessor register opnd_t operand. |
| imm3 | The third integer constant opnd_t operand. |
| #define INSTR_CREATE_mrc2 | ( | dc, | |
| Rd, | |||
| imm, | |||
| imm2, | |||
| cpreg, | |||
| cpreg2, | |||
| imm3 | |||
| ) | instr_create_1dst_5src((dc), OP_mrc2, (Rd), (imm), (imm2), (cpreg), (cpreg2), (imm3)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| cpreg | The coprocessor register opnd_t operand. |
| cpreg2 | The second coprocessor register opnd_t operand. |
| imm3 | The third integer constant opnd_t operand. |
| #define INSTR_CREATE_mrrc | ( | dc, | |
| Ra, | |||
| Rd, | |||
| imm, | |||
| imm2, | |||
| cpreg | |||
| ) | instr_create_2dst_3src((dc), OP_mrrc, (Ra), (Rd), (imm), (imm2), (cpreg)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mrrc2 | ( | dc, | |
| Ra, | |||
| Rd, | |||
| imm, | |||
| imm2, | |||
| cpreg | |||
| ) | instr_create_2dst_3src((dc), OP_mrrc2, (Ra), (Rd), (imm), (imm2), (cpreg)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mrs | ( | dc, | |
| Rd, | |||
| statreg | |||
| ) | instr_create_1dst_1src((dc), OP_mrs, (Rd), (statreg)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mrs_priv | ( | dc, | |
| Rd, | |||
| imm | |||
| ) | instr_create_1dst_1src((dc), OP_mrs_priv, (Rd), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mrs_priv_spsr | ( | dc, | |
| Rd, | |||
| statreg, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_mrs_priv, (Rd), (statreg), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_msr | ( | dc, | |
| statreg, | |||
| imm_msr, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_msr, (statreg), (imm_msr), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_msr_imm | ( | dc, | |
| statreg, | |||
| imm, | |||
| imm2 | |||
| ) | instr_create_1dst_2src((dc), OP_msr, (statreg), (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_msr_priv | ( | dc, | |
| imm, | |||
| Rm | |||
| ) | instr_create_0dst_2src((dc), OP_msr_priv, (imm), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_msr_priv_spsr | ( | dc, | |
| statreg, | |||
| imm, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_msr_priv, (statreg), (imm), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mul | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_mul, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_muls | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_muls, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mvn | ( | dc, | |
| Rd, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mvn_shimm | ( | dc, | |
| Rd, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mvn_shreg | ( | dc, | |
| Rd, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mvns | ( | dc, | |
| Rd, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mvns_shimm | ( | dc, | |
| Rd, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_mvns_shreg | ( | dc, | |
| Rd, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_neg | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | INSTR_CREATE_rsb((dc), (Rd), (Rn), OPND_CREATE_INT16(0)) |
| #define INSTR_CREATE_nop | ( | dc | ) | instr_create_0dst_0src((dc), OP_nop) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| #define INSTR_CREATE_orn | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_orn_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_orns | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_orns_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_orr | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_orr_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_orr_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_orrs | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_orrs_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_orrs_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_pkhbt_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_pkhtb_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_pld | ( | dc, | |
| mem | |||
| ) | instr_create_0dst_1src((dc), OP_pld, (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_pldw | ( | dc, | |
| mem | |||
| ) | instr_create_0dst_1src((dc), OP_pldw, (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_pli | ( | dc, | |
| mem | |||
| ) | instr_create_0dst_1src((dc), OP_pli, (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_pop | ( | dc, | |
| Rd | |||
| ) |
This macro creates an instr_t for a pop instruction into a single register, automatically supplying any implicit operands.
| #define INSTR_CREATE_pop_list | ( | dc, | |
| list_len, | |||
| ... | |||
| ) | INSTR_CREATE_ldm_wb((dc), OPND_CREATE_MEMLIST(DR_REG_XSP), list_len, __VA_ARGS__) |
This macro creates an instr_t for a pop instruction into a list of registers, automatically supplying any implicit operands.
| #define INSTR_CREATE_push | ( | dc, | |
| Rt | |||
| ) |
This macro creates an instr_t for a push instruction of a single register, automatically supplying any implicit operands.
| #define INSTR_CREATE_push_list | ( | dc, | |
| list_len, | |||
| ... | |||
| ) | INSTR_CREATE_stmdb_wb((dc), OPND_CREATE_MEMLIST(DR_REG_XSP), list_len, __VA_ARGS__) |
This macro creates an instr_t for a push instruction of a list of registers, automatically supplying any implicit operands.
| #define INSTR_CREATE_qadd | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_qadd, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_qadd16 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_qadd16, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_qadd8 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_qadd8, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_qasx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_qasx, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_qdadd | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_qdadd, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_qdsub | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_qdsub, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_qsax | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_qsax, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_qsub | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src((dc), OP_qsub, (Rd), (Rm), (Rn)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_qsub16 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_qsub16, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_qsub8 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_qsub8, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rbit | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src((dc), OP_rbit, (Rd), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rev | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src((dc), OP_rev, (Rd), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rev16 | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src((dc), OP_rev16, (Rd), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_revsh | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src((dc), OP_revsh, (Rd), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rfe | ( | dc, | |
| statreg, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_rfe, (statreg), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rfe_wb | ( | dc, | |
| statreg, | |||
| mem | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rfeda | ( | dc, | |
| statreg, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_rfeda, (statreg), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rfeda_wb | ( | dc, | |
| statreg, | |||
| mem | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rfedb | ( | dc, | |
| statreg, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_rfedb, (statreg), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rfedb_wb | ( | dc, | |
| statreg, | |||
| mem | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rfeib | ( | dc, | |
| statreg, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_rfeib, (statreg), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rfeib_wb | ( | dc, | |
| statreg, | |||
| mem | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ror | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_ror, (Rd), (Rn), (Rm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rors | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_rors, (Rd), (Rn), (Rm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rrx | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src((dc), OP_rrx, (Rd), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rrxs | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src((dc), OP_rrxs, (Rd), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rsb | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rsb_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rsb_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_rsbs | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rsbs_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rsbs_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_rsc | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rsc_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rsc_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_rscs | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rscs_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_rscs_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_sadd16 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_sadd16, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sadd8 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_sadd8, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sasx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_sasx, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sbc | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sbc_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sbc_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_sbcs | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sbcs_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sbcs_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_sbfx | ( | dc, | |
| Rd, | |||
| Rm, | |||
| imm, | |||
| imm2 | |||
| ) | instr_create_1dst_3src((dc), OP_sbfx, (Rd), (Rm), (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sdiv | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_sdiv, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sel | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_sel, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_setend | ( | dc, | |
| imm | |||
| ) | instr_create_0dst_1src((dc), OP_setend, (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sev | ( | dc | ) | instr_create_0dst_0src((dc), OP_sev) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| #define INSTR_CREATE_sevl | ( | dc | ) | instr_create_0dst_0src((dc), OP_sevl) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| #define INSTR_CREATE_sha1c_32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_sha1c_32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sha1h_32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_sha1h_32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sha1m_32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_sha1m_32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sha1p_32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_sha1p_32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sha1su0_32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_sha1su0_32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sha1su1_32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_sha1su1_32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sha256h2_32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_sha256h2_32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sha256h_32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_sha256h_32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sha256su0_32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_sha256su0_32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sha256su1_32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_sha256su1_32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_shadd16 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_shadd16, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_shadd8 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_shadd8, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_shasx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_shasx, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_shsax | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_shsax, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_shsub16 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_shsub16, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_shsub8 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_shsub8, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smc | ( | dc, | |
| imm | |||
| ) | instr_create_0dst_1src((dc), OP_smc, (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlabb | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_smlabb, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlabt | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_smlabt, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlad | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_smlad, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smladx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_smladx, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlal | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_4src((dc), OP_smlal, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlalbb | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_4src((dc), OP_smlalbb, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlalbt | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_4src((dc), OP_smlalbt, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlald | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_4src((dc), OP_smlald, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlaldx | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_4src((dc), OP_smlaldx, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlals | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_4src((dc), OP_smlals, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlaltb | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_4src((dc), OP_smlaltb, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlaltt | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_4src((dc), OP_smlaltt, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlatb | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_smlatb, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlatt | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_smlatt, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlawb | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_smlawb, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlawt | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_smlawt, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlsd | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_smlsd, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlsdx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_smlsdx, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlsld | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_4src((dc), OP_smlsld, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smlsldx | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_4src((dc), OP_smlsldx, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smmla | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_smmla, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smmlar | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_smmlar, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smmls | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_smmls, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smmlsr | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_smmlsr, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smmul | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_smmul, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smmulr | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_smmulr, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smuad | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_smuad, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smuadx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_smuadx, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smulbb | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_smulbb, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smulbt | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_smulbt, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smull | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_2src((dc), OP_smull, (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smulls | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_2src((dc), OP_smulls, (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smultb | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_smultb, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smultt | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_smultt, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smulwb | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_smulwb, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smulwt | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_smulwt, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smusd | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_smusd, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_smusdx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_smusdx, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_srs | ( | dc, | |
| mem, | |||
| imm, | |||
| statreg | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_srs_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| statreg | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_srsda | ( | dc, | |
| mem, | |||
| imm, | |||
| statreg | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_srsda_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| statreg | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_srsdb | ( | dc, | |
| mem, | |||
| imm, | |||
| statreg | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_srsdb_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| statreg | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_srsib | ( | dc, | |
| mem, | |||
| imm, | |||
| statreg | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_srsib_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| statreg | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ssat16 | ( | dc, | |
| Rd, | |||
| imm, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_ssat16, (Rd), (imm), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ssat_shimm | ( | dc, | |
| Rd, | |||
| imm, | |||
| Rm, | |||
| shift, | |||
| imm2 | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| #define INSTR_CREATE_ssax | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_ssax, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ssub16 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_ssub16, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ssub8 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_ssub8, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stc | ( | dc, | |
| mem, | |||
| imm, | |||
| cpreg, | |||
| imm2 | |||
| ) | instr_create_1dst_3src((dc), OP_stc, (mem), (imm), (cpreg), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stc2 | ( | dc, | |
| mem, | |||
| imm, | |||
| cpreg, | |||
| imm2 | |||
| ) | instr_create_1dst_3src((dc), OP_stc2, (mem), (imm), (cpreg), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stc2_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| cpreg, | |||
| imm2 | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stc2l | ( | dc, | |
| mem, | |||
| imm, | |||
| cpreg, | |||
| imm2 | |||
| ) | instr_create_1dst_3src((dc), OP_stc2l, (mem), (imm), (cpreg), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stc2l_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| cpreg, | |||
| imm2 | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stc_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| cpreg, | |||
| imm2 | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stcl | ( | dc, | |
| mem, | |||
| imm, | |||
| cpreg, | |||
| imm2 | |||
| ) | instr_create_1dst_3src((dc), OP_stcl, (mem), (imm), (cpreg), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stcl_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| cpreg, | |||
| imm2 | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stl | ( | dc, | |
| mem, | |||
| Rm | |||
| ) | instr_create_1dst_1src((dc), OP_stl, (mem), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stlb | ( | dc, | |
| mem, | |||
| Rm | |||
| ) | instr_create_1dst_1src((dc), OP_stlb, (mem), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stlex | ( | dc, | |
| mem, | |||
| Rd, | |||
| Rm | |||
| ) | instr_create_2dst_1src((dc), OP_stlex, (mem), (Rd), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stlexb | ( | dc, | |
| mem, | |||
| Rd, | |||
| Rm | |||
| ) | instr_create_2dst_1src((dc), OP_stlexb, (mem), (Rd), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stlexd | ( | dc, | |
| mem, | |||
| Rd, | |||
| Rt, | |||
| Rt2 | |||
| ) | instr_create_2dst_2src((dc), OP_stlexd, (mem), (Rd), (Rt), (Rt2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stlexh | ( | dc, | |
| mem, | |||
| Rd, | |||
| Rm | |||
| ) | instr_create_2dst_1src((dc), OP_stlexh, (mem), (Rd), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stlh | ( | dc, | |
| mem, | |||
| Rm | |||
| ) | instr_create_1dst_1src((dc), OP_stlh, (mem), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stm | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) | instr_create_Ndst_Msrc_varsrc((dc), OP_stm, 1, 0, list_len, 0, (mem), __VA_ARGS__) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stm_priv | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stm_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stmda | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) | instr_create_Ndst_Msrc_varsrc((dc), OP_stmda, 1, 0, list_len, 0, (mem), __VA_ARGS__) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stmda_priv | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stmda_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stmdb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) | instr_create_Ndst_Msrc_varsrc((dc), OP_stmdb, 1, 0, list_len, 0, (mem), __VA_ARGS__) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stmdb_priv | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stmdb_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stmib | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) | instr_create_Ndst_Msrc_varsrc((dc), OP_stmib, 1, 0, list_len, 0, (mem), __VA_ARGS__) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stmib_priv | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_stmib_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_str | ( | dc, | |
| mem, | |||
| Rt | |||
| ) | instr_create_1dst_1src((dc), OP_str, (mem), (Rt)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_str_wbimm | ( | dc, | |
| mem, | |||
| Rt, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_str_wbreg | ( | dc, | |
| mem, | |||
| Rt, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strb | ( | dc, | |
| mem, | |||
| Rt | |||
| ) | instr_create_1dst_1src((dc), OP_strb, (mem), (Rt)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strb_wbimm | ( | dc, | |
| mem, | |||
| Rt, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strb_wbreg | ( | dc, | |
| mem, | |||
| Rt, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strbt | ( | dc, | |
| mem, | |||
| Rt | |||
| ) | instr_create_1dst_1src((dc), OP_strbt, (mem), (Rt)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strbt_wbimm | ( | dc, | |
| mem, | |||
| Rt, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strbt_wbreg | ( | dc, | |
| mem, | |||
| Rt, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strd | ( | dc, | |
| mem, | |||
| Rt, | |||
| Rt2 | |||
| ) | instr_create_1dst_2src((dc), OP_strd, (mem), (Rt), (Rt2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strd_wbimm | ( | dc, | |
| mem, | |||
| Rt, | |||
| Rt2, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strd_wbreg | ( | dc, | |
| mem, | |||
| Rt, | |||
| Rt2, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strex | ( | dc, | |
| mem, | |||
| Rd, | |||
| Rm | |||
| ) | instr_create_2dst_1src((dc), OP_strex, (mem), (Rd), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strexb | ( | dc, | |
| mem, | |||
| Rd, | |||
| Rm | |||
| ) | instr_create_2dst_1src((dc), OP_strexb, (mem), (Rd), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strexd | ( | dc, | |
| mem, | |||
| Rd, | |||
| Rt, | |||
| Rt2 | |||
| ) | instr_create_2dst_2src((dc), OP_strexd, (mem), (Rd), (Rt), (Rt2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strexh | ( | dc, | |
| mem, | |||
| Rd, | |||
| Rm | |||
| ) | instr_create_2dst_1src((dc), OP_strexh, (mem), (Rd), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strh | ( | dc, | |
| mem, | |||
| Rt | |||
| ) | instr_create_1dst_1src((dc), OP_strh, (mem), (Rt)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strh_wbimm | ( | dc, | |
| mem, | |||
| Rt, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strh_wbreg | ( | dc, | |
| mem, | |||
| Rt, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strht | ( | dc, | |
| mem, | |||
| Rt | |||
| ) | instr_create_1dst_1src((dc), OP_strht, (mem), (Rt)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strht_wbimm | ( | dc, | |
| mem, | |||
| Rt, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strht_wbreg | ( | dc, | |
| mem, | |||
| Rt, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strt | ( | dc, | |
| mem, | |||
| Rt | |||
| ) | instr_create_1dst_1src((dc), OP_strt, (mem), (Rt)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strt_wbimm | ( | dc, | |
| mem, | |||
| Rt, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_strt_wbreg | ( | dc, | |
| mem, | |||
| Rt, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sub | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sub_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sub_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_subs | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_subs_shimm | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_subs_shreg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| Rn | The source register opnd_t operand. |
| Rm | The second source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| Rs | The third source register opnd_t operand. |
| #define INSTR_CREATE_subw | ( | dc, | |
| Rd, | |||
| Rn, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_subw, (Rd), (Rn), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_svc | ( | dc, | |
| imm | |||
| ) | instr_create_0dst_1src((dc), OP_svc, (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_swp | ( | dc, | |
| Rd, | |||
| mem, | |||
| Rm | |||
| ) | instr_create_2dst_2src((dc), OP_swp, (mem), (Rd), (mem), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_swpb | ( | dc, | |
| Rd, | |||
| mem, | |||
| Rm | |||
| ) | instr_create_2dst_2src((dc), OP_swpb, (mem), (Rd), (mem), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sxtab | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_sxtab, (Rd), (Rn), (Rm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sxtab16 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_sxtab16, (Rd), (Rn), (Rm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sxtah | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_sxtah, (Rd), (Rn), (Rm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sxtb | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src((dc), OP_sxtb, (Rd), (Rn)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sxtb16 | ( | dc, | |
| Rd, | |||
| Rm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_sxtb16, (Rd), (Rm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sxtb_imm | ( | dc, | |
| Rd, | |||
| Rm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_sxtb, (Rd), (Rm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sxth | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src((dc), OP_sxth, (Rd), (Rn)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_sxth_imm | ( | dc, | |
| Rd, | |||
| Rm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_sxth, (Rd), (Rm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_tbb | ( | dc, | |
| mem | |||
| ) | instr_create_0dst_1src((dc), OP_tbb, (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_tbh | ( | dc, | |
| mem | |||
| ) | instr_create_0dst_1src((dc), OP_tbh, (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_teq | ( | dc, | |
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_teq_shimm | ( | dc, | |
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_teq_shreg | ( | dc, | |
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_tst | ( | dc, | |
| Rn, | |||
| Rm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_tst_shimm | ( | dc, | |
| Rn, | |||
| Rm, | |||
| shift, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_tst_shreg | ( | dc, | |
| Rn, | |||
| Rm, | |||
| shift, | |||
| Rs | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uadd16 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_uadd16, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uadd8 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_uadd8, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uasx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_uasx, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_ubfx | ( | dc, | |
| Rd, | |||
| Rm, | |||
| imm, | |||
| imm2 | |||
| ) | instr_create_1dst_3src((dc), OP_ubfx, (Rd), (Rm), (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_udf | ( | dc, | |
| imm | |||
| ) | instr_create_0dst_1src((dc), OP_udf, (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_udiv | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_udiv, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uhadd16 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_uhadd16, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uhadd8 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_uhadd8, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uhasx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_uhasx, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uhsax | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_uhsax, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uhsub16 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_uhsub16, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uhsub8 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_uhsub8, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_umaal | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_4src((dc), OP_umaal, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_umlal | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_4src((dc), OP_umlal, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_umlals | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_4src((dc), OP_umlals, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_umull | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_2src((dc), OP_umull, (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_umulls | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_2dst_2src((dc), OP_umulls, (Rd), (Rd2), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uqadd16 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_uqadd16, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uqadd8 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_uqadd8, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uqasx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_uqasx, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uqsax | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_uqsax, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uqsub16 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_uqsub16, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uqsub8 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_uqsub8, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_usad8 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_usad8, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_usada8 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_3src((dc), OP_usada8, (Rd), (Rn), (Rm), (Ra)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_usat16 | ( | dc, | |
| Rd, | |||
| imm, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_usat16, (Rd), (imm), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_usat_shimm | ( | dc, | |
| Rd, | |||
| imm, | |||
| Rm, | |||
| shift, | |||
| imm2 | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Rd | The destination register opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| shift | The dr_shift_type_t integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| #define INSTR_CREATE_usax | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_usax, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_usub16 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_usub16, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_usub8 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src((dc), OP_usub8, (Rd), (Rn), (Rm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uxtab | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_uxtab, (Rd), (Rn), (Rm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uxtab16 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_uxtab16, (Rd), (Rn), (Rm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uxtah | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_uxtah, (Rd), (Rn), (Rm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uxtb | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src((dc), OP_uxtb, (Rd), (Rn)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uxtb16 | ( | dc, | |
| Rd, | |||
| Rm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_uxtb16, (Rd), (Rm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uxtb_imm | ( | dc, | |
| Rd, | |||
| Rm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_uxtb, (Rd), (Rm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uxth | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src((dc), OP_uxth, (Rd), (Rn)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_uxth_imm | ( | dc, | |
| Rd, | |||
| Rm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_uxth, (Rd), (Rm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaba_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaba_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaba_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaba_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaba_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaba_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaba_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaba_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaba_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaba_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaba_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaba_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabal_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabal_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabal_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabal_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabal_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabal_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabal_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabal_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabal_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabal_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabal_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabal_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabd_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabd_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabd_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabd_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabd_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabd_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabd_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabd_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabd_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabd_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabd_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabd_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabdl_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabdl_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabdl_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabdl_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabdl_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabdl_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabdl_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabdl_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabdl_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabdl_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabdl_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vabdl_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabs_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vabs_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabs_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vabs_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabs_s16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vabs_s16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabs_s32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vabs_s32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vabs_s8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vabs_s8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vacge_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vacge_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vacgt_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vacgt_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vadd_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vadd_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vadd_f64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vadd_f64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vadd_i16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vadd_i16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vadd_i32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vadd_i32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vadd_i64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vadd_i64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vadd_i8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vadd_i8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaddhn_i16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaddhn_i16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaddhn_i32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaddhn_i32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaddhn_i64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaddhn_i64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaddl_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaddl_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaddl_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaddl_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaddl_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaddl_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaddl_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaddl_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaddl_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaddl_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaddl_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaddl_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaddw_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaddw_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaddw_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaddw_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaddw_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaddw_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaddw_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaddw_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaddw_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaddw_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vaddw_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vaddw_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vand | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vand, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vbic | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vbic, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vbic_i16 | ( | dc, | |
| Vd, | |||
| imm | |||
| ) | instr_create_1dst_1src((dc), OP_vbic_i16, (Vd), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vbic_i32 | ( | dc, | |
| Vd, | |||
| imm | |||
| ) | instr_create_1dst_1src((dc), OP_vbic_i32, (Vd), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vbif | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vbif, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vbit | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vbit, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vbsl | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vbsl, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vceq_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vceq_f32, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vceq_i16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vceq_i16, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vceq_i32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vceq_i32, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vceq_i8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vceq_i8, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcge_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcge_f32, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcge_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcge_s16, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcge_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcge_s32, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcge_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcge_s8, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcge_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vcge_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcge_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vcge_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcge_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vcge_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcgt_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcgt_f32, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcgt_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcgt_s16, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcgt_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcgt_s32, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcgt_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcgt_s8, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcgt_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vcgt_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcgt_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vcgt_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcgt_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vcgt_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcle_f32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcle_f32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcle_s16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcle_s16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcle_s32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcle_s32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcle_s8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcle_s8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcls_s16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcls_s16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcls_s32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcls_s32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcls_s8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcls_s8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vclt_f32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vclt_f32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vclt_s16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vclt_s16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vclt_s32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vclt_s32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vclt_s8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vclt_s8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vclz_i16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vclz_i16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vclz_i32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vclz_i32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vclz_i8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vclz_i8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcmp_f32 | ( | dc, | |
| Vt, | |||
| Vm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcmp_f64 | ( | dc, | |
| Vt, | |||
| Vm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcmpe_f32 | ( | dc, | |
| Vt, | |||
| Vm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcmpe_f64 | ( | dc, | |
| Vt, | |||
| Vm_or_imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcnt_8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcnt_8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f16_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvt_f16_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f32_f16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvt_f32_f16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f32_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvt_f32_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f32_s16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_f32_s16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f32_s32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvt_f32_s32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f32_s32_imm | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_f32_s32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f32_u16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_f32_u16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f32_u32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvt_f32_u32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f32_u32_imm | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_f32_u32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f64_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvt_f64_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f64_s16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_f64_s16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f64_s32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvt_f64_s32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f64_s32_imm | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_f64_s32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f64_u16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_f64_u16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f64_u32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvt_f64_u32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_f64_u32_imm | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_f64_u32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_s16_f32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_s16_f32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_s16_f64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_s16_f64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_s32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvt_s32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_s32_f32_imm | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_s32_f32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_s32_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvt_s32_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_s32_f64_imm | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_s32_f64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_u16_f32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_u16_f32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_u16_f64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_u16_f64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_u32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvt_u32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_u32_f32_imm | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_u32_f32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_u32_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvt_u32_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvt_u32_f64_imm | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vcvt_u32_f64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvta_s32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvta_s32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvta_s32_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvta_s32_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvta_u32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvta_u32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvta_u32_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvta_u32_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtb_f16_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtb_f16_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtb_f16_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtb_f16_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtb_f32_f16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtb_f32_f16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtb_f64_f16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtb_f64_f16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtm_s32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtm_s32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtm_s32_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtm_s32_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtm_u32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtm_u32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtm_u32_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtm_u32_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtn_s32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtn_s32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtn_s32_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtn_s32_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtn_u32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtn_u32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtn_u32_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtn_u32_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtp_s32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtp_s32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtp_s32_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtp_s32_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtp_u32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtp_u32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtp_u32_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtp_u32_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtr_s32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtr_s32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtr_s32_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtr_s32_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtr_u32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtr_u32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtr_u32_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtr_u32_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtt_f16_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtt_f16_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtt_f16_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtt_f16_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtt_f32_f16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtt_f32_f16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vcvtt_f64_f16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vcvtt_f64_f16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vdiv_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vdiv_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vdiv_f64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vdiv_f64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vdup_16 | ( | dc, | |
| Vd, | |||
| Rt | |||
| ) | instr_create_1dst_1src((dc), OP_vdup_16, (Vd), (Rt)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vdup_16_imm | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vdup_16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vdup_32 | ( | dc, | |
| Vd, | |||
| Rt | |||
| ) | instr_create_1dst_1src((dc), OP_vdup_32, (Vd), (Rt)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vdup_32_imm | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vdup_32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vdup_8 | ( | dc, | |
| Vd, | |||
| Rt | |||
| ) | instr_create_1dst_1src((dc), OP_vdup_8, (Vd), (Rt)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vdup_8_imm | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vdup_8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_veor | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_veor, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vext | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vext, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vfma_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vfma_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vfma_f64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vfma_f64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vfms_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vfms_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vfms_f64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vfms_f64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vfnma_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vfnma_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vfnma_f64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vfnma_f64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vfnms_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vfnms_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vfnms_f64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vfnms_f64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vhadd_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vhadd_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vhadd_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vhadd_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vhadd_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vhadd_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vhadd_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vhadd_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vhadd_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vhadd_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vhadd_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vhadd_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vhsub_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vhsub_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vhsub_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vhsub_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vhsub_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vhsub_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vhsub_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vhsub_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vhsub_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vhsub_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vhsub_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vhsub_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld1_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_64 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_64_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_64_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_8 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_8_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_8_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_dup_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_dup_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_dup_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_dup_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_dup_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_dup_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_dup_8 | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld1_dup_8_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld1_dup_8_wbreg | ( | dc, | |
| mem, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld1_lane_16 | ( | dc, | |
| Vd, | |||
| mem, | |||
| imm, | |||
| imm2 | |||
| ) | instr_create_1dst_3src((dc), OP_vld1_lane_16, (Vd), (mem), (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld1_lane_16_wbimm | ( | dc, | |
| Vd, | |||
| mem, | |||
| imm, | |||
| imm2 | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld1_lane_16_wbreg | ( | dc, | |
| Vd, | |||
| mem, | |||
| imm, | |||
| imm2, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld1_lane_32 | ( | dc, | |
| Vd, | |||
| mem, | |||
| imm, | |||
| imm2 | |||
| ) | instr_create_1dst_3src((dc), OP_vld1_lane_32, (Vd), (mem), (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld1_lane_32_wbimm | ( | dc, | |
| Vd, | |||
| mem, | |||
| imm, | |||
| imm2 | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld1_lane_32_wbreg | ( | dc, | |
| Vd, | |||
| mem, | |||
| imm, | |||
| imm2, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld1_lane_8 | ( | dc, | |
| Vd, | |||
| mem, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vld1_lane_8, (Vd), (mem), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld1_lane_8_wbimm | ( | dc, | |
| Vd, | |||
| mem, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld1_lane_8_wbreg | ( | dc, | |
| Vd, | |||
| mem, | |||
| imm, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld2_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_8 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_8_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_8_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_dup_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_dup_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_dup_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_dup_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_dup_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_dup_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_dup_8 | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld2_dup_8_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld2_dup_8_wbreg | ( | dc, | |
| mem, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_lane_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_lane_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_lane_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_lane_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_lane_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_lane_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_lane_8 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_lane_8_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld2_lane_8_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_8 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_8_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_8_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_dup_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_dup_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_dup_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_dup_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_dup_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_dup_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_dup_8 | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld3_dup_8_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld3_dup_8_wbreg | ( | dc, | |
| mem, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_lane_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_lane_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_lane_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_lane_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_lane_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_lane_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_lane_8 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_lane_8_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld3_lane_8_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_8 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_8_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_8_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_dup_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_dup_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_dup_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_dup_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_dup_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_dup_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_dup_8 | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld4_dup_8_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vld4_dup_8_wbreg | ( | dc, | |
| mem, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_lane_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_lane_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_lane_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_lane_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_lane_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_lane_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_lane_8 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_lane_8_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vld4_lane_8_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vldm | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) | instr_create_Ndst_Msrc_vardst((dc), OP_vldm, 0, 1, list_len, 0, (mem), __VA_ARGS__) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vldm_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vldmdb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vldr | ( | dc, | |
| Vd, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_vldr, (Vd), (mem)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmax_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmax_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmax_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmax_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmax_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmax_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmax_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmax_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmax_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmax_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmax_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmax_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmax_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmax_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmaxnm_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmaxnm_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmaxnm_f64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmaxnm_f64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmin_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmin_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmin_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmin_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmin_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmin_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmin_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmin_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmin_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmin_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmin_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmin_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmin_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmin_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vminnm_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vminnm_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vminnm_f64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vminnm_f64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmla_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmla_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmla_f32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmla_f32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmla_f64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmla_f64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmla_i16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmla_i16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmla_i16_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmla_i16, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmla_i32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmla_i32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmla_i32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmla_i32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmla_i8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmla_i8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlal_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmlal_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlal_s16_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmlal_s16, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlal_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmlal_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlal_s32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmlal_s32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlal_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmlal_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlal_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmlal_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlal_u16_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmlal_u16, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlal_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmlal_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlal_u32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmlal_u32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlal_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmlal_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmls_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmls_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmls_f32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmls_f32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmls_f64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmls_f64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmls_i16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmls_i16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmls_i16_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmls_i16, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmls_i32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmls_i32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmls_i32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmls_i32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmls_i8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmls_i8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlsl_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmlsl_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlsl_s16_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmlsl_s16, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlsl_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmlsl_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlsl_s32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmlsl_s32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlsl_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmlsl_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlsl_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmlsl_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlsl_u16_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmlsl_u16, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlsl_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmlsl_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlsl_u32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmlsl_u32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmlsl_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmlsl_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_16 | ( | dc, | |
| Vd, | |||
| Rt, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vmov_16, (Vd), (Rt), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_32_g2s | ( | dc, | |
| Vd, | |||
| Rt, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vmov_32, (Vd), (Rt), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_32_s2g | ( | dc, | |
| Rd, | |||
| Vn, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vmov_32, (Rd), (Vn), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_8 | ( | dc, | |
| Vd, | |||
| Rt, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vmov_8, (Vd), (Rt), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_f32 | ( | dc, | |
| Vd, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_1src((dc), OP_vmov_f32, (Vd), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_f64 | ( | dc, | |
| Vd, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_1src((dc), OP_vmov_f64, (Vd), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_g2s | ( | dc, | |
| Vd, | |||
| Rt | |||
| ) | instr_create_1dst_1src((dc), OP_vmov, (Vd), (Rt)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_gg2s | ( | dc, | |
| Vd, | |||
| Rt, | |||
| Rt2 | |||
| ) | instr_create_1dst_2src((dc), OP_vmov, (Vd), (Rt), (Rt2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_gg2ss | ( | dc, | |
| Vd, | |||
| Vd2, | |||
| Rt, | |||
| Rt2 | |||
| ) | instr_create_2dst_2src((dc), OP_vmov, (Vd), (Vd2), (Rt), (Rt2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_i16 | ( | dc, | |
| Vd, | |||
| imm | |||
| ) | instr_create_1dst_1src((dc), OP_vmov_i16, (Vd), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_i32 | ( | dc, | |
| Vd, | |||
| imm | |||
| ) | instr_create_1dst_1src((dc), OP_vmov_i32, (Vd), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_i64 | ( | dc, | |
| Vd, | |||
| imm | |||
| ) | instr_create_1dst_1src((dc), OP_vmov_i64, (Vd), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_i8 | ( | dc, | |
| Vd, | |||
| imm | |||
| ) | instr_create_1dst_1src((dc), OP_vmov_i8, (Vd), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_s16 | ( | dc, | |
| Rd, | |||
| Vn, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vmov_s16, (Rd), (Vn), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_s2g | ( | dc, | |
| Rd, | |||
| Vn | |||
| ) | instr_create_1dst_1src((dc), OP_vmov, (Rd), (Vn)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_s2gg | ( | dc, | |
| Ra, | |||
| Rd, | |||
| Vm | |||
| ) | instr_create_2dst_1src((dc), OP_vmov, (Ra), (Rd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_s8 | ( | dc, | |
| Rd, | |||
| Vn, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vmov_s8, (Rd), (Vn), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_ss2gg | ( | dc, | |
| Rd, | |||
| Rd2, | |||
| Vt, | |||
| Vt2 | |||
| ) | instr_create_2dst_2src((dc), OP_vmov, (Rd), (Rd2), (Vt), (Vt2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_u16 | ( | dc, | |
| Rd, | |||
| Vn, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vmov_u16, (Rd), (Vn), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmov_u8 | ( | dc, | |
| Rd, | |||
| Vn, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vmov_u8, (Rd), (Vn), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmovl_s16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vmovl_s16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmovl_s32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vmovl_s32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmovl_s8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vmovl_s8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmovl_u16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vmovl_u16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmovl_u32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vmovl_u32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmovl_u8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vmovl_u8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmovn_i16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vmovn_i16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmovn_i32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vmovn_i32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmovn_i64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vmovn_i64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmrs | ( | dc, | |
| Rd | |||
| ) | instr_create_1dst_1src((dc), OP_vmrs, (Rd), opnd_create_reg(DR_REG_FPSCR)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmrs_imm | ( | dc, | |
| Rd, | |||
| imm | |||
| ) | instr_create_1dst_1src((dc), OP_vmrs, (Rd), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmsr | ( | dc, | |
| Rt | |||
| ) | instr_create_1dst_1src((dc), OP_vmsr, opnd_create_reg(DR_REG_FPSCR), (Rt)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmsr_imm | ( | dc, | |
| Rt, | |||
| imm | |||
| ) | instr_create_0dst_2src((dc), OP_vmsr, (Rt), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmul_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmul_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmul_f32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmul_f32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmul_f64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmul_f64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmul_i16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmul_i16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmul_i16_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmul_i16, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmul_i32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmul_i32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmul_i32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmul_i32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmul_i8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmul_i8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmul_p32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmul_p32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmul_p8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmul_p8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmull_p32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmull_p32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmull_p8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmull_p8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmull_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmull_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmull_s16_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmull_s16, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmull_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmull_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmull_s32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmull_s32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmull_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmull_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmull_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmull_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmull_u16_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmull_u16, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmull_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmull_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmull_u32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vmull_u32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmull_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vmull_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmvn | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vmvn, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmvn_i16 | ( | dc, | |
| Vd, | |||
| imm | |||
| ) | instr_create_1dst_1src((dc), OP_vmvn_i16, (Vd), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vmvn_i32 | ( | dc, | |
| Vd, | |||
| imm | |||
| ) | instr_create_1dst_1src((dc), OP_vmvn_i32, (Vd), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vneg_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vneg_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vneg_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vneg_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vneg_s16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vneg_s16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vneg_s32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vneg_s32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vneg_s8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vneg_s8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vnmla_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vnmla_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vnmla_f64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vnmla_f64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vnmls_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vnmls_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vnmls_f64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vnmls_f64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vnmul_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vnmul_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vnmul_f64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vnmul_f64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vorn | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vorn, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vorr | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vorr, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vorr_i16 | ( | dc, | |
| Vd, | |||
| imm | |||
| ) | instr_create_1dst_1src((dc), OP_vorr_i16, (Vd), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vorr_i32 | ( | dc, | |
| Vd, | |||
| imm | |||
| ) | instr_create_1dst_1src((dc), OP_vorr_i32, (Vd), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpadal_s16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vpadal_s16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpadal_s32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vpadal_s32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpadal_s8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vpadal_s8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpadal_u16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vpadal_u16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpadal_u32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vpadal_u32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpadal_u8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vpadal_u8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpadd_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpadd_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpadd_i16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpadd_i16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpadd_i32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpadd_i32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpadd_i8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpadd_i8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpaddl_s16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vpaddl_s16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpaddl_s32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vpaddl_s32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpaddl_s8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vpaddl_s8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpaddl_u16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vpaddl_u16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpaddl_u32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vpaddl_u32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpaddl_u8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vpaddl_u8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpmax_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpmax_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpmax_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpmax_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpmax_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpmax_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpmax_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpmax_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpmax_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpmax_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpmax_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpmax_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpmax_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpmax_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpmin_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpmin_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpmin_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpmin_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpmin_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpmin_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpmin_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpmin_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpmin_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpmin_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpmin_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpmin_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vpmin_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vpmin_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqabs_s16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vqabs_s16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqabs_s32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vqabs_s32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqabs_s8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vqabs_s8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqadd_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqadd_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqadd_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqadd_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqadd_s64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqadd_s64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqadd_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqadd_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqadd_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqadd_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqadd_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqadd_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqadd_u64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqadd_u64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqadd_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqadd_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmlal_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqdmlal_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmlal_s16_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vqdmlal_s16, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmlal_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqdmlal_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmlal_s32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vqdmlal_s32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmlsl_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqdmlsl_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmlsl_s16_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vqdmlsl_s16, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmlsl_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqdmlsl_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmlsl_s32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vqdmlsl_s32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmulh_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqdmulh_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmulh_s16_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vqdmulh_s16, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmulh_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqdmulh_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmulh_s32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vqdmulh_s32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmull_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqdmull_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmull_s16_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vqdmull_s16, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmull_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqdmull_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqdmull_s32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vqdmull_s32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqmovn_s16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vqmovn_s16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqmovn_s32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vqmovn_s32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqmovn_s64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vqmovn_s64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqmovn_u16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vqmovn_u16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqmovn_u32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vqmovn_u32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqmovn_u64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vqmovn_u64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqmovun_s16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vqmovun_s16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqmovun_s32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vqmovun_s32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqmovun_s64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vqmovun_s64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqneg_s16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vqneg_s16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqneg_s32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vqneg_s32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqneg_s8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vqneg_s8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrdmulh_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrdmulh_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrdmulh_s16_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vqrdmulh_s16, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrdmulh_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrdmulh_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrdmulh_s32_imm | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_3src((dc), OP_vqrdmulh_s32, (Vd), (Vn), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshl_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshl_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshl_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshl_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshl_s64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshl_s64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshl_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshl_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshl_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshl_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshl_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshl_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshl_u64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshl_u64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshl_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshl_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshrn_s16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshrn_s16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshrn_s32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshrn_s32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshrn_s64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshrn_s64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshrn_u16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshrn_u16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshrn_u32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshrn_u32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshrn_u64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshrn_u64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshrun_s16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshrun_s16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshrun_s32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshrun_s32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqrshrun_s64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqrshrun_s64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshl_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshl_s16, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshl_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshl_s32, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshl_s64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshl_s64, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshl_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshl_s8, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshl_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshl_u16, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshl_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshl_u32, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshl_u64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshl_u64, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshl_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm_or_imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshl_u8, (Vd), (Vn), (Vm_or_imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshlu_s16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshlu_s16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshlu_s32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshlu_s32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshlu_s64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshlu_s64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshlu_s8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshlu_s8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshrn_s16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshrn_s16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshrn_s32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshrn_s32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshrn_s64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshrn_s64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshrn_u16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshrn_u16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshrn_u32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshrn_u32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshrn_u64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshrn_u64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshrun_s16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshrun_s16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshrun_s32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshrun_s32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqshrun_s64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vqshrun_s64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqsub_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqsub_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqsub_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqsub_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqsub_s64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqsub_s64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqsub_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqsub_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqsub_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqsub_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqsub_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqsub_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqsub_u64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqsub_u64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vqsub_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vqsub_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vraddhn_i16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vraddhn_i16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vraddhn_i32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vraddhn_i32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vraddhn_i64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vraddhn_i64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrecpe_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrecpe_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrecpe_u32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrecpe_u32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrecps_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrecps_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrev16_16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrev16_16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrev16_8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrev16_8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrev32_16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrev32_16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrev32_32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrev32_32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrev32_8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrev32_8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrev64_16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrev64_16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrev64_32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrev64_32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrev64_8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrev64_8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrhadd_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrhadd_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrhadd_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrhadd_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrhadd_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrhadd_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrhadd_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrhadd_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrhadd_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrhadd_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrhadd_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrhadd_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrinta_f32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrinta_f32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrinta_f64_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrinta_f64_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrintm_f32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrintm_f32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrintm_f64_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrintm_f64_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrintn_f32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrintn_f32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrintn_f64_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrintn_f64_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrintp_f32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrintp_f32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrintp_f64_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrintp_f64_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrintr_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrintr_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrintr_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrintr_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrintx_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrintx_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrintx_f32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrintx_f32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrintx_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrintx_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrintz_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrintz_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrintz_f32_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrintz_f32_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrintz_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrintz_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshl_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshl_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshl_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshl_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshl_s64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshl_s64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshl_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshl_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshl_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshl_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshl_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshl_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshl_u64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshl_u64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshl_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshl_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshr_s16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshr_s16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshr_s32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshr_s32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshr_s64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshr_s64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshr_s8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshr_s8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshr_u16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshr_u16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshr_u32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshr_u32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshr_u64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshr_u64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshr_u8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshr_u8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshrn_i16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshrn_i16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshrn_i32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshrn_i32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrshrn_i64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrshrn_i64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrsqrte_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrsqrte_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrsqrte_u32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vrsqrte_u32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrsqrts_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrsqrts_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrsra_s16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrsra_s16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrsra_s32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrsra_s32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrsra_s64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrsra_s64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrsra_s8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrsra_s8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrsra_u16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrsra_u16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrsra_u32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrsra_u32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrsra_u64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrsra_u64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrsra_u8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vrsra_u8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrsubhn_i16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrsubhn_i16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrsubhn_i32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrsubhn_i32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vrsubhn_i64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vrsubhn_i64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsel_eq_f32 | ( | dc, | |
| Vd, | |||
| imm, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_3src((dc), OP_vsel_eq_f32, (Vd), (imm), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsel_eq_f64 | ( | dc, | |
| Vd, | |||
| imm, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_3src((dc), OP_vsel_eq_f64, (Vd), (imm), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsel_ge_f32 | ( | dc, | |
| Vd, | |||
| imm, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_3src((dc), OP_vsel_ge_f32, (Vd), (imm), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsel_ge_f64 | ( | dc, | |
| Vd, | |||
| imm, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_3src((dc), OP_vsel_ge_f64, (Vd), (imm), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsel_gt_f32 | ( | dc, | |
| Vd, | |||
| imm, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_3src((dc), OP_vsel_gt_f32, (Vd), (imm), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsel_gt_f64 | ( | dc, | |
| Vd, | |||
| imm, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_3src((dc), OP_vsel_gt_f64, (Vd), (imm), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsel_vs_f32 | ( | dc, | |
| Vd, | |||
| imm, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_3src((dc), OP_vsel_vs_f32, (Vd), (imm), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsel_vs_f64 | ( | dc, | |
| Vd, | |||
| imm, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_3src((dc), OP_vsel_vs_f64, (Vd), (imm), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshl_i16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshl_i16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshl_i32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshl_i32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshl_i64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshl_i64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshl_i8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshl_i8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshl_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vshl_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshl_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vshl_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshl_s64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vshl_s64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshl_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vshl_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshl_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vshl_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshl_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vshl_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshl_u64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vshl_u64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshl_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vshl_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshll_i16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshll_i16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshll_i32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshll_i32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshll_i8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshll_i8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshll_s16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshll_s16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshll_s32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshll_s32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshll_s8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshll_s8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshll_u16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshll_u16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshll_u32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshll_u32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshll_u8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshll_u8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshr_s16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshr_s16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshr_s32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshr_s32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshr_s64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshr_s64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshr_s8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshr_s8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshr_u16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshr_u16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshr_u32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshr_u32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshr_u64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshr_u64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshr_u8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshr_u8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshrn_i16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshrn_i16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshrn_i32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshrn_i32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vshrn_i64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vshrn_i64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsli_16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsli_16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsli_32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsli_32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsli_64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsli_64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsli_8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsli_8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsqrt_f32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vsqrt_f32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsqrt_f64 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vsqrt_f64, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsra_s16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsra_s16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsra_s32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsra_s32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsra_s64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsra_s64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsra_s8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsra_s8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsra_u16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsra_u16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsra_u32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsra_u32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsra_u64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsra_u64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsra_u8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsra_u8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsri_16 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsri_16, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsri_32 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsri_32, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsri_64 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsri_64, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsri_8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vsri_8, (Vd), (Vm), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vst1_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst1_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst1_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst1_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst1_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst1_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst1_64 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst1_64_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst1_64_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst1_8 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst1_8_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst1_8_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst1_lane_16 | ( | dc, | |
| mem, | |||
| Vt, | |||
| imm, | |||
| imm2 | |||
| ) | instr_create_1dst_3src((dc), OP_vst1_lane_16, (mem), (Vt), (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vst1_lane_16_wbimm | ( | dc, | |
| mem, | |||
| Vt, | |||
| imm, | |||
| imm2 | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vst1_lane_16_wbreg | ( | dc, | |
| mem, | |||
| Vt, | |||
| imm, | |||
| imm2, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vst1_lane_32 | ( | dc, | |
| mem, | |||
| Vt, | |||
| imm, | |||
| imm2 | |||
| ) | instr_create_1dst_3src((dc), OP_vst1_lane_32, (mem), (Vt), (imm), (imm2)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vst1_lane_32_wbimm | ( | dc, | |
| mem, | |||
| Vt, | |||
| imm, | |||
| imm2 | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vst1_lane_32_wbreg | ( | dc, | |
| mem, | |||
| Vt, | |||
| imm, | |||
| imm2, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vst1_lane_8 | ( | dc, | |
| mem, | |||
| Vt, | |||
| imm | |||
| ) | instr_create_1dst_2src((dc), OP_vst1_lane_8, (mem), (Vt), (imm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vst1_lane_8_wbimm | ( | dc, | |
| mem, | |||
| Vt, | |||
| imm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vst1_lane_8_wbreg | ( | dc, | |
| mem, | |||
| Vt, | |||
| imm, | |||
| Rm | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vst2_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_8 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_8_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_8_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_lane_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_lane_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_lane_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_lane_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_lane_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_lane_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_lane_8 | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_lane_8_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst2_lane_8_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_8 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_8_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_8_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_lane_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_lane_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_lane_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_lane_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_lane_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_lane_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_lane_8 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_lane_8_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst3_lane_8_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_8 | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_8_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_8_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_lane_16 | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_lane_16_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_lane_16_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_lane_32 | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_lane_32_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_lane_32_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_lane_8 | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_lane_8_wbimm | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vst4_lane_8_wbreg | ( | dc, | |
| mem, | |||
| imm, | |||
| imm2, | |||
| Rm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| mem | The memory opnd_t operand. |
| imm | The integer constant opnd_t operand. |
| imm2 | The second integer constant opnd_t operand. |
| Rm | The source register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vstm | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) | instr_create_Ndst_Msrc_varsrc((dc), OP_vstm, 1, 0, list_len, 0, (mem), __VA_ARGS__) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vstm_wb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vstmdb | ( | dc, | |
| mem, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vstr | ( | dc, | |
| mem, | |||
| Vt | |||
| ) | instr_create_1dst_1src((dc), OP_vstr, (mem), (Vt)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsub_f32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsub_f32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsub_f64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsub_f64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsub_i16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsub_i16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsub_i32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsub_i32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsub_i64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsub_i64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsub_i8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsub_i8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsubhn_i16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsubhn_i16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsubhn_i32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsubhn_i32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsubhn_i64 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsubhn_i64, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsubl_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsubl_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsubl_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsubl_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsubl_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsubl_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsubl_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsubl_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsubl_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsubl_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsubl_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsubl_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsubw_s16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsubw_s16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsubw_s32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsubw_s32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsubw_s8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsubw_s8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsubw_u16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsubw_u16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsubw_u32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsubw_u32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vsubw_u8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vsubw_u8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vswp | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vswp, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vtbl_8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Vd | The destination SIMD register opnd_t operand. |
| Vm | The source SIMD register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vtbx_8 | ( | dc, | |
| Vd, | |||
| Vm, | |||
| list_len, | |||
| ... | |||
| ) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| Vd | The destination SIMD register opnd_t operand. |
| Vm | The source SIMD register opnd_t operand. |
| list_len | The number of registers in the register list. |
| ... | The register list as separate opnd_t arguments. The registers in the list must be in increasing order. |
| #define INSTR_CREATE_vtrn_16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vtrn_16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vtrn_32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vtrn_32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vtrn_8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vtrn_8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vtst_16 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vtst_16, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vtst_32 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vtst_32, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vtst_8 | ( | dc, | |
| Vd, | |||
| Vn, | |||
| Vm | |||
| ) | instr_create_1dst_2src((dc), OP_vtst_8, (Vd), (Vn), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vuzp_16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vuzp_16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vuzp_32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vuzp_32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vuzp_8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vuzp_8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vzip_16 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vzip_16, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vzip_32 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vzip_32, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_vzip_8 | ( | dc, | |
| Vd, | |||
| Vm | |||
| ) | instr_create_1dst_1src((dc), OP_vzip_8, (Vd), (Vm)) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| #define INSTR_CREATE_wfe | ( | dc | ) | instr_create_0dst_0src((dc), OP_wfe) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| #define INSTR_CREATE_wfi | ( | dc | ) | instr_create_0dst_0src((dc), OP_wfi) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| #define INSTR_CREATE_yield | ( | dc | ) | instr_create_0dst_0src((dc), OP_yield) |
This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| #define OPND_CREATE_ABSMEM | ( | addr, | |
| size | |||
| ) | opnd_create_rel_addr(addr, size) |
Create an absolute address operand encoded as pc-relative. Encoding will fail if addr is out of the maximum signed displacement reach for the architecture and ISA mode.
| #define OPND_CREATE_INT | ( | val | ) | OPND_CREATE_INTPTR(val) |
Create an immediate integer operand. For ARM, the size of an immediate is ignored when encoding, so there is no need to specify the final size.
| #define OPND_CREATE_INT_MSR_G | ( | ) | opnd_create_immed_int(EFLAGS_MSR_G, OPSZ_4b) |
The immediate opnd_t for use with OP_msr to write the apsr_g status flags.
| #define OPND_CREATE_INT_MSR_NZCVQ | ( | ) | opnd_create_immed_int(EFLAGS_MSR_NZCVQ, OPSZ_4b) |
The immediate opnd_t for use with OP_msr to write the nzcvq status flags.
| #define OPND_CREATE_INT_MSR_NZCVQG | ( | ) | opnd_create_immed_int(EFLAGS_MSR_NZCVQG, OPSZ_4b) |
The immediate opnd_t for use with OP_msr to write the apsr_nzcvqg status flags.
| #define OPND_CREATE_MEMLIST | ( | base | ) | opnd_create_base_disp(base, DR_REG_NULL, 0, 0, OPSZ_VAR_REGLIST) |
A memory opnd_t that auto-sizes at encode time to match a register list.
| #define OPND_CREATE_NEG_REG | ( | reg | ) | opnd_create_reg_ex(reg, 0, DR_OPND_NEGATED) |
Create a negated register operand.
| #define XINST_CREATE_add | ( | dc, | |
| d, | |||
| s | |||
| ) | INSTR_CREATE_add((dc), (d), (d), (s)) |
This platform-independent macro creates an instr_t for an addition instruction that does not affect the status flags.
| #define XINST_CREATE_add_2src | ( | dc, | |
| d, | |||
| s1, | |||
| s2 | |||
| ) | INSTR_CREATE_add((dc), (d), (s1), (s2)) |
This platform-independent macro creates an instr_t for an addition instruction that does not affect the status flags and takes two sources plus a destination.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| d | The opnd_t explicit destination operand for the instruction. |
| s1 | The opnd_t explicit first source operand for the instruction. This must be a register. |
| s2 | The opnd_t explicit source operand for the instruction. This can be either a register or a 32-bit immediate integer on x86. |
| #define XINST_CREATE_add_s | ( | dc, | |
| d, | |||
| s | |||
| ) | INSTR_CREATE_adds((dc), (d), (d), (s)) |
This platform-independent macro creates an instr_t for an addition instruction that does affect the status flags.
| #define XINST_CREATE_add_sll | ( | dc, | |
| d, | |||
| s1, | |||
| s2_toshift, | |||
| shift_amount | |||
| ) |
This platform-independent macro creates an instr_t for an addition instruction that does not affect the status flags and takes two register sources plus a destination, with one source being shifted logically left by an immediate amount that is limited to either 0, 1, 2, or 3.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| d | The opnd_t explicit destination operand for the instruction. |
| s1 | The opnd_t explicit first source operand for the instruction. This must be a register. |
| s2_toshift | The opnd_t explicit source operand for the instruction. This must be a register. |
| shift_amount | An integer value that must be either 0, 1, 2, or 3. |
| #define XINST_CREATE_and_s | ( | dc, | |
| d, | |||
| s | |||
| ) | INSTR_CREATE_ands((dc), (d), (d), (s)) |
This platform-independent macro creates an instr_t for a bitwise and instruction that does affect the status flags.
| #define XINST_CREATE_call | ( | dc, | |
| t | |||
| ) | INSTR_CREATE_bl((dc), (t)) |
This platform-independent macro creates an instr_t for an unconditional branch instruction.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| t | The opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded). |
| #define XINST_CREATE_call_reg | ( | dc, | |
| r | |||
| ) | INSTR_CREATE_blx_ind(dc, r) |
| #define XINST_CREATE_cmp | ( | dc, | |
| s1, | |||
| s2 | |||
| ) | INSTR_CREATE_cmp((dc), (s1), (s2)) |
| #define XINST_CREATE_debug_instr | ( | dc | ) | INSTR_CREATE_bkpt((dc), OPND_CREATE_INT8(1)) |
| #define XINST_CREATE_interrupt | ( | dc, | |
| i | |||
| ) | INSTR_CREATE_svc(dc, (i)) |
| #define XINST_CREATE_jump | ( | dc, | |
| t | |||
| ) | INSTR_CREATE_b((dc), (t)) |
This platform-independent macro creates an instr_t for an unconditional branch instruction.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| t | The opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded). |
| #define XINST_CREATE_jump_cond | ( | dc, | |
| pred, | |||
| t | |||
| ) | (INSTR_PRED(INSTR_CREATE_b((dc), (t)), (pred))) |
This platform-independent macro creates an instr_t for a conditional branch instruction that branches if the previously-set condition codes indicate the condition indicated by pred.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| pred | The dr_pred_type_t condition to match. |
| t | The opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded). |
| #define XINST_CREATE_jump_mem | ( | dc, | |
| m | |||
| ) | INSTR_CREATE_ldr((dc), opnd_create_reg(DR_REG_PC), (m)) |
| #define XINST_CREATE_jump_reg | ( | dc, | |
| r | |||
| ) | INSTR_CREATE_bx((dc), (r)) |
| #define XINST_CREATE_jump_short | ( | dc, | |
| t | |||
| ) |
This platform-independent macro creates an instr_t for an unconditional branch instruction with the smallest available reach.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| t | The opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded). |
| #define XINST_CREATE_load | ( | dc, | |
| r, | |||
| m | |||
| ) | INSTR_CREATE_ldr((dc), (r), (m)) |
| #define XINST_CREATE_load_1byte | ( | dc, | |
| r, | |||
| m | |||
| ) | INSTR_CREATE_ldrb((dc), (r), (m)) |
| #define XINST_CREATE_load_1byte_zext4 | ( | dc, | |
| r, | |||
| m | |||
| ) | INSTR_CREATE_ldrb((dc), (r), (m)) |
| #define XINST_CREATE_load_2bytes | ( | dc, | |
| r, | |||
| m | |||
| ) | INSTR_CREATE_ldrh((dc), (r), (m)) |
| #define XINST_CREATE_load_int | ( | dc, | |
| r, | |||
| i | |||
| ) |
This platform-independent macro creates an instr_t for an immediate integer load instruction.
| dc | The void * dcontext used to allocate memory for the instr_t. |
| r | The destination register opnd. |
| i | The source immediate integer opnd. |
| #define XINST_CREATE_load_pair | ( | dc, | |
| r1, | |||
| r2, | |||
| m | |||
| ) | INSTR_CREATE_ldrd((dc), (r1), (r2), (m)) |
| #define XINST_CREATE_load_simd | ( | dc, | |
| r, | |||
| m | |||
| ) | INSTR_CREATE_vldr((dc), (r), (m)) |
| #define XINST_CREATE_move | ( | dc, | |
| d, | |||
| s | |||
| ) | INSTR_CREATE_mov((dc), (d), (s)) |
| #define XINST_CREATE_nop | ( | dc | ) | INSTR_CREATE_nop(dc) |
| #define XINST_CREATE_return | ( | dc | ) | INSTR_CREATE_pop(dc, opnd_create_reg(DR_REG_PC)) |
| #define XINST_CREATE_slr_s | ( | dc, | |
| d, | |||
| s | |||
| ) | INSTR_CREATE_lsrs((dc), (d), (d), (s)) |
This platform-independent macro creates an instr_t for a logical right shift instruction that does affect the status flags.
| #define XINST_CREATE_store | ( | dc, | |
| m, | |||
| r | |||
| ) | INSTR_CREATE_str((dc), (m), (r)) |
| #define XINST_CREATE_store_1byte | ( | dc, | |
| m, | |||
| r | |||
| ) | INSTR_CREATE_strb((dc), (m), (r)) |
| #define XINST_CREATE_store_2bytes | ( | dc, | |
| m, | |||
| r | |||
| ) | INSTR_CREATE_strh((dc), (m), (r)) |
| #define XINST_CREATE_store_pair | ( | dc, | |
| m, | |||
| r1, | |||
| r2 | |||
| ) | INSTR_CREATE_strd((dc), (m), (r1), (r2)) |
| #define XINST_CREATE_store_simd | ( | dc, | |
| m, | |||
| r | |||
| ) | INSTR_CREATE_vstr((dc), (m), (r)) |
| #define XINST_CREATE_sub | ( | dc, | |
| d, | |||
| s | |||
| ) | INSTR_CREATE_sub((dc), (d), (d), (s)) |
This platform-independent macro creates an instr_t for a subtraction instruction that does not affect the status flags.
| #define XINST_CREATE_sub_s | ( | dc, | |
| d, | |||
| s | |||
| ) | INSTR_CREATE_subs((dc), (d), (d), (s)) |
This platform-independent macro creates an instr_t for a subtraction instruction that does affect the status flags.
| anonymous enum |
Immediate values for INSTR_CREATE_dmb().
| Enumerator | |
|---|---|
| DR_VG_NUM_ARGS | Defines the maximum number of arguments that can be passed to a Valgrind annotation, and accordingly specifies the length of the array vg_client_request_t.args. |
| DR_NOTE_ANNOTATION | Identifies an annotation point. This label will be replaced by a clean call to the registered annotation handler. |
| DR_NOTE_CLEAN_CALL_END | Identifies the end of a clean call. |
| DR_NOTE_REG_BARRIER | Identifies a point at which clients should restore all registers to their application values, as required for DR's internal block mangling. |
| EFLAGS_CF | The bit in the eflags register of CF (Carry Flag). |
| EFLAGS_PF | The bit in the eflags register of PF (Parity Flag). |
| EFLAGS_AF | The bit in the eflags register of AF (Aux Carry Flag). |
| EFLAGS_ZF | The bit in the eflags register of ZF (Zero Flag). |
| EFLAGS_SF | The bit in the eflags register of SF (Sign Flag). |
| EFLAGS_DF | The bit in the eflags register of DF (Direction Flag). |
| EFLAGS_OF | The bit in the eflags register of OF (Overflow Flag). |
| EFLAGS_ARITH | The bits in the eflags register of CF, PF, AF, ZF, SF, OF. |
| DR_DMB_OSHLD | DMB Outer Shareable - Loads. |
| DR_DMB_OSHST | DMB Outer Shareable - Stores. |
| DR_DMB_OSH | DMB Outer Shareable - Loads and Stores. |
| DR_DMB_NSHLD | DMB Non Shareable - Loads. |
| DR_DMB_NSHST | DMB Non Shareable - Stores. |
| DR_DMB_NSH | DMB Non Shareable - Loads and Stores. |
| DR_DMB_ISHLD | DMB Inner Shareable - Loads. |
| DR_DMB_ISHST | DMB Inner Shareable - Stores. |
| DR_DMB_ISH | DMB Inner Shareable - Loads and Stores. |
| DR_DMB_LD | DMB Full System - Loads. |
| DR_DMB_ST | DMB Full System - Stores. |
| DR_DMB_SY | DMB Full System - Loads and Stores. |
| OP_UNDECODED | INVALID opcode |
| OP_CONTD | UNDECODED opcode |
| OP_LABEL | CONTD opcode |
| OP_adc | LABEL opcode ARM adc opcode. |
| OP_adcs | ARM adcs opcode. |
| OP_add | ARM add opcode. |
| OP_adds | ARM adds opcode. |
| OP_addw | ARM addw opcode. |
| OP_aesd_8 | ARM aesd_8 opcode. |
| OP_aese_8 | ARM aese_8 opcode. |
| OP_aesimc_8 | ARM aesimc_8 opcode. |
| OP_aesmc_8 | ARM aesmc_8 opcode. |
| OP_and | ARM and opcode. |
| OP_ands | ARM ands opcode. |
| OP_asr | ARM asr opcode. |
| OP_asrs | ARM asrs opcode. |
| OP_b | ARM b opcode. |
| OP_b_short | ARM b_short opcode. |
| OP_bfc | ARM bfc opcode. |
| OP_bfi | ARM bfi opcode. |
| OP_bic | ARM bic opcode. |
| OP_bics | ARM bics opcode. |
| OP_bkpt | ARM bkpt opcode. |
| OP_bl | ARM bl opcode. |
| OP_blx | ARM blx opcode. |
| OP_blx_ind | ARM blx_ind opcode. |
| OP_bx | ARM bx opcode. |
| OP_bxj | ARM bxj opcode. |
| OP_cbnz | ARM cbnz opcode. |
| OP_cbz | ARM cbz opcode. |
| OP_cdp | ARM cdp opcode. |
| OP_cdp2 | ARM cdp2 opcode. |
| OP_clrex | ARM clrex opcode. |
| OP_clz | ARM clz opcode. |
| OP_cmn | ARM cmn opcode. |
| OP_cmp | ARM cmp opcode. |
| OP_cps | ARM cps opcode. |
| OP_cpsid | ARM cpsid opcode. |
| OP_cpsie | ARM cpsie opcode. |
| OP_crc32b | ARM crc32b opcode. |
| OP_crc32cb | ARM crc32cb opcode. |
| OP_crc32h | ARM crc32h opcode. |
| OP_crc32ch | ARM crc32ch opcode. |
| OP_crc32w | ARM crc32w opcode. |
| OP_crc32cw | ARM crc32cw opcode. |
| OP_dbg | ARM dbg opcode. |
| OP_dcps1 | ARM dcps1 opcode. |
| OP_dcps2 | ARM dcps2 opcode. |
| OP_dcps3 | ARM dcps3 opcode. |
| OP_dmb | ARM dmb opcode. |
| OP_dsb | ARM dsb opcode. |
| OP_enterx | ARM enterx opcode. |
| OP_eor | ARM eor opcode. |
| OP_eors | ARM eors opcode. |
| OP_eret | ARM eret opcode. |
| OP_hlt | ARM hlt opcode. |
| OP_hvc | ARM hvc opcode. |
| OP_isb | ARM isb opcode. |
| OP_it | ARM it opcode. |
| OP_lda | ARM lda opcode. |
| OP_ldab | ARM ldab opcode. |
| OP_ldaex | ARM ldaex opcode. |
| OP_ldaexb | ARM ldaexb opcode. |
| OP_ldaexd | ARM ldaexd opcode. |
| OP_ldaexh | ARM ldaexh opcode. |
| OP_ldah | ARM ldah opcode. |
| OP_ldc | ARM ldc opcode. |
| OP_ldc2 | ARM ldc2 opcode. |
| OP_ldc2l | ARM ldc2l opcode. |
| OP_ldcl | ARM ldcl opcode. |
| OP_ldm | ARM ldm opcode. |
| OP_ldm_priv | ARM ldm_priv opcode. |
| OP_ldmda | ARM ldmda opcode. |
| OP_ldmda_priv | ARM ldmda_priv opcode. |
| OP_ldmdb | ARM ldmdb opcode. |
| OP_ldmdb_priv | ARM ldmdb_priv opcode. |
| OP_ldmib | ARM ldmib opcode. |
| OP_ldmib_priv | ARM ldmib_priv opcode. |
| OP_ldr | ARM ldr opcode. |
| OP_ldrb | ARM ldrb opcode. |
| OP_ldrbt | ARM ldrbt opcode. |
| OP_ldrd | ARM ldrd opcode. |
| OP_ldrex | ARM ldrex opcode. |
| OP_ldrexb | ARM ldrexb opcode. |
| OP_ldrexd | ARM ldrexd opcode. |
| OP_ldrexh | ARM ldrexh opcode. |
| OP_ldrh | ARM ldrh opcode. |
| OP_ldrht | ARM ldrht opcode. |
| OP_ldrsb | ARM ldrsb opcode. |
| OP_ldrsbt | ARM ldrsbt opcode. |
| OP_ldrsh | ARM ldrsh opcode. |
| OP_ldrsht | ARM ldrsht opcode. |
| OP_ldrt | ARM ldrt opcode. |
| OP_leavex | ARM leavex opcode. |
| OP_lsl | ARM lsl opcode. |
| OP_lsls | ARM lsls opcode. |
| OP_lsr | ARM lsr opcode. |
| OP_lsrs | ARM lsrs opcode. |
| OP_mcr | ARM mcr opcode. |
| OP_mcr2 | ARM mcr2 opcode. |
| OP_mcrr | ARM mcrr opcode. |
| OP_mcrr2 | ARM mcrr2 opcode. |
| OP_mla | ARM mla opcode. |
| OP_mlas | ARM mlas opcode. |
| OP_mls | ARM mls opcode. |
| OP_mov | ARM mov opcode. |
| OP_movs | ARM movs opcode. |
| OP_movt | ARM movt opcode. |
| OP_movw | ARM movw opcode. |
| OP_mrc | ARM mrc opcode. |
| OP_mrc2 | ARM mrc2 opcode. |
| OP_mrrc | ARM mrrc opcode. |
| OP_mrrc2 | ARM mrrc2 opcode. |
| OP_mrs | ARM mrs opcode. |
| OP_mrs_priv | ARM mrs_priv opcode. |
| OP_msr | ARM msr opcode. |
| OP_msr_priv | ARM msr_priv opcode. |
| OP_mul | ARM mul opcode. |
| OP_muls | ARM muls opcode. |
| OP_mvn | ARM mvn opcode. |
| OP_mvns | ARM mvns opcode. |
| OP_nop | ARM nop opcode. |
| OP_orn | ARM orn opcode. |
| OP_orns | ARM orns opcode. |
| OP_orr | ARM orr opcode. |
| OP_orrs | ARM orrs opcode. |
| OP_pkhbt | ARM pkhbt opcode. |
| OP_pkhtb | ARM pkhtb opcode. |
| OP_pld | ARM pld opcode. |
| OP_pldw | ARM pldw opcode. |
| OP_pli | ARM pli opcode. |
| OP_qadd | ARM qadd opcode. |
| OP_qadd16 | ARM qadd16 opcode. |
| OP_qadd8 | ARM qadd8 opcode. |
| OP_qasx | ARM qasx opcode. |
| OP_qdadd | ARM qdadd opcode. |
| OP_qdsub | ARM qdsub opcode. |
| OP_qsax | ARM qsax opcode. |
| OP_qsub | ARM qsub opcode. |
| OP_qsub16 | ARM qsub16 opcode. |
| OP_qsub8 | ARM qsub8 opcode. |
| OP_rbit | ARM rbit opcode. |
| OP_rev | ARM rev opcode. |
| OP_rev16 | ARM rev16 opcode. |
| OP_revsh | ARM revsh opcode. |
| OP_rfe | ARM rfe opcode. |
| OP_rfeda | ARM rfeda opcode. |
| OP_rfedb | ARM rfedb opcode. |
| OP_rfeib | ARM rfeib opcode. |
| OP_ror | ARM ror opcode. |
| OP_rors | ARM rors opcode. |
| OP_rrx | ARM rrx opcode. |
| OP_rrxs | ARM rrxs opcode. |
| OP_rsb | ARM rsb opcode. |
| OP_rsbs | ARM rsbs opcode. |
| OP_rsc | ARM rsc opcode. |
| OP_rscs | ARM rscs opcode. |
| OP_sadd16 | ARM sadd16 opcode. |
| OP_sadd8 | ARM sadd8 opcode. |
| OP_sasx | ARM sasx opcode. |
| OP_sbc | ARM sbc opcode. |
| OP_sbcs | ARM sbcs opcode. |
| OP_sbfx | ARM sbfx opcode. |
| OP_sdiv | ARM sdiv opcode. |
| OP_sel | ARM sel opcode. |
| OP_setend | ARM setend opcode. |
| OP_sev | ARM sev opcode. |
| OP_sevl | ARM sevl opcode. |
| OP_sha1c_32 | ARM sha1c_32 opcode. |
| OP_sha1h_32 | ARM sha1h_32 opcode. |
| OP_sha1m_32 | ARM sha1m_32 opcode. |
| OP_sha1p_32 | ARM sha1p_32 opcode. |
| OP_sha1su0_32 | ARM sha1su0_32 opcode. |
| OP_sha1su1_32 | ARM sha1su1_32 opcode. |
| OP_sha256h2_32 | ARM sha256h2_32 opcode. |
| OP_sha256h_32 | ARM sha256h_32 opcode. |
| OP_sha256su0_32 | ARM sha256su0_32 opcode. |
| OP_sha256su1_32 | ARM sha256su1_32 opcode. |
| OP_shadd16 | ARM shadd16 opcode. |
| OP_shadd8 | ARM shadd8 opcode. |
| OP_shasx | ARM shasx opcode. |
| OP_shsax | ARM shsax opcode. |
| OP_shsub16 | ARM shsub16 opcode. |
| OP_shsub8 | ARM shsub8 opcode. |
| OP_smc | ARM smc opcode. |
| OP_smlabb | ARM smlabb opcode. |
| OP_smlabt | ARM smlabt opcode. |
| OP_smlad | ARM smlad opcode. |
| OP_smladx | ARM smladx opcode. |
| OP_smlal | ARM smlal opcode. |
| OP_smlalbb | ARM smlalbb opcode. |
| OP_smlalbt | ARM smlalbt opcode. |
| OP_smlald | ARM smlald opcode. |
| OP_smlaldx | ARM smlaldx opcode. |
| OP_smlals | ARM smlals opcode. |
| OP_smlaltb | ARM smlaltb opcode. |
| OP_smlaltt | ARM smlaltt opcode. |
| OP_smlatb | ARM smlatb opcode. |
| OP_smlatt | ARM smlatt opcode. |
| OP_smlawb | ARM smlawb opcode. |
| OP_smlawt | ARM smlawt opcode. |
| OP_smlsd | ARM smlsd opcode. |
| OP_smlsdx | ARM smlsdx opcode. |
| OP_smlsld | ARM smlsld opcode. |
| OP_smlsldx | ARM smlsldx opcode. |
| OP_smmla | ARM smmla opcode. |
| OP_smmlar | ARM smmlar opcode. |
| OP_smmls | ARM smmls opcode. |
| OP_smmlsr | ARM smmlsr opcode. |
| OP_smmul | ARM smmul opcode. |
| OP_smmulr | ARM smmulr opcode. |
| OP_smuad | ARM smuad opcode. |
| OP_smuadx | ARM smuadx opcode. |
| OP_smulbb | ARM smulbb opcode. |
| OP_smulbt | ARM smulbt opcode. |
| OP_smull | ARM smull opcode. |
| OP_smulls | ARM smulls opcode. |
| OP_smultb | ARM smultb opcode. |
| OP_smultt | ARM smultt opcode. |
| OP_smulwb | ARM smulwb opcode. |
| OP_smulwt | ARM smulwt opcode. |
| OP_smusd | ARM smusd opcode. |
| OP_smusdx | ARM smusdx opcode. |
| OP_srs | ARM srs opcode. |
| OP_srsda | ARM srsda opcode. |
| OP_srsdb | ARM srsdb opcode. |
| OP_srsib | ARM srsib opcode. |
| OP_ssat | ARM ssat opcode. |
| OP_ssat16 | ARM ssat16 opcode. |
| OP_ssax | ARM ssax opcode. |
| OP_ssub16 | ARM ssub16 opcode. |
| OP_ssub8 | ARM ssub8 opcode. |
| OP_stc | ARM stc opcode. |
| OP_stc2 | ARM stc2 opcode. |
| OP_stc2l | ARM stc2l opcode. |
| OP_stcl | ARM stcl opcode. |
| OP_stl | ARM stl opcode. |
| OP_stlb | ARM stlb opcode. |
| OP_stlex | ARM stlex opcode. |
| OP_stlexb | ARM stlexb opcode. |
| OP_stlexd | ARM stlexd opcode. |
| OP_stlexh | ARM stlexh opcode. |
| OP_stlh | ARM stlh opcode. |
| OP_stm | ARM stm opcode. |
| OP_stm_priv | ARM stm_priv opcode. |
| OP_stmda | ARM stmda opcode. |
| OP_stmda_priv | ARM stmda_priv opcode. |
| OP_stmdb | ARM stmdb opcode. |
| OP_stmdb_priv | ARM stmdb_priv opcode. |
| OP_stmib | ARM stmib opcode. |
| OP_stmib_priv | ARM stmib_priv opcode. |
| OP_str | ARM str opcode. |
| OP_strb | ARM strb opcode. |
| OP_strbt | ARM strbt opcode. |
| OP_strd | ARM strd opcode. |
| OP_strex | ARM strex opcode. |
| OP_strexb | ARM strexb opcode. |
| OP_strexd | ARM strexd opcode. |
| OP_strexh | ARM strexh opcode. |
| OP_strh | ARM strh opcode. |
| OP_strht | ARM strht opcode. |
| OP_strt | ARM strt opcode. |
| OP_sub | ARM sub opcode. |
| OP_subs | ARM subs opcode. |
| OP_subw | ARM subw opcode. |
| OP_svc | ARM svc opcode. |
| OP_swp | ARM swp opcode. |
| OP_swpb | ARM swpb opcode. |
| OP_sxtab | ARM sxtab opcode. |
| OP_sxtab16 | ARM sxtab16 opcode. |
| OP_sxtah | ARM sxtah opcode. |
| OP_sxtb | ARM sxtb opcode. |
| OP_sxtb16 | ARM sxtb16 opcode. |
| OP_sxth | ARM sxth opcode. |
| OP_tbb | ARM tbb opcode. |
| OP_tbh | ARM tbh opcode. |
| OP_teq | ARM teq opcode. |
| OP_tst | ARM tst opcode. |
| OP_uadd16 | ARM uadd16 opcode. |
| OP_uadd8 | ARM uadd8 opcode. |
| OP_uasx | ARM uasx opcode. |
| OP_ubfx | ARM ubfx opcode. |
| OP_udf | ARM udf opcode. |
| OP_udiv | ARM udiv opcode. |
| OP_uhadd16 | ARM uhadd16 opcode. |
| OP_uhadd8 | ARM uhadd8 opcode. |
| OP_uhasx | ARM uhasx opcode. |
| OP_uhsax | ARM uhsax opcode. |
| OP_uhsub16 | ARM uhsub16 opcode. |
| OP_uhsub8 | ARM uhsub8 opcode. |
| OP_umaal | ARM umaal opcode. |
| OP_umlal | ARM umlal opcode. |
| OP_umlals | ARM umlals opcode. |
| OP_umull | ARM umull opcode. |
| OP_umulls | ARM umulls opcode. |
| OP_uqadd16 | ARM uqadd16 opcode. |
| OP_uqadd8 | ARM uqadd8 opcode. |
| OP_uqasx | ARM uqasx opcode. |
| OP_uqsax | ARM uqsax opcode. |
| OP_uqsub16 | ARM uqsub16 opcode. |
| OP_uqsub8 | ARM uqsub8 opcode. |
| OP_usad8 | ARM usad8 opcode. |
| OP_usada8 | ARM usada8 opcode. |
| OP_usat | ARM usat opcode. |
| OP_usat16 | ARM usat16 opcode. |
| OP_usax | ARM usax opcode. |
| OP_usub16 | ARM usub16 opcode. |
| OP_usub8 | ARM usub8 opcode. |
| OP_uxtab | ARM uxtab opcode. |
| OP_uxtab16 | ARM uxtab16 opcode. |
| OP_uxtah | ARM uxtah opcode. |
| OP_uxtb | ARM uxtb opcode. |
| OP_uxtb16 | ARM uxtb16 opcode. |
| OP_uxth | ARM uxth opcode. |
| OP_vaba_s16 | ARM vaba_s16 opcode. |
| OP_vaba_s32 | ARM vaba_s32 opcode. |
| OP_vaba_s8 | ARM vaba_s8 opcode. |
| OP_vaba_u16 | ARM vaba_u16 opcode. |
| OP_vaba_u32 | ARM vaba_u32 opcode. |
| OP_vaba_u8 | ARM vaba_u8 opcode. |
| OP_vabal_s16 | ARM vabal_s16 opcode. |
| OP_vabal_s32 | ARM vabal_s32 opcode. |
| OP_vabal_s8 | ARM vabal_s8 opcode. |
| OP_vabal_u16 | ARM vabal_u16 opcode. |
| OP_vabal_u32 | ARM vabal_u32 opcode. |
| OP_vabal_u8 | ARM vabal_u8 opcode. |
| OP_vabd_s16 | ARM vabd_s16 opcode. |
| OP_vabd_s32 | ARM vabd_s32 opcode. |
| OP_vabd_s8 | ARM vabd_s8 opcode. |
| OP_vabd_u16 | ARM vabd_u16 opcode. |
| OP_vabd_u32 | ARM vabd_u32 opcode. |
| OP_vabd_u8 | ARM vabd_u8 opcode. |
| OP_vabdl_s16 | ARM vabdl_s16 opcode. |
| OP_vabdl_s32 | ARM vabdl_s32 opcode. |
| OP_vabdl_s8 | ARM vabdl_s8 opcode. |
| OP_vabdl_u16 | ARM vabdl_u16 opcode. |
| OP_vabdl_u32 | ARM vabdl_u32 opcode. |
| OP_vabdl_u8 | ARM vabdl_u8 opcode. |
| OP_vabs_f32 | ARM vabs_f32 opcode. |
| OP_vabs_f64 | ARM vabs_f64 opcode. |
| OP_vabs_s16 | ARM vabs_s16 opcode. |
| OP_vabs_s32 | ARM vabs_s32 opcode. |
| OP_vabs_s8 | ARM vabs_s8 opcode. |
| OP_vacge_f32 | ARM vacge_f32 opcode. |
| OP_vacgt_f32 | ARM vacgt_f32 opcode. |
| OP_vadd_f32 | ARM vadd_f32 opcode. |
| OP_vadd_f64 | ARM vadd_f64 opcode. |
| OP_vadd_i16 | ARM vadd_i16 opcode. |
| OP_vadd_i32 | ARM vadd_i32 opcode. |
| OP_vadd_i64 | ARM vadd_i64 opcode. |
| OP_vadd_i8 | ARM vadd_i8 opcode. |
| OP_vaddhn_i16 | ARM vaddhn_i16 opcode. |
| OP_vaddhn_i32 | ARM vaddhn_i32 opcode. |
| OP_vaddhn_i64 | ARM vaddhn_i64 opcode. |
| OP_vaddl_s16 | ARM vaddl_s16 opcode. |
| OP_vaddl_s32 | ARM vaddl_s32 opcode. |
| OP_vaddl_s8 | ARM vaddl_s8 opcode. |
| OP_vaddl_u16 | ARM vaddl_u16 opcode. |
| OP_vaddl_u32 | ARM vaddl_u32 opcode. |
| OP_vaddl_u8 | ARM vaddl_u8 opcode. |
| OP_vaddw_s16 | ARM vaddw_s16 opcode. |
| OP_vaddw_s32 | ARM vaddw_s32 opcode. |
| OP_vaddw_s8 | ARM vaddw_s8 opcode. |
| OP_vaddw_u16 | ARM vaddw_u16 opcode. |
| OP_vaddw_u32 | ARM vaddw_u32 opcode. |
| OP_vaddw_u8 | ARM vaddw_u8 opcode. |
| OP_vand | ARM vand opcode. |
| OP_vbic | ARM vbic opcode. |
| OP_vbic_i16 | ARM vbic_i16 opcode. |
| OP_vbic_i32 | ARM vbic_i32 opcode. |
| OP_vbif | ARM vbif opcode. |
| OP_vbit | ARM vbit opcode. |
| OP_vbsl | ARM vbsl opcode. |
| OP_vceq_f32 | ARM vceq_f32 opcode. |
| OP_vceq_i16 | ARM vceq_i16 opcode. |
| OP_vceq_i32 | ARM vceq_i32 opcode. |
| OP_vceq_i8 | ARM vceq_i8 opcode. |
| OP_vcge_f32 | ARM vcge_f32 opcode. |
| OP_vcge_s16 | ARM vcge_s16 opcode. |
| OP_vcge_s32 | ARM vcge_s32 opcode. |
| OP_vcge_s8 | ARM vcge_s8 opcode. |
| OP_vcge_u16 | ARM vcge_u16 opcode. |
| OP_vcge_u32 | ARM vcge_u32 opcode. |
| OP_vcge_u8 | ARM vcge_u8 opcode. |
| OP_vcgt_f32 | ARM vcgt_f32 opcode. |
| OP_vcgt_s16 | ARM vcgt_s16 opcode. |
| OP_vcgt_s32 | ARM vcgt_s32 opcode. |
| OP_vcgt_s8 | ARM vcgt_s8 opcode. |
| OP_vcgt_u16 | ARM vcgt_u16 opcode. |
| OP_vcgt_u32 | ARM vcgt_u32 opcode. |
| OP_vcgt_u8 | ARM vcgt_u8 opcode. |
| OP_vcle_f32 | ARM vcle_f32 opcode. |
| OP_vcle_s16 | ARM vcle_s16 opcode. |
| OP_vcle_s32 | ARM vcle_s32 opcode. |
| OP_vcle_s8 | ARM vcle_s8 opcode. |
| OP_vcls_s16 | ARM vcls_s16 opcode. |
| OP_vcls_s32 | ARM vcls_s32 opcode. |
| OP_vcls_s8 | ARM vcls_s8 opcode. |
| OP_vclt_f32 | ARM vclt_f32 opcode. |
| OP_vclt_s16 | ARM vclt_s16 opcode. |
| OP_vclt_s32 | ARM vclt_s32 opcode. |
| OP_vclt_s8 | ARM vclt_s8 opcode. |
| OP_vclz_i16 | ARM vclz_i16 opcode. |
| OP_vclz_i32 | ARM vclz_i32 opcode. |
| OP_vclz_i8 | ARM vclz_i8 opcode. |
| OP_vcmp_f32 | ARM vcmp_f32 opcode. |
| OP_vcmp_f64 | ARM vcmp_f64 opcode. |
| OP_vcmpe_f32 | ARM vcmpe_f32 opcode. |
| OP_vcmpe_f64 | ARM vcmpe_f64 opcode. |
| OP_vcnt_8 | ARM vcnt_8 opcode. |
| OP_vcvt_f16_f32 | ARM vcvt_f16_f32 opcode. |
| OP_vcvt_f32_f16 | ARM vcvt_f32_f16 opcode. |
| OP_vcvt_f32_f64 | ARM vcvt_f32_f64 opcode. |
| OP_vcvt_f32_s16 | ARM vcvt_f32_s16 opcode. |
| OP_vcvt_f32_s32 | ARM vcvt_f32_s32 opcode. |
| OP_vcvt_f32_u16 | ARM vcvt_f32_u16 opcode. |
| OP_vcvt_f32_u32 | ARM vcvt_f32_u32 opcode. |
| OP_vcvt_f64_f32 | ARM vcvt_f64_f32 opcode. |
| OP_vcvt_f64_s16 | ARM vcvt_f64_s16 opcode. |
| OP_vcvt_f64_s32 | ARM vcvt_f64_s32 opcode. |
| OP_vcvt_f64_u16 | ARM vcvt_f64_u16 opcode. |
| OP_vcvt_f64_u32 | ARM vcvt_f64_u32 opcode. |
| OP_vcvt_s16_f32 | ARM vcvt_s16_f32 opcode. |
| OP_vcvt_s16_f64 | ARM vcvt_s16_f64 opcode. |
| OP_vcvt_s32_f32 | ARM vcvt_s32_f32 opcode. |
| OP_vcvt_s32_f64 | ARM vcvt_s32_f64 opcode. |
| OP_vcvt_u16_f32 | ARM vcvt_u16_f32 opcode. |
| OP_vcvt_u16_f64 | ARM vcvt_u16_f64 opcode. |
| OP_vcvt_u32_f32 | ARM vcvt_u32_f32 opcode. |
| OP_vcvt_u32_f64 | ARM vcvt_u32_f64 opcode. |
| OP_vcvta_s32_f32 | ARM vcvta_s32_f32 opcode. |
| OP_vcvta_s32_f64 | ARM vcvta_s32_f64 opcode. |
| OP_vcvta_u32_f32 | ARM vcvta_u32_f32 opcode. |
| OP_vcvta_u32_f64 | ARM vcvta_u32_f64 opcode. |
| OP_vcvtb_f16_f32 | ARM vcvtb_f16_f32 opcode. |
| OP_vcvtb_f16_f64 | ARM vcvtb_f16_f64 opcode. |
| OP_vcvtb_f32_f16 | ARM vcvtb_f32_f16 opcode. |
| OP_vcvtb_f64_f16 | ARM vcvtb_f64_f16 opcode. |
| OP_vcvtm_s32_f32 | ARM vcvtm_s32_f32 opcode. |
| OP_vcvtm_s32_f64 | ARM vcvtm_s32_f64 opcode. |
| OP_vcvtm_u32_f32 | ARM vcvtm_u32_f32 opcode. |
| OP_vcvtm_u32_f64 | ARM vcvtm_u32_f64 opcode. |
| OP_vcvtn_s32_f32 | ARM vcvtn_s32_f32 opcode. |
| OP_vcvtn_s32_f64 | ARM vcvtn_s32_f64 opcode. |
| OP_vcvtn_u32_f32 | ARM vcvtn_u32_f32 opcode. |
| OP_vcvtn_u32_f64 | ARM vcvtn_u32_f64 opcode. |
| OP_vcvtp_s32_f32 | ARM vcvtp_s32_f32 opcode. |
| OP_vcvtp_s32_f64 | ARM vcvtp_s32_f64 opcode. |
| OP_vcvtp_u32_f32 | ARM vcvtp_u32_f32 opcode. |
| OP_vcvtp_u32_f64 | ARM vcvtp_u32_f64 opcode. |
| OP_vcvtr_s32_f32 | ARM vcvtr_s32_f32 opcode. |
| OP_vcvtr_s32_f64 | ARM vcvtr_s32_f64 opcode. |
| OP_vcvtr_u32_f32 | ARM vcvtr_u32_f32 opcode. |
| OP_vcvtr_u32_f64 | ARM vcvtr_u32_f64 opcode. |
| OP_vcvtt_f16_f32 | ARM vcvtt_f16_f32 opcode. |
| OP_vcvtt_f16_f64 | ARM vcvtt_f16_f64 opcode. |
| OP_vcvtt_f32_f16 | ARM vcvtt_f32_f16 opcode. |
| OP_vcvtt_f64_f16 | ARM vcvtt_f64_f16 opcode. |
| OP_vdiv_f32 | ARM vdiv_f32 opcode. |
| OP_vdiv_f64 | ARM vdiv_f64 opcode. |
| OP_vdup_16 | ARM vdup_16 opcode. |
| OP_vdup_32 | ARM vdup_32 opcode. |
| OP_vdup_8 | ARM vdup_8 opcode. |
| OP_veor | ARM veor opcode. |
| OP_vext | ARM vext opcode. |
| OP_vfma_f32 | ARM vfma_f32 opcode. |
| OP_vfma_f64 | ARM vfma_f64 opcode. |
| OP_vfms_f32 | ARM vfms_f32 opcode. |
| OP_vfms_f64 | ARM vfms_f64 opcode. |
| OP_vfnma_f32 | ARM vfnma_f32 opcode. |
| OP_vfnma_f64 | ARM vfnma_f64 opcode. |
| OP_vfnms_f32 | ARM vfnms_f32 opcode. |
| OP_vfnms_f64 | ARM vfnms_f64 opcode. |
| OP_vhadd_s16 | ARM vhadd_s16 opcode. |
| OP_vhadd_s32 | ARM vhadd_s32 opcode. |
| OP_vhadd_s8 | ARM vhadd_s8 opcode. |
| OP_vhadd_u16 | ARM vhadd_u16 opcode. |
| OP_vhadd_u32 | ARM vhadd_u32 opcode. |
| OP_vhadd_u8 | ARM vhadd_u8 opcode. |
| OP_vhsub_s16 | ARM vhsub_s16 opcode. |
| OP_vhsub_s32 | ARM vhsub_s32 opcode. |
| OP_vhsub_s8 | ARM vhsub_s8 opcode. |
| OP_vhsub_u16 | ARM vhsub_u16 opcode. |
| OP_vhsub_u32 | ARM vhsub_u32 opcode. |
| OP_vhsub_u8 | ARM vhsub_u8 opcode. |
| OP_vld1_16 | ARM vld1_16 opcode. |
| OP_vld1_32 | ARM vld1_32 opcode. |
| OP_vld1_64 | ARM vld1_64 opcode. |
| OP_vld1_8 | ARM vld1_8 opcode. |
| OP_vld1_dup_16 | ARM vld1_dup_16 opcode. |
| OP_vld1_dup_32 | ARM vld1_dup_32 opcode. |
| OP_vld1_dup_8 | ARM vld1_dup_8 opcode. |
| OP_vld1_lane_16 | ARM vld1_lane_16 opcode. |
| OP_vld1_lane_32 | ARM vld1_lane_32 opcode. |
| OP_vld1_lane_8 | ARM vld1_lane_8 opcode. |
| OP_vld2_16 | ARM vld2_16 opcode. |
| OP_vld2_32 | ARM vld2_32 opcode. |
| OP_vld2_8 | ARM vld2_8 opcode. |
| OP_vld2_dup_16 | ARM vld2_dup_16 opcode. |
| OP_vld2_dup_32 | ARM vld2_dup_32 opcode. |
| OP_vld2_dup_8 | ARM vld2_dup_8 opcode. |
| OP_vld2_lane_16 | ARM vld2_lane_16 opcode. |
| OP_vld2_lane_32 | ARM vld2_lane_32 opcode. |
| OP_vld2_lane_8 | ARM vld2_lane_8 opcode. |
| OP_vld3_16 | ARM vld3_16 opcode. |
| OP_vld3_32 | ARM vld3_32 opcode. |
| OP_vld3_8 | ARM vld3_8 opcode. |
| OP_vld3_dup_16 | ARM vld3_dup_16 opcode. |
| OP_vld3_dup_32 | ARM vld3_dup_32 opcode. |
| OP_vld3_dup_8 | ARM vld3_dup_8 opcode. |
| OP_vld3_lane_16 | ARM vld3_lane_16 opcode. |
| OP_vld3_lane_32 | ARM vld3_lane_32 opcode. |
| OP_vld3_lane_8 | ARM vld3_lane_8 opcode. |
| OP_vld4_16 | ARM vld4_16 opcode. |
| OP_vld4_32 | ARM vld4_32 opcode. |
| OP_vld4_8 | ARM vld4_8 opcode. |
| OP_vld4_dup_16 | ARM vld4_dup_16 opcode. |
| OP_vld4_dup_32 | ARM vld4_dup_32 opcode. |
| OP_vld4_dup_8 | ARM vld4_dup_8 opcode. |
| OP_vld4_lane_16 | ARM vld4_lane_16 opcode. |
| OP_vld4_lane_32 | ARM vld4_lane_32 opcode. |
| OP_vld4_lane_8 | ARM vld4_lane_8 opcode. |
| OP_vldm | ARM vldm opcode. |
| OP_vldmdb | ARM vldmdb opcode. |
| OP_vldr | ARM vldr opcode. |
| OP_vmax_f32 | ARM vmax_f32 opcode. |
| OP_vmax_s16 | ARM vmax_s16 opcode. |
| OP_vmax_s32 | ARM vmax_s32 opcode. |
| OP_vmax_s8 | ARM vmax_s8 opcode. |
| OP_vmax_u16 | ARM vmax_u16 opcode. |
| OP_vmax_u32 | ARM vmax_u32 opcode. |
| OP_vmax_u8 | ARM vmax_u8 opcode. |
| OP_vmaxnm_f32 | ARM vmaxnm_f32 opcode. |
| OP_vmaxnm_f64 | ARM vmaxnm_f64 opcode. |
| OP_vmin_f32 | ARM vmin_f32 opcode. |
| OP_vmin_s16 | ARM vmin_s16 opcode. |
| OP_vmin_s32 | ARM vmin_s32 opcode. |
| OP_vmin_s8 | ARM vmin_s8 opcode. |
| OP_vmin_u16 | ARM vmin_u16 opcode. |
| OP_vmin_u32 | ARM vmin_u32 opcode. |
| OP_vmin_u8 | ARM vmin_u8 opcode. |
| OP_vminnm_f32 | ARM vminnm_f32 opcode. |
| OP_vminnm_f64 | ARM vminnm_f64 opcode. |
| OP_vmla_f32 | ARM vmla_f32 opcode. |
| OP_vmla_f64 | ARM vmla_f64 opcode. |
| OP_vmla_i16 | ARM vmla_i16 opcode. |
| OP_vmla_i32 | ARM vmla_i32 opcode. |
| OP_vmla_i8 | ARM vmla_i8 opcode. |
| OP_vmlal_s16 | ARM vmlal_s16 opcode. |
| OP_vmlal_s32 | ARM vmlal_s32 opcode. |
| OP_vmlal_s8 | ARM vmlal_s8 opcode. |
| OP_vmlal_u16 | ARM vmlal_u16 opcode. |
| OP_vmlal_u32 | ARM vmlal_u32 opcode. |
| OP_vmlal_u8 | ARM vmlal_u8 opcode. |
| OP_vmls_f32 | ARM vmls_f32 opcode. |
| OP_vmls_f64 | ARM vmls_f64 opcode. |
| OP_vmls_i16 | ARM vmls_i16 opcode. |
| OP_vmls_i32 | ARM vmls_i32 opcode. |
| OP_vmls_i8 | ARM vmls_i8 opcode. |
| OP_vmlsl_s16 | ARM vmlsl_s16 opcode. |
| OP_vmlsl_s32 | ARM vmlsl_s32 opcode. |
| OP_vmlsl_s8 | ARM vmlsl_s8 opcode. |
| OP_vmlsl_u16 | ARM vmlsl_u16 opcode. |
| OP_vmlsl_u32 | ARM vmlsl_u32 opcode. |
| OP_vmlsl_u8 | ARM vmlsl_u8 opcode. |
| OP_vmov | ARM vmov opcode. |
| OP_vmov_16 | ARM vmov_16 opcode. |
| OP_vmov_32 | ARM vmov_32 opcode. |
| OP_vmov_8 | ARM vmov_8 opcode. |
| OP_vmov_f32 | ARM vmov_f32 opcode. |
| OP_vmov_f64 | ARM vmov_f64 opcode. |
| OP_vmov_i16 | ARM vmov_i16 opcode. |
| OP_vmov_i32 | ARM vmov_i32 opcode. |
| OP_vmov_i64 | ARM vmov_i64 opcode. |
| OP_vmov_i8 | ARM vmov_i8 opcode. |
| OP_vmov_s16 | ARM vmov_s16 opcode. |
| OP_vmov_s8 | ARM vmov_s8 opcode. |
| OP_vmov_u16 | ARM vmov_u16 opcode. |
| OP_vmov_u8 | ARM vmov_u8 opcode. |
| OP_vmovl_s16 | ARM vmovl_s16 opcode. |
| OP_vmovl_s32 | ARM vmovl_s32 opcode. |
| OP_vmovl_s8 | ARM vmovl_s8 opcode. |
| OP_vmovl_u16 | ARM vmovl_u16 opcode. |
| OP_vmovl_u32 | ARM vmovl_u32 opcode. |
| OP_vmovl_u8 | ARM vmovl_u8 opcode. |
| OP_vmovn_i16 | ARM vmovn_i16 opcode. |
| OP_vmovn_i32 | ARM vmovn_i32 opcode. |
| OP_vmovn_i64 | ARM vmovn_i64 opcode. |
| OP_vmrs | ARM vmrs opcode. |
| OP_vmsr | ARM vmsr opcode. |
| OP_vmul_f32 | ARM vmul_f32 opcode. |
| OP_vmul_f64 | ARM vmul_f64 opcode. |
| OP_vmul_i16 | ARM vmul_i16 opcode. |
| OP_vmul_i32 | ARM vmul_i32 opcode. |
| OP_vmul_i8 | ARM vmul_i8 opcode. |
| OP_vmul_p32 | ARM vmul_p32 opcode. |
| OP_vmul_p8 | ARM vmul_p8 opcode. |
| OP_vmull_p32 | ARM vmull_p32 opcode. |
| OP_vmull_p8 | ARM vmull_p8 opcode. |
| OP_vmull_s16 | ARM vmull_s16 opcode. |
| OP_vmull_s32 | ARM vmull_s32 opcode. |
| OP_vmull_s8 | ARM vmull_s8 opcode. |
| OP_vmull_u16 | ARM vmull_u16 opcode. |
| OP_vmull_u32 | ARM vmull_u32 opcode. |
| OP_vmull_u8 | ARM vmull_u8 opcode. |
| OP_vmvn | ARM vmvn opcode. |
| OP_vmvn_i16 | ARM vmvn_i16 opcode. |
| OP_vmvn_i32 | ARM vmvn_i32 opcode. |
| OP_vneg_f32 | ARM vneg_f32 opcode. |
| OP_vneg_f64 | ARM vneg_f64 opcode. |
| OP_vneg_s16 | ARM vneg_s16 opcode. |
| OP_vneg_s32 | ARM vneg_s32 opcode. |
| OP_vneg_s8 | ARM vneg_s8 opcode. |
| OP_vnmla_f32 | ARM vnmla_f32 opcode. |
| OP_vnmla_f64 | ARM vnmla_f64 opcode. |
| OP_vnmls_f32 | ARM vnmls_f32 opcode. |
| OP_vnmls_f64 | ARM vnmls_f64 opcode. |
| OP_vnmul_f32 | ARM vnmul_f32 opcode. |
| OP_vnmul_f64 | ARM vnmul_f64 opcode. |
| OP_vorn | ARM vorn opcode. |
| OP_vorr | ARM vorr opcode. |
| OP_vorr_i16 | ARM vorr_i16 opcode. |
| OP_vorr_i32 | ARM vorr_i32 opcode. |
| OP_vpadal_s16 | ARM vpadal_s16 opcode. |
| OP_vpadal_s32 | ARM vpadal_s32 opcode. |
| OP_vpadal_s8 | ARM vpadal_s8 opcode. |
| OP_vpadal_u16 | ARM vpadal_u16 opcode. |
| OP_vpadal_u32 | ARM vpadal_u32 opcode. |
| OP_vpadal_u8 | ARM vpadal_u8 opcode. |
| OP_vpadd_f32 | ARM vpadd_f32 opcode. |
| OP_vpadd_i16 | ARM vpadd_i16 opcode. |
| OP_vpadd_i32 | ARM vpadd_i32 opcode. |
| OP_vpadd_i8 | ARM vpadd_i8 opcode. |
| OP_vpaddl_s16 | ARM vpaddl_s16 opcode. |
| OP_vpaddl_s32 | ARM vpaddl_s32 opcode. |
| OP_vpaddl_s8 | ARM vpaddl_s8 opcode. |
| OP_vpaddl_u16 | ARM vpaddl_u16 opcode. |
| OP_vpaddl_u32 | ARM vpaddl_u32 opcode. |
| OP_vpaddl_u8 | ARM vpaddl_u8 opcode. |
| OP_vpmax_f32 | ARM vpmax_f32 opcode. |
| OP_vpmax_s16 | ARM vpmax_s16 opcode. |
| OP_vpmax_s32 | ARM vpmax_s32 opcode. |
| OP_vpmax_s8 | ARM vpmax_s8 opcode. |
| OP_vpmax_u16 | ARM vpmax_u16 opcode. |
| OP_vpmax_u32 | ARM vpmax_u32 opcode. |
| OP_vpmax_u8 | ARM vpmax_u8 opcode. |
| OP_vpmin_f32 | ARM vpmin_f32 opcode. |
| OP_vpmin_s16 | ARM vpmin_s16 opcode. |
| OP_vpmin_s32 | ARM vpmin_s32 opcode. |
| OP_vpmin_s8 | ARM vpmin_s8 opcode. |
| OP_vpmin_u16 | ARM vpmin_u16 opcode. |
| OP_vpmin_u32 | ARM vpmin_u32 opcode. |
| OP_vpmin_u8 | ARM vpmin_u8 opcode. |
| OP_vqabs_s16 | ARM vqabs_s16 opcode. |
| OP_vqabs_s32 | ARM vqabs_s32 opcode. |
| OP_vqabs_s8 | ARM vqabs_s8 opcode. |
| OP_vqadd_s16 | ARM vqadd_s16 opcode. |
| OP_vqadd_s32 | ARM vqadd_s32 opcode. |
| OP_vqadd_s64 | ARM vqadd_s64 opcode. |
| OP_vqadd_s8 | ARM vqadd_s8 opcode. |
| OP_vqadd_u16 | ARM vqadd_u16 opcode. |
| OP_vqadd_u32 | ARM vqadd_u32 opcode. |
| OP_vqadd_u64 | ARM vqadd_u64 opcode. |
| OP_vqadd_u8 | ARM vqadd_u8 opcode. |
| OP_vqdmlal_s16 | ARM vqdmlal_s16 opcode. |
| OP_vqdmlal_s32 | ARM vqdmlal_s32 opcode. |
| OP_vqdmlsl_s16 | ARM vqdmlsl_s16 opcode. |
| OP_vqdmlsl_s32 | ARM vqdmlsl_s32 opcode. |
| OP_vqdmulh_s16 | ARM vqdmulh_s16 opcode. |
| OP_vqdmulh_s32 | ARM vqdmulh_s32 opcode. |
| OP_vqdmull_s16 | ARM vqdmull_s16 opcode. |
| OP_vqdmull_s32 | ARM vqdmull_s32 opcode. |
| OP_vqmovn_s16 | ARM vqmovn_s16 opcode. |
| OP_vqmovn_s32 | ARM vqmovn_s32 opcode. |
| OP_vqmovn_s64 | ARM vqmovn_s64 opcode. |
| OP_vqmovn_u16 | ARM vqmovn_u16 opcode. |
| OP_vqmovn_u32 | ARM vqmovn_u32 opcode. |
| OP_vqmovn_u64 | ARM vqmovn_u64 opcode. |
| OP_vqmovun_s16 | ARM vqmovun_s16 opcode. |
| OP_vqmovun_s32 | ARM vqmovun_s32 opcode. |
| OP_vqmovun_s64 | ARM vqmovun_s64 opcode. |
| OP_vqneg_s16 | ARM vqneg_s16 opcode. |
| OP_vqneg_s32 | ARM vqneg_s32 opcode. |
| OP_vqneg_s8 | ARM vqneg_s8 opcode. |
| OP_vqrdmulh_s16 | ARM vqrdmulh_s16 opcode. |
| OP_vqrdmulh_s32 | ARM vqrdmulh_s32 opcode. |
| OP_vqrshl_s16 | ARM vqrshl_s16 opcode. |
| OP_vqrshl_s32 | ARM vqrshl_s32 opcode. |
| OP_vqrshl_s64 | ARM vqrshl_s64 opcode. |
| OP_vqrshl_s8 | ARM vqrshl_s8 opcode. |
| OP_vqrshl_u16 | ARM vqrshl_u16 opcode. |
| OP_vqrshl_u32 | ARM vqrshl_u32 opcode. |
| OP_vqrshl_u64 | ARM vqrshl_u64 opcode. |
| OP_vqrshl_u8 | ARM vqrshl_u8 opcode. |
| OP_vqrshrn_s16 | ARM vqrshrn_s16 opcode. |
| OP_vqrshrn_s32 | ARM vqrshrn_s32 opcode. |
| OP_vqrshrn_s64 | ARM vqrshrn_s64 opcode. |
| OP_vqrshrn_u16 | ARM vqrshrn_u16 opcode. |
| OP_vqrshrn_u32 | ARM vqrshrn_u32 opcode. |
| OP_vqrshrn_u64 | ARM vqrshrn_u64 opcode. |
| OP_vqrshrun_s16 | ARM vqrshrun_s16 opcode. |
| OP_vqrshrun_s32 | ARM vqrshrun_s32 opcode. |
| OP_vqrshrun_s64 | ARM vqrshrun_s64 opcode. |
| OP_vqshl_s16 | ARM vqshl_s16 opcode. |
| OP_vqshl_s32 | ARM vqshl_s32 opcode. |
| OP_vqshl_s64 | ARM vqshl_s64 opcode. |
| OP_vqshl_s8 | ARM vqshl_s8 opcode. |
| OP_vqshl_u16 | ARM vqshl_u16 opcode. |
| OP_vqshl_u32 | ARM vqshl_u32 opcode. |
| OP_vqshl_u64 | ARM vqshl_u64 opcode. |
| OP_vqshl_u8 | ARM vqshl_u8 opcode. |
| OP_vqshlu_s16 | ARM vqshlu_s16 opcode. |
| OP_vqshlu_s32 | ARM vqshlu_s32 opcode. |
| OP_vqshlu_s64 | ARM vqshlu_s64 opcode. |
| OP_vqshlu_s8 | ARM vqshlu_s8 opcode. |
| OP_vqshrn_s16 | ARM vqshrn_s16 opcode. |
| OP_vqshrn_s32 | ARM vqshrn_s32 opcode. |
| OP_vqshrn_s64 | ARM vqshrn_s64 opcode. |
| OP_vqshrn_u16 | ARM vqshrn_u16 opcode. |
| OP_vqshrn_u32 | ARM vqshrn_u32 opcode. |
| OP_vqshrn_u64 | ARM vqshrn_u64 opcode. |
| OP_vqshrun_s16 | ARM vqshrun_s16 opcode. |
| OP_vqshrun_s32 | ARM vqshrun_s32 opcode. |
| OP_vqshrun_s64 | ARM vqshrun_s64 opcode. |
| OP_vqsub_s16 | ARM vqsub_s16 opcode. |
| OP_vqsub_s32 | ARM vqsub_s32 opcode. |
| OP_vqsub_s64 | ARM vqsub_s64 opcode. |
| OP_vqsub_s8 | ARM vqsub_s8 opcode. |
| OP_vqsub_u16 | ARM vqsub_u16 opcode. |
| OP_vqsub_u32 | ARM vqsub_u32 opcode. |
| OP_vqsub_u64 | ARM vqsub_u64 opcode. |
| OP_vqsub_u8 | ARM vqsub_u8 opcode. |
| OP_vraddhn_i16 | ARM vraddhn_i16 opcode. |
| OP_vraddhn_i32 | ARM vraddhn_i32 opcode. |
| OP_vraddhn_i64 | ARM vraddhn_i64 opcode. |
| OP_vrecpe_f32 | ARM vrecpe_f32 opcode. |
| OP_vrecpe_u32 | ARM vrecpe_u32 opcode. |
| OP_vrecps_f32 | ARM vrecps_f32 opcode. |
| OP_vrev16_16 | ARM vrev16_16 opcode. |
| OP_vrev16_8 | ARM vrev16_8 opcode. |
| OP_vrev32_16 | ARM vrev32_16 opcode. |
| OP_vrev32_32 | ARM vrev32_32 opcode. |
| OP_vrev32_8 | ARM vrev32_8 opcode. |
| OP_vrev64_16 | ARM vrev64_16 opcode. |
| OP_vrev64_32 | ARM vrev64_32 opcode. |
| OP_vrev64_8 | ARM vrev64_8 opcode. |
| OP_vrhadd_s16 | ARM vrhadd_s16 opcode. |
| OP_vrhadd_s32 | ARM vrhadd_s32 opcode. |
| OP_vrhadd_s8 | ARM vrhadd_s8 opcode. |
| OP_vrhadd_u16 | ARM vrhadd_u16 opcode. |
| OP_vrhadd_u32 | ARM vrhadd_u32 opcode. |
| OP_vrhadd_u8 | ARM vrhadd_u8 opcode. |
| OP_vrinta_f32_f32 | ARM vrinta_f32_f32 opcode. |
| OP_vrinta_f64_f64 | ARM vrinta_f64_f64 opcode. |
| OP_vrintm_f32_f32 | ARM vrintm_f32_f32 opcode. |
| OP_vrintm_f64_f64 | ARM vrintm_f64_f64 opcode. |
| OP_vrintn_f32_f32 | ARM vrintn_f32_f32 opcode. |
| OP_vrintn_f64_f64 | ARM vrintn_f64_f64 opcode. |
| OP_vrintp_f32_f32 | ARM vrintp_f32_f32 opcode. |
| OP_vrintp_f64_f64 | ARM vrintp_f64_f64 opcode. |
| OP_vrintr_f32 | ARM vrintr_f32 opcode. |
| OP_vrintr_f64 | ARM vrintr_f64 opcode. |
| OP_vrintx_f32 | ARM vrintx_f32 opcode. |
| OP_vrintx_f32_f32 | ARM vrintx_f32_f32 opcode. |
| OP_vrintx_f64 | ARM vrintx_f64 opcode. |
| OP_vrintz_f32 | ARM vrintz_f32 opcode. |
| OP_vrintz_f32_f32 | ARM vrintz_f32_f32 opcode. |
| OP_vrintz_f64 | ARM vrintz_f64 opcode. |
| OP_vrshl_s16 | ARM vrshl_s16 opcode. |
| OP_vrshl_s32 | ARM vrshl_s32 opcode. |
| OP_vrshl_s64 | ARM vrshl_s64 opcode. |
| OP_vrshl_s8 | ARM vrshl_s8 opcode. |
| OP_vrshl_u16 | ARM vrshl_u16 opcode. |
| OP_vrshl_u32 | ARM vrshl_u32 opcode. |
| OP_vrshl_u64 | ARM vrshl_u64 opcode. |
| OP_vrshl_u8 | ARM vrshl_u8 opcode. |
| OP_vrshr_s16 | ARM vrshr_s16 opcode. |
| OP_vrshr_s32 | ARM vrshr_s32 opcode. |
| OP_vrshr_s64 | ARM vrshr_s64 opcode. |
| OP_vrshr_s8 | ARM vrshr_s8 opcode. |
| OP_vrshr_u16 | ARM vrshr_u16 opcode. |
| OP_vrshr_u32 | ARM vrshr_u32 opcode. |
| OP_vrshr_u64 | ARM vrshr_u64 opcode. |
| OP_vrshr_u8 | ARM vrshr_u8 opcode. |
| OP_vrshrn_i16 | ARM vrshrn_i16 opcode. |
| OP_vrshrn_i32 | ARM vrshrn_i32 opcode. |
| OP_vrshrn_i64 | ARM vrshrn_i64 opcode. |
| OP_vrsqrte_f32 | ARM vrsqrte_f32 opcode. |
| OP_vrsqrte_u32 | ARM vrsqrte_u32 opcode. |
| OP_vrsqrts_f32 | ARM vrsqrts_f32 opcode. |
| OP_vrsra_s16 | ARM vrsra_s16 opcode. |
| OP_vrsra_s32 | ARM vrsra_s32 opcode. |
| OP_vrsra_s64 | ARM vrsra_s64 opcode. |
| OP_vrsra_s8 | ARM vrsra_s8 opcode. |
| OP_vrsra_u16 | ARM vrsra_u16 opcode. |
| OP_vrsra_u32 | ARM vrsra_u32 opcode. |
| OP_vrsra_u64 | ARM vrsra_u64 opcode. |
| OP_vrsra_u8 | ARM vrsra_u8 opcode. |
| OP_vrsubhn_i16 | ARM vrsubhn_i16 opcode. |
| OP_vrsubhn_i32 | ARM vrsubhn_i32 opcode. |
| OP_vrsubhn_i64 | ARM vrsubhn_i64 opcode. |
| OP_vsel_eq_f32 | ARM vsel_eq_f32 opcode. |
| OP_vsel_eq_f64 | ARM vsel_eq_f64 opcode. |
| OP_vsel_ge_f32 | ARM vsel_ge_f32 opcode. |
| OP_vsel_ge_f64 | ARM vsel_ge_f64 opcode. |
| OP_vsel_gt_f32 | ARM vsel_gt_f32 opcode. |
| OP_vsel_gt_f64 | ARM vsel_gt_f64 opcode. |
| OP_vsel_vs_f32 | ARM vsel_vs_f32 opcode. |
| OP_vsel_vs_f64 | ARM vsel_vs_f64 opcode. |
| OP_vshl_i16 | ARM vshl_i16 opcode. |
| OP_vshl_i32 | ARM vshl_i32 opcode. |
| OP_vshl_i64 | ARM vshl_i64 opcode. |
| OP_vshl_i8 | ARM vshl_i8 opcode. |
| OP_vshl_s16 | ARM vshl_s16 opcode. |
| OP_vshl_s32 | ARM vshl_s32 opcode. |
| OP_vshl_s64 | ARM vshl_s64 opcode. |
| OP_vshl_s8 | ARM vshl_s8 opcode. |
| OP_vshl_u16 | ARM vshl_u16 opcode. |
| OP_vshl_u32 | ARM vshl_u32 opcode. |
| OP_vshl_u64 | ARM vshl_u64 opcode. |
| OP_vshl_u8 | ARM vshl_u8 opcode. |
| OP_vshll_i16 | ARM vshll_i16 opcode. |
| OP_vshll_i32 | ARM vshll_i32 opcode. |
| OP_vshll_i8 | ARM vshll_i8 opcode. |
| OP_vshll_s16 | ARM vshll_s16 opcode. |
| OP_vshll_s32 | ARM vshll_s32 opcode. |
| OP_vshll_s8 | ARM vshll_s8 opcode. |
| OP_vshll_u16 | ARM vshll_u16 opcode. |
| OP_vshll_u32 | ARM vshll_u32 opcode. |
| OP_vshll_u8 | ARM vshll_u8 opcode. |
| OP_vshr_s16 | ARM vshr_s16 opcode. |
| OP_vshr_s32 | ARM vshr_s32 opcode. |
| OP_vshr_s64 | ARM vshr_s64 opcode. |
| OP_vshr_s8 | ARM vshr_s8 opcode. |
| OP_vshr_u16 | ARM vshr_u16 opcode. |
| OP_vshr_u32 | ARM vshr_u32 opcode. |
| OP_vshr_u64 | ARM vshr_u64 opcode. |
| OP_vshr_u8 | ARM vshr_u8 opcode. |
| OP_vshrn_i16 | ARM vshrn_i16 opcode. |
| OP_vshrn_i32 | ARM vshrn_i32 opcode. |
| OP_vshrn_i64 | ARM vshrn_i64 opcode. |
| OP_vsli_16 | ARM vsli_16 opcode. |
| OP_vsli_32 | ARM vsli_32 opcode. |
| OP_vsli_64 | ARM vsli_64 opcode. |
| OP_vsli_8 | ARM vsli_8 opcode. |
| OP_vsqrt_f32 | ARM vsqrt_f32 opcode. |
| OP_vsqrt_f64 | ARM vsqrt_f64 opcode. |
| OP_vsra_s16 | ARM vsra_s16 opcode. |
| OP_vsra_s32 | ARM vsra_s32 opcode. |
| OP_vsra_s64 | ARM vsra_s64 opcode. |
| OP_vsra_s8 | ARM vsra_s8 opcode. |
| OP_vsra_u16 | ARM vsra_u16 opcode. |
| OP_vsra_u32 | ARM vsra_u32 opcode. |
| OP_vsra_u64 | ARM vsra_u64 opcode. |
| OP_vsra_u8 | ARM vsra_u8 opcode. |
| OP_vsri_16 | ARM vsri_16 opcode. |
| OP_vsri_32 | ARM vsri_32 opcode. |
| OP_vsri_64 | ARM vsri_64 opcode. |
| OP_vsri_8 | ARM vsri_8 opcode. |
| OP_vst1_16 | ARM vst1_16 opcode. |
| OP_vst1_32 | ARM vst1_32 opcode. |
| OP_vst1_64 | ARM vst1_64 opcode. |
| OP_vst1_8 | ARM vst1_8 opcode. |
| OP_vst1_lane_16 | ARM vst1_lane_16 opcode. |
| OP_vst1_lane_32 | ARM vst1_lane_32 opcode. |
| OP_vst1_lane_8 | ARM vst1_lane_8 opcode. |
| OP_vst2_16 | ARM vst2_16 opcode. |
| OP_vst2_32 | ARM vst2_32 opcode. |
| OP_vst2_8 | ARM vst2_8 opcode. |
| OP_vst2_lane_16 | ARM vst2_lane_16 opcode. |
| OP_vst2_lane_32 | ARM vst2_lane_32 opcode. |
| OP_vst2_lane_8 | ARM vst2_lane_8 opcode. |
| OP_vst3_16 | ARM vst3_16 opcode. |
| OP_vst3_32 | ARM vst3_32 opcode. |
| OP_vst3_8 | ARM vst3_8 opcode. |
| OP_vst3_lane_16 | ARM vst3_lane_16 opcode. |
| OP_vst3_lane_32 | ARM vst3_lane_32 opcode. |
| OP_vst3_lane_8 | ARM vst3_lane_8 opcode. |
| OP_vst4_16 | ARM vst4_16 opcode. |
| OP_vst4_32 | ARM vst4_32 opcode. |
| OP_vst4_8 | ARM vst4_8 opcode. |
| OP_vst4_lane_16 | ARM vst4_lane_16 opcode. |
| OP_vst4_lane_32 | ARM vst4_lane_32 opcode. |
| OP_vst4_lane_8 | ARM vst4_lane_8 opcode. |
| OP_vstm | ARM vstm opcode. |
| OP_vstmdb | ARM vstmdb opcode. |
| OP_vstr | ARM vstr opcode. |
| OP_vsub_f32 | ARM vsub_f32 opcode. |
| OP_vsub_f64 | ARM vsub_f64 opcode. |
| OP_vsub_i16 | ARM vsub_i16 opcode. |
| OP_vsub_i32 | ARM vsub_i32 opcode. |
| OP_vsub_i64 | ARM vsub_i64 opcode. |
| OP_vsub_i8 | ARM vsub_i8 opcode. |
| OP_vsubhn_i16 | ARM vsubhn_i16 opcode. |
| OP_vsubhn_i32 | ARM vsubhn_i32 opcode. |
| OP_vsubhn_i64 | ARM vsubhn_i64 opcode. |
| OP_vsubl_s16 | ARM vsubl_s16 opcode. |
| OP_vsubl_s32 | ARM vsubl_s32 opcode. |
| OP_vsubl_s8 | ARM vsubl_s8 opcode. |
| OP_vsubl_u16 | ARM vsubl_u16 opcode. |
| OP_vsubl_u32 | ARM vsubl_u32 opcode. |
| OP_vsubl_u8 | ARM vsubl_u8 opcode. |
| OP_vsubw_s16 | ARM vsubw_s16 opcode. |
| OP_vsubw_s32 | ARM vsubw_s32 opcode. |
| OP_vsubw_s8 | ARM vsubw_s8 opcode. |
| OP_vsubw_u16 | ARM vsubw_u16 opcode. |
| OP_vsubw_u32 | ARM vsubw_u32 opcode. |
| OP_vsubw_u8 | ARM vsubw_u8 opcode. |
| OP_vswp | ARM vswp opcode. |
| OP_vtbl_8 | ARM vtbl_8 opcode. |
| OP_vtbx_8 | ARM vtbx_8 opcode. |
| OP_vtrn_16 | ARM vtrn_16 opcode. |
| OP_vtrn_32 | ARM vtrn_32 opcode. |
| OP_vtrn_8 | ARM vtrn_8 opcode. |
| OP_vtst_16 | ARM vtst_16 opcode. |
| OP_vtst_32 | ARM vtst_32 opcode. |
| OP_vtst_8 | ARM vtst_8 opcode. |
| OP_vuzp_16 | ARM vuzp_16 opcode. |
| OP_vuzp_32 | ARM vuzp_32 opcode. |
| OP_vuzp_8 | ARM vuzp_8 opcode. |
| OP_vzip_16 | ARM vzip_16 opcode. |
| OP_vzip_32 | ARM vzip_32 opcode. |
| OP_vzip_8 | ARM vzip_8 opcode. |
| OP_wfe | ARM wfe opcode. |
| OP_wfi | ARM wfi opcode. |
| OP_yield | ARM yield opcode. |
| OP_FIRST | First real opcode. |
| OP_LAST | Last real opcode. |
| OP_UNDECODED | INVALID opcode |
| OP_CONTD | UNDECODED opcode |
| OP_LABEL | CONTD opcode |
| OP_add | LABEL opcode IA-32/AMD64 add opcode. |
| OP_or | IA-32/AMD64 or opcode. |
| OP_adc | IA-32/AMD64 adc opcode. |
| OP_sbb | IA-32/AMD64 sbb opcode. |
| OP_and | IA-32/AMD64 and opcode. |
| OP_daa | IA-32/AMD64 daa opcode. |
| OP_sub | IA-32/AMD64 sub opcode. |
| OP_das | IA-32/AMD64 das opcode. |
| OP_xor | IA-32/AMD64 xor opcode. |
| OP_aaa | IA-32/AMD64 aaa opcode. |
| OP_cmp | IA-32/AMD64 cmp opcode. |
| OP_aas | IA-32/AMD64 aas opcode. |
| OP_inc | IA-32/AMD64 inc opcode. |
| OP_dec | IA-32/AMD64 dec opcode. |
| OP_push | IA-32/AMD64 push opcode. |
| OP_push_imm | IA-32/AMD64 push_imm opcode. |
| OP_pop | IA-32/AMD64 pop opcode. |
| OP_pusha | IA-32/AMD64 pusha opcode. |
| OP_popa | IA-32/AMD64 popa opcode. |
| OP_bound | IA-32/AMD64 bound opcode. |
| OP_arpl | IA-32/AMD64 arpl opcode. |
| OP_imul | IA-32/AMD64 imul opcode. |
| OP_jo_short | IA-32/AMD64 jo_short opcode. |
| OP_jno_short | IA-32/AMD64 jno_short opcode. |
| OP_jb_short | IA-32/AMD64 jb_short opcode. |
| OP_jnb_short | IA-32/AMD64 jnb_short opcode. |
| OP_jz_short | IA-32/AMD64 jz_short opcode. |
| OP_jnz_short | IA-32/AMD64 jnz_short opcode. |
| OP_jbe_short | IA-32/AMD64 jbe_short opcode. |
| OP_jnbe_short | IA-32/AMD64 jnbe_short opcode. |
| OP_js_short | IA-32/AMD64 js_short opcode. |
| OP_jns_short | IA-32/AMD64 jns_short opcode. |
| OP_jp_short | IA-32/AMD64 jp_short opcode. |
| OP_jnp_short | IA-32/AMD64 jnp_short opcode. |
| OP_jl_short | IA-32/AMD64 jl_short opcode. |
| OP_jnl_short | IA-32/AMD64 jnl_short opcode. |
| OP_jle_short | IA-32/AMD64 jle_short opcode. |
| OP_jnle_short | IA-32/AMD64 jnle_short opcode. |
| OP_call | IA-32/AMD64 call opcode. |
| OP_call_ind | IA-32/AMD64 call_ind opcode. |
| OP_call_far | IA-32/AMD64 call_far opcode. |
| OP_call_far_ind | IA-32/AMD64 call_far_ind opcode. |
| OP_jmp | IA-32/AMD64 jmp opcode. |
| OP_jmp_short | IA-32/AMD64 jmp_short opcode. |
| OP_jmp_ind | IA-32/AMD64 jmp_ind opcode. |
| OP_jmp_far | IA-32/AMD64 jmp_far opcode. |
| OP_jmp_far_ind | IA-32/AMD64 jmp_far_ind opcode. |
| OP_loopne | IA-32/AMD64 loopne opcode. |
| OP_loope | IA-32/AMD64 loope opcode. |
| OP_loop | IA-32/AMD64 loop opcode. |
| OP_jecxz | IA-32/AMD64 jecxz opcode. |
| OP_mov_ld | IA-32/AMD64 mov_ld opcode. |
| OP_mov_st | IA-32/AMD64 mov_st opcode. |
| OP_mov_imm | IA-32/AMD64 mov_imm opcode. |
| OP_mov_seg | IA-32/AMD64 mov_seg opcode. |
| OP_mov_priv | IA-32/AMD64 mov_priv opcode. |
| OP_test | IA-32/AMD64 test opcode. |
| OP_lea | IA-32/AMD64 lea opcode. |
| OP_xchg | IA-32/AMD64 xchg opcode. |
| OP_cwde | IA-32/AMD64 cwde opcode. |
| OP_cdq | IA-32/AMD64 cdq opcode. |
| OP_fwait | IA-32/AMD64 fwait opcode. |
| OP_pushf | IA-32/AMD64 pushf opcode. |
| OP_popf | IA-32/AMD64 popf opcode. |
| OP_sahf | IA-32/AMD64 sahf opcode. |
| OP_lahf | IA-32/AMD64 lahf opcode. |
| OP_ret | IA-32/AMD64 ret opcode. |
| OP_ret_far | IA-32/AMD64 ret_far opcode. |
| OP_les | IA-32/AMD64 les opcode. |
| OP_lds | IA-32/AMD64 lds opcode. |
| OP_enter | IA-32/AMD64 enter opcode. |
| OP_leave | IA-32/AMD64 leave opcode. |
| OP_int3 | IA-32/AMD64 int3 opcode. |
| OP_int | IA-32/AMD64 int opcode. |
| OP_into | IA-32/AMD64 into opcode. |
| OP_iret | IA-32/AMD64 iret opcode. |
| OP_aam | IA-32/AMD64 aam opcode. |
| OP_aad | IA-32/AMD64 aad opcode. |
| OP_xlat | IA-32/AMD64 xlat opcode. |
| OP_in | IA-32/AMD64 in opcode. |
| OP_out | IA-32/AMD64 out opcode. |
| OP_hlt | IA-32/AMD64 hlt opcode. |
| OP_cmc | IA-32/AMD64 cmc opcode. |
| OP_clc | IA-32/AMD64 clc opcode. |
| OP_stc | IA-32/AMD64 stc opcode. |
| OP_cli | IA-32/AMD64 cli opcode. |
| OP_sti | IA-32/AMD64 sti opcode. |
| OP_cld | IA-32/AMD64 cld opcode. |
| OP_std | IA-32/AMD64 std opcode. |
| OP_lar | IA-32/AMD64 lar opcode. |
| OP_lsl | IA-32/AMD64 lsl opcode. |
| OP_syscall | IA-32/AMD64 syscall opcode. |
| OP_clts | IA-32/AMD64 clts opcode. |
| OP_sysret | IA-32/AMD64 sysret opcode. |
| OP_invd | IA-32/AMD64 invd opcode. |
| OP_wbinvd | IA-32/AMD64 wbinvd opcode. |
| OP_ud2a | IA-32/AMD64 ud2a opcode. |
| OP_nop_modrm | IA-32/AMD64 nop_modrm opcode. |
| OP_movntps | IA-32/AMD64 movntps opcode. |
| OP_movntpd | IA-32/AMD64 movntpd opcode. |
| OP_wrmsr | IA-32/AMD64 wrmsr opcode. |
| OP_rdtsc | IA-32/AMD64 rdtsc opcode. |
| OP_rdmsr | IA-32/AMD64 rdmsr opcode. |
| OP_rdpmc | IA-32/AMD64 rdpmc opcode. |
| OP_sysenter | IA-32/AMD64 sysenter opcode. |
| OP_sysexit | IA-32/AMD64 sysexit opcode. |
| OP_cmovo | IA-32/AMD64 cmovo opcode. |
| OP_cmovno | IA-32/AMD64 cmovno opcode. |
| OP_cmovb | IA-32/AMD64 cmovb opcode. |
| OP_cmovnb | IA-32/AMD64 cmovnb opcode. |
| OP_cmovz | IA-32/AMD64 cmovz opcode. |
| OP_cmovnz | IA-32/AMD64 cmovnz opcode. |
| OP_cmovbe | IA-32/AMD64 cmovbe opcode. |
| OP_cmovnbe | IA-32/AMD64 cmovnbe opcode. |
| OP_cmovs | IA-32/AMD64 cmovs opcode. |
| OP_cmovns | IA-32/AMD64 cmovns opcode. |
| OP_cmovp | IA-32/AMD64 cmovp opcode. |
| OP_cmovnp | IA-32/AMD64 cmovnp opcode. |
| OP_cmovl | IA-32/AMD64 cmovl opcode. |
| OP_cmovnl | IA-32/AMD64 cmovnl opcode. |
| OP_cmovle | IA-32/AMD64 cmovle opcode. |
| OP_cmovnle | IA-32/AMD64 cmovnle opcode. |
| OP_punpcklbw | IA-32/AMD64 punpcklbw opcode. |
| OP_punpcklwd | IA-32/AMD64 punpcklwd opcode. |
| OP_punpckldq | IA-32/AMD64 punpckldq opcode. |
| OP_packsswb | IA-32/AMD64 packsswb opcode. |
| OP_pcmpgtb | IA-32/AMD64 pcmpgtb opcode. |
| OP_pcmpgtw | IA-32/AMD64 pcmpgtw opcode. |
| OP_pcmpgtd | IA-32/AMD64 pcmpgtd opcode. |
| OP_packuswb | IA-32/AMD64 packuswb opcode. |
| OP_punpckhbw | IA-32/AMD64 punpckhbw opcode. |
| OP_punpckhwd | IA-32/AMD64 punpckhwd opcode. |
| OP_punpckhdq | IA-32/AMD64 punpckhdq opcode. |
| OP_packssdw | IA-32/AMD64 packssdw opcode. |
| OP_punpcklqdq | IA-32/AMD64 punpcklqdq opcode. |
| OP_punpckhqdq | IA-32/AMD64 punpckhqdq opcode. |
| OP_movd | IA-32/AMD64 movd opcode. |
| OP_movq | IA-32/AMD64 movq opcode. |
| OP_movdqu | IA-32/AMD64 movdqu opcode. |
| OP_movdqa | IA-32/AMD64 movdqa opcode. |
| OP_pshufw | IA-32/AMD64 pshufw opcode. |
| OP_pshufd | IA-32/AMD64 pshufd opcode. |
| OP_pshufhw | IA-32/AMD64 pshufhw opcode. |
| OP_pshuflw | IA-32/AMD64 pshuflw opcode. |
| OP_pcmpeqb | IA-32/AMD64 pcmpeqb opcode. |
| OP_pcmpeqw | IA-32/AMD64 pcmpeqw opcode. |
| OP_pcmpeqd | IA-32/AMD64 pcmpeqd opcode. |
| OP_emms | IA-32/AMD64 emms opcode. |
| OP_jo | IA-32/AMD64 jo opcode. |
| OP_jno | IA-32/AMD64 jno opcode. |
| OP_jb | IA-32/AMD64 jb opcode. |
| OP_jnb | IA-32/AMD64 jnb opcode. |
| OP_jz | IA-32/AMD64 jz opcode. |
| OP_jnz | IA-32/AMD64 jnz opcode. |
| OP_jbe | IA-32/AMD64 jbe opcode. |
| OP_jnbe | IA-32/AMD64 jnbe opcode. |
| OP_js | IA-32/AMD64 js opcode. |
| OP_jns | IA-32/AMD64 jns opcode. |
| OP_jp | IA-32/AMD64 jp opcode. |
| OP_jnp | IA-32/AMD64 jnp opcode. |
| OP_jl | IA-32/AMD64 jl opcode. |
| OP_jnl | IA-32/AMD64 jnl opcode. |
| OP_jle | IA-32/AMD64 jle opcode. |
| OP_jnle | IA-32/AMD64 jnle opcode. |
| OP_seto | IA-32/AMD64 seto opcode. |
| OP_setno | IA-32/AMD64 setno opcode. |
| OP_setb | IA-32/AMD64 setb opcode. |
| OP_setnb | IA-32/AMD64 setnb opcode. |
| OP_setz | IA-32/AMD64 setz opcode. |
| OP_setnz | IA-32/AMD64 setnz opcode. |
| OP_setbe | IA-32/AMD64 setbe opcode. |
| OP_setnbe | IA-32/AMD64 setnbe opcode. |
| OP_sets | IA-32/AMD64 sets opcode. |
| OP_setns | IA-32/AMD64 setns opcode. |
| OP_setp | IA-32/AMD64 setp opcode. |
| OP_setnp | IA-32/AMD64 setnp opcode. |
| OP_setl | IA-32/AMD64 setl opcode. |
| OP_setnl | IA-32/AMD64 setnl opcode. |
| OP_setle | IA-32/AMD64 setle opcode. |
| OP_setnle | IA-32/AMD64 setnle opcode. |
| OP_cpuid | IA-32/AMD64 cpuid opcode. |
| OP_bt | IA-32/AMD64 bt opcode. |
| OP_shld | IA-32/AMD64 shld opcode. |
| OP_rsm | IA-32/AMD64 rsm opcode. |
| OP_bts | IA-32/AMD64 bts opcode. |
| OP_shrd | IA-32/AMD64 shrd opcode. |
| OP_cmpxchg | IA-32/AMD64 cmpxchg opcode. |
| OP_lss | IA-32/AMD64 lss opcode. |
| OP_btr | IA-32/AMD64 btr opcode. |
| OP_lfs | IA-32/AMD64 lfs opcode. |
| OP_lgs | IA-32/AMD64 lgs opcode. |
| OP_movzx | IA-32/AMD64 movzx opcode. |
| OP_ud2b | IA-32/AMD64 ud2b opcode. |
| OP_btc | IA-32/AMD64 btc opcode. |
| OP_bsf | IA-32/AMD64 bsf opcode. |
| OP_bsr | IA-32/AMD64 bsr opcode. |
| OP_movsx | IA-32/AMD64 movsx opcode. |
| OP_xadd | IA-32/AMD64 xadd opcode. |
| OP_movnti | IA-32/AMD64 movnti opcode. |
| OP_pinsrw | IA-32/AMD64 pinsrw opcode. |
| OP_pextrw | IA-32/AMD64 pextrw opcode. |
| OP_bswap | IA-32/AMD64 bswap opcode. |
| OP_psrlw | IA-32/AMD64 psrlw opcode. |
| OP_psrld | IA-32/AMD64 psrld opcode. |
| OP_psrlq | IA-32/AMD64 psrlq opcode. |
| OP_paddq | IA-32/AMD64 paddq opcode. |
| OP_pmullw | IA-32/AMD64 pmullw opcode. |
| OP_pmovmskb | IA-32/AMD64 pmovmskb opcode. |
| OP_psubusb | IA-32/AMD64 psubusb opcode. |
| OP_psubusw | IA-32/AMD64 psubusw opcode. |
| OP_pminub | IA-32/AMD64 pminub opcode. |
| OP_pand | IA-32/AMD64 pand opcode. |
| OP_paddusb | IA-32/AMD64 paddusb opcode. |
| OP_paddusw | IA-32/AMD64 paddusw opcode. |
| OP_pmaxub | IA-32/AMD64 pmaxub opcode. |
| OP_pandn | IA-32/AMD64 pandn opcode. |
| OP_pavgb | IA-32/AMD64 pavgb opcode. |
| OP_psraw | IA-32/AMD64 psraw opcode. |
| OP_psrad | IA-32/AMD64 psrad opcode. |
| OP_pavgw | IA-32/AMD64 pavgw opcode. |
| OP_pmulhuw | IA-32/AMD64 pmulhuw opcode. |
| OP_pmulhw | IA-32/AMD64 pmulhw opcode. |
| OP_movntq | IA-32/AMD64 movntq opcode. |
| OP_movntdq | IA-32/AMD64 movntdq opcode. |
| OP_psubsb | IA-32/AMD64 psubsb opcode. |
| OP_psubsw | IA-32/AMD64 psubsw opcode. |
| OP_pminsw | IA-32/AMD64 pminsw opcode. |
| OP_por | IA-32/AMD64 por opcode. |
| OP_paddsb | IA-32/AMD64 paddsb opcode. |
| OP_paddsw | IA-32/AMD64 paddsw opcode. |
| OP_pmaxsw | IA-32/AMD64 pmaxsw opcode. |
| OP_pxor | IA-32/AMD64 pxor opcode. |
| OP_psllw | IA-32/AMD64 psllw opcode. |
| OP_pslld | IA-32/AMD64 pslld opcode. |
| OP_psllq | IA-32/AMD64 psllq opcode. |
| OP_pmuludq | IA-32/AMD64 pmuludq opcode. |
| OP_pmaddwd | IA-32/AMD64 pmaddwd opcode. |
| OP_psadbw | IA-32/AMD64 psadbw opcode. |
| OP_maskmovq | IA-32/AMD64 maskmovq opcode. |
| OP_maskmovdqu | IA-32/AMD64 maskmovdqu opcode. |
| OP_psubb | IA-32/AMD64 psubb opcode. |
| OP_psubw | IA-32/AMD64 psubw opcode. |
| OP_psubd | IA-32/AMD64 psubd opcode. |
| OP_psubq | IA-32/AMD64 psubq opcode. |
| OP_paddb | IA-32/AMD64 paddb opcode. |
| OP_paddw | IA-32/AMD64 paddw opcode. |
| OP_paddd | IA-32/AMD64 paddd opcode. |
| OP_psrldq | IA-32/AMD64 psrldq opcode. |
| OP_pslldq | IA-32/AMD64 pslldq opcode. |
| OP_rol | IA-32/AMD64 rol opcode. |
| OP_ror | IA-32/AMD64 ror opcode. |
| OP_rcl | IA-32/AMD64 rcl opcode. |
| OP_rcr | IA-32/AMD64 rcr opcode. |
| OP_shl | IA-32/AMD64 shl opcode. |
| OP_shr | IA-32/AMD64 shr opcode. |
| OP_sar | IA-32/AMD64 sar opcode. |
| OP_not | IA-32/AMD64 not opcode. |
| OP_neg | IA-32/AMD64 neg opcode. |
| OP_mul | IA-32/AMD64 mul opcode. |
| OP_div | IA-32/AMD64 div opcode. |
| OP_idiv | IA-32/AMD64 idiv opcode. |
| OP_sldt | IA-32/AMD64 sldt opcode. |
| OP_str | IA-32/AMD64 str opcode. |
| OP_lldt | IA-32/AMD64 lldt opcode. |
| OP_ltr | IA-32/AMD64 ltr opcode. |
| OP_verr | IA-32/AMD64 verr opcode. |
| OP_verw | IA-32/AMD64 verw opcode. |
| OP_sgdt | IA-32/AMD64 sgdt opcode. |
| OP_sidt | IA-32/AMD64 sidt opcode. |
| OP_lgdt | IA-32/AMD64 lgdt opcode. |
| OP_lidt | IA-32/AMD64 lidt opcode. |
| OP_smsw | IA-32/AMD64 smsw opcode. |
| OP_lmsw | IA-32/AMD64 lmsw opcode. |
| OP_invlpg | IA-32/AMD64 invlpg opcode. |
| OP_cmpxchg8b | IA-32/AMD64 cmpxchg8b opcode. |
| OP_fxsave32 | IA-32/AMD64 fxsave opcode. |
| OP_fxrstor32 | IA-32/AMD64 fxrstor opcode. |
| OP_ldmxcsr | IA-32/AMD64 ldmxcsr opcode. |
| OP_stmxcsr | IA-32/AMD64 stmxcsr opcode. |
| OP_lfence | IA-32/AMD64 lfence opcode. |
| OP_mfence | IA-32/AMD64 mfence opcode. |
| OP_clflush | IA-32/AMD64 clflush opcode. |
| OP_sfence | IA-32/AMD64 sfence opcode. |
| OP_prefetchnta | IA-32/AMD64 prefetchnta opcode. |
| OP_prefetcht0 | IA-32/AMD64 prefetcht0 opcode. |
| OP_prefetcht1 | IA-32/AMD64 prefetcht1 opcode. |
| OP_prefetcht2 | IA-32/AMD64 prefetcht2 opcode. |
| OP_prefetch | IA-32/AMD64 prefetch opcode. |
| OP_prefetchw | IA-32/AMD64 prefetchw opcode. |
| OP_movups | IA-32/AMD64 movups opcode. |
| OP_movss | IA-32/AMD64 movss opcode. |
| OP_movupd | IA-32/AMD64 movupd opcode. |
| OP_movsd | IA-32/AMD64 movsd opcode. |
| OP_movlps | IA-32/AMD64 movlps opcode. |
| OP_movlpd | IA-32/AMD64 movlpd opcode. |
| OP_unpcklps | IA-32/AMD64 unpcklps opcode. |
| OP_unpcklpd | IA-32/AMD64 unpcklpd opcode. |
| OP_unpckhps | IA-32/AMD64 unpckhps opcode. |
| OP_unpckhpd | IA-32/AMD64 unpckhpd opcode. |
| OP_movhps | IA-32/AMD64 movhps opcode. |
| OP_movhpd | IA-32/AMD64 movhpd opcode. |
| OP_movaps | IA-32/AMD64 movaps opcode. |
| OP_movapd | IA-32/AMD64 movapd opcode. |
| OP_cvtpi2ps | IA-32/AMD64 cvtpi2ps opcode. |
| OP_cvtsi2ss | IA-32/AMD64 cvtsi2ss opcode. |
| OP_cvtpi2pd | IA-32/AMD64 cvtpi2pd opcode. |
| OP_cvtsi2sd | IA-32/AMD64 cvtsi2sd opcode. |
| OP_cvttps2pi | IA-32/AMD64 cvttps2pi opcode. |
| OP_cvttss2si | IA-32/AMD64 cvttss2si opcode. |
| OP_cvttpd2pi | IA-32/AMD64 cvttpd2pi opcode. |
| OP_cvttsd2si | IA-32/AMD64 cvttsd2si opcode. |
| OP_cvtps2pi | IA-32/AMD64 cvtps2pi opcode. |
| OP_cvtss2si | IA-32/AMD64 cvtss2si opcode. |
| OP_cvtpd2pi | IA-32/AMD64 cvtpd2pi opcode. |
| OP_cvtsd2si | IA-32/AMD64 cvtsd2si opcode. |
| OP_ucomiss | IA-32/AMD64 ucomiss opcode. |
| OP_ucomisd | IA-32/AMD64 ucomisd opcode. |
| OP_comiss | IA-32/AMD64 comiss opcode. |
| OP_comisd | IA-32/AMD64 comisd opcode. |
| OP_movmskps | IA-32/AMD64 movmskps opcode. |
| OP_movmskpd | IA-32/AMD64 movmskpd opcode. |
| OP_sqrtps | IA-32/AMD64 sqrtps opcode. |
| OP_sqrtss | IA-32/AMD64 sqrtss opcode. |
| OP_sqrtpd | IA-32/AMD64 sqrtpd opcode. |
| OP_sqrtsd | IA-32/AMD64 sqrtsd opcode. |
| OP_rsqrtps | IA-32/AMD64 rsqrtps opcode. |
| OP_rsqrtss | IA-32/AMD64 rsqrtss opcode. |
| OP_rcpps | IA-32/AMD64 rcpps opcode. |
| OP_rcpss | IA-32/AMD64 rcpss opcode. |
| OP_andps | IA-32/AMD64 andps opcode. |
| OP_andpd | IA-32/AMD64 andpd opcode. |
| OP_andnps | IA-32/AMD64 andnps opcode. |
| OP_andnpd | IA-32/AMD64 andnpd opcode. |
| OP_orps | IA-32/AMD64 orps opcode. |
| OP_orpd | IA-32/AMD64 orpd opcode. |
| OP_xorps | IA-32/AMD64 xorps opcode. |
| OP_xorpd | IA-32/AMD64 xorpd opcode. |
| OP_addps | IA-32/AMD64 addps opcode. |
| OP_addss | IA-32/AMD64 addss opcode. |
| OP_addpd | IA-32/AMD64 addpd opcode. |
| OP_addsd | IA-32/AMD64 addsd opcode. |
| OP_mulps | IA-32/AMD64 mulps opcode. |
| OP_mulss | IA-32/AMD64 mulss opcode. |
| OP_mulpd | IA-32/AMD64 mulpd opcode. |
| OP_mulsd | IA-32/AMD64 mulsd opcode. |
| OP_cvtps2pd | IA-32/AMD64 cvtps2pd opcode. |
| OP_cvtss2sd | IA-32/AMD64 cvtss2sd opcode. |
| OP_cvtpd2ps | IA-32/AMD64 cvtpd2ps opcode. |
| OP_cvtsd2ss | IA-32/AMD64 cvtsd2ss opcode. |
| OP_cvtdq2ps | IA-32/AMD64 cvtdq2ps opcode. |
| OP_cvttps2dq | IA-32/AMD64 cvttps2dq opcode. |
| OP_cvtps2dq | IA-32/AMD64 cvtps2dq opcode. |
| OP_subps | IA-32/AMD64 subps opcode. |
| OP_subss | IA-32/AMD64 subss opcode. |
| OP_subpd | IA-32/AMD64 subpd opcode. |
| OP_subsd | IA-32/AMD64 subsd opcode. |
| OP_minps | IA-32/AMD64 minps opcode. |
| OP_minss | IA-32/AMD64 minss opcode. |
| OP_minpd | IA-32/AMD64 minpd opcode. |
| OP_minsd | IA-32/AMD64 minsd opcode. |
| OP_divps | IA-32/AMD64 divps opcode. |
| OP_divss | IA-32/AMD64 divss opcode. |
| OP_divpd | IA-32/AMD64 divpd opcode. |
| OP_divsd | IA-32/AMD64 divsd opcode. |
| OP_maxps | IA-32/AMD64 maxps opcode. |
| OP_maxss | IA-32/AMD64 maxss opcode. |
| OP_maxpd | IA-32/AMD64 maxpd opcode. |
| OP_maxsd | IA-32/AMD64 maxsd opcode. |
| OP_cmpps | IA-32/AMD64 cmpps opcode. |
| OP_cmpss | IA-32/AMD64 cmpss opcode. |
| OP_cmppd | IA-32/AMD64 cmppd opcode. |
| OP_cmpsd | IA-32/AMD64 cmpsd opcode. |
| OP_shufps | IA-32/AMD64 shufps opcode. |
| OP_shufpd | IA-32/AMD64 shufpd opcode. |
| OP_cvtdq2pd | IA-32/AMD64 cvtdq2pd opcode. |
| OP_cvttpd2dq | IA-32/AMD64 cvttpd2dq opcode. |
| OP_cvtpd2dq | IA-32/AMD64 cvtpd2dq opcode. |
| OP_nop | IA-32/AMD64 nop opcode. |
| OP_pause | IA-32/AMD64 pause opcode. |
| OP_ins | IA-32/AMD64 ins opcode. |
| OP_rep_ins | IA-32/AMD64 rep_ins opcode. |
| OP_outs | IA-32/AMD64 outs opcode. |
| OP_rep_outs | IA-32/AMD64 rep_outs opcode. |
| OP_movs | IA-32/AMD64 movs opcode. |
| OP_rep_movs | IA-32/AMD64 rep_movs opcode. |
| OP_stos | IA-32/AMD64 stos opcode. |
| OP_rep_stos | IA-32/AMD64 rep_stos opcode. |
| OP_lods | IA-32/AMD64 lods opcode. |
| OP_rep_lods | IA-32/AMD64 rep_lods opcode. |
| OP_cmps | IA-32/AMD64 cmps opcode. |
| OP_rep_cmps | IA-32/AMD64 rep_cmps opcode. |
| OP_repne_cmps | IA-32/AMD64 repne_cmps opcode. |
| OP_scas | IA-32/AMD64 scas opcode. |
| OP_rep_scas | IA-32/AMD64 rep_scas opcode. |
| OP_repne_scas | IA-32/AMD64 repne_scas opcode. |
| OP_fadd | IA-32/AMD64 fadd opcode. |
| OP_fmul | IA-32/AMD64 fmul opcode. |
| OP_fcom | IA-32/AMD64 fcom opcode. |
| OP_fcomp | IA-32/AMD64 fcomp opcode. |
| OP_fsub | IA-32/AMD64 fsub opcode. |
| OP_fsubr | IA-32/AMD64 fsubr opcode. |
| OP_fdiv | IA-32/AMD64 fdiv opcode. |
| OP_fdivr | IA-32/AMD64 fdivr opcode. |
| OP_fld | IA-32/AMD64 fld opcode. |
| OP_fst | IA-32/AMD64 fst opcode. |
| OP_fstp | IA-32/AMD64 fstp opcode. |
| OP_fldenv | IA-32/AMD64 fldenv opcode. |
| OP_fldcw | IA-32/AMD64 fldcw opcode. |
| OP_fnstenv | IA-32/AMD64 fnstenv opcode. |
| OP_fnstcw | IA-32/AMD64 fnstcw opcode. |
| OP_fiadd | IA-32/AMD64 fiadd opcode. |
| OP_fimul | IA-32/AMD64 fimul opcode. |
| OP_ficom | IA-32/AMD64 ficom opcode. |
| OP_ficomp | IA-32/AMD64 ficomp opcode. |
| OP_fisub | IA-32/AMD64 fisub opcode. |
| OP_fisubr | IA-32/AMD64 fisubr opcode. |
| OP_fidiv | IA-32/AMD64 fidiv opcode. |
| OP_fidivr | IA-32/AMD64 fidivr opcode. |
| OP_fild | IA-32/AMD64 fild opcode. |
| OP_fist | IA-32/AMD64 fist opcode. |
| OP_fistp | IA-32/AMD64 fistp opcode. |
| OP_frstor | IA-32/AMD64 frstor opcode. |
| OP_fnsave | IA-32/AMD64 fnsave opcode. |
| OP_fnstsw | IA-32/AMD64 fnstsw opcode. |
| OP_fbld | IA-32/AMD64 fbld opcode. |
| OP_fbstp | IA-32/AMD64 fbstp opcode. |
| OP_fxch | IA-32/AMD64 fxch opcode. |
| OP_fnop | IA-32/AMD64 fnop opcode. |
| OP_fchs | IA-32/AMD64 fchs opcode. |
| OP_fabs | IA-32/AMD64 fabs opcode. |
| OP_ftst | IA-32/AMD64 ftst opcode. |
| OP_fxam | IA-32/AMD64 fxam opcode. |
| OP_fld1 | IA-32/AMD64 fld1 opcode. |
| OP_fldl2t | IA-32/AMD64 fldl2t opcode. |
| OP_fldl2e | IA-32/AMD64 fldl2e opcode. |
| OP_fldpi | IA-32/AMD64 fldpi opcode. |
| OP_fldlg2 | IA-32/AMD64 fldlg2 opcode. |
| OP_fldln2 | IA-32/AMD64 fldln2 opcode. |
| OP_fldz | IA-32/AMD64 fldz opcode. |
| OP_f2xm1 | IA-32/AMD64 f2xm1 opcode. |
| OP_fyl2x | IA-32/AMD64 fyl2x opcode. |
| OP_fptan | IA-32/AMD64 fptan opcode. |
| OP_fpatan | IA-32/AMD64 fpatan opcode. |
| OP_fxtract | IA-32/AMD64 fxtract opcode. |
| OP_fprem1 | IA-32/AMD64 fprem1 opcode. |
| OP_fdecstp | IA-32/AMD64 fdecstp opcode. |
| OP_fincstp | IA-32/AMD64 fincstp opcode. |
| OP_fprem | IA-32/AMD64 fprem opcode. |
| OP_fyl2xp1 | IA-32/AMD64 fyl2xp1 opcode. |
| OP_fsqrt | IA-32/AMD64 fsqrt opcode. |
| OP_fsincos | IA-32/AMD64 fsincos opcode. |
| OP_frndint | IA-32/AMD64 frndint opcode. |
| OP_fscale | IA-32/AMD64 fscale opcode. |
| OP_fsin | IA-32/AMD64 fsin opcode. |
| OP_fcos | IA-32/AMD64 fcos opcode. |
| OP_fcmovb | IA-32/AMD64 fcmovb opcode. |
| OP_fcmove | IA-32/AMD64 fcmove opcode. |
| OP_fcmovbe | IA-32/AMD64 fcmovbe opcode. |
| OP_fcmovu | IA-32/AMD64 fcmovu opcode. |
| OP_fucompp | IA-32/AMD64 fucompp opcode. |
| OP_fcmovnb | IA-32/AMD64 fcmovnb opcode. |
| OP_fcmovne | IA-32/AMD64 fcmovne opcode. |
| OP_fcmovnbe | IA-32/AMD64 fcmovnbe opcode. |
| OP_fcmovnu | IA-32/AMD64 fcmovnu opcode. |
| OP_fnclex | IA-32/AMD64 fnclex opcode. |
| OP_fninit | IA-32/AMD64 fninit opcode. |
| OP_fucomi | IA-32/AMD64 fucomi opcode. |
| OP_fcomi | IA-32/AMD64 fcomi opcode. |
| OP_ffree | IA-32/AMD64 ffree opcode. |
| OP_fucom | IA-32/AMD64 fucom opcode. |
| OP_fucomp | IA-32/AMD64 fucomp opcode. |
| OP_faddp | IA-32/AMD64 faddp opcode. |
| OP_fmulp | IA-32/AMD64 fmulp opcode. |
| OP_fcompp | IA-32/AMD64 fcompp opcode. |
| OP_fsubrp | IA-32/AMD64 fsubrp opcode. |
| OP_fsubp | IA-32/AMD64 fsubp opcode. |
| OP_fdivrp | IA-32/AMD64 fdivrp opcode. |
| OP_fdivp | IA-32/AMD64 fdivp opcode. |
| OP_fucomip | IA-32/AMD64 fucomip opcode. |
| OP_fcomip | IA-32/AMD64 fcomip opcode. |
| OP_fisttp | IA-32/AMD64 fisttp opcode. |
| OP_haddpd | IA-32/AMD64 haddpd opcode. |
| OP_haddps | IA-32/AMD64 haddps opcode. |
| OP_hsubpd | IA-32/AMD64 hsubpd opcode. |
| OP_hsubps | IA-32/AMD64 hsubps opcode. |
| OP_addsubpd | IA-32/AMD64 addsubpd opcode. |
| OP_addsubps | IA-32/AMD64 addsubps opcode. |
| OP_lddqu | IA-32/AMD64 lddqu opcode. |
| OP_monitor | IA-32/AMD64 monitor opcode. |
| OP_mwait | IA-32/AMD64 mwait opcode. |
| OP_movsldup | IA-32/AMD64 movsldup opcode. |
| OP_movshdup | IA-32/AMD64 movshdup opcode. |
| OP_movddup | IA-32/AMD64 movddup opcode. |
| OP_femms | IA-32/AMD64 femms opcode. |
| OP_unknown_3dnow | IA-32/AMD64 unknown_3dnow opcode. |
| OP_pavgusb | IA-32/AMD64 pavgusb opcode. |
| OP_pfadd | IA-32/AMD64 pfadd opcode. |
| OP_pfacc | IA-32/AMD64 pfacc opcode. |
| OP_pfcmpge | IA-32/AMD64 pfcmpge opcode. |
| OP_pfcmpgt | IA-32/AMD64 pfcmpgt opcode. |
| OP_pfcmpeq | IA-32/AMD64 pfcmpeq opcode. |
| OP_pfmin | IA-32/AMD64 pfmin opcode. |
| OP_pfmax | IA-32/AMD64 pfmax opcode. |
| OP_pfmul | IA-32/AMD64 pfmul opcode. |
| OP_pfrcp | IA-32/AMD64 pfrcp opcode. |
| OP_pfrcpit1 | IA-32/AMD64 pfrcpit1 opcode. |
| OP_pfrcpit2 | IA-32/AMD64 pfrcpit2 opcode. |
| OP_pfrsqrt | IA-32/AMD64 pfrsqrt opcode. |
| OP_pfrsqit1 | IA-32/AMD64 pfrsqit1 opcode. |
| OP_pmulhrw | IA-32/AMD64 pmulhrw opcode. |
| OP_pfsub | IA-32/AMD64 pfsub opcode. |
| OP_pfsubr | IA-32/AMD64 pfsubr opcode. |
| OP_pi2fd | IA-32/AMD64 pi2fd opcode. |
| OP_pf2id | IA-32/AMD64 pf2id opcode. |
| OP_pi2fw | IA-32/AMD64 pi2fw opcode. |
| OP_pf2iw | IA-32/AMD64 pf2iw opcode. |
| OP_pfnacc | IA-32/AMD64 pfnacc opcode. |
| OP_pfpnacc | IA-32/AMD64 pfpnacc opcode. |
| OP_pswapd | IA-32/AMD64 pswapd opcode. |
| OP_pshufb | IA-32/AMD64 pshufb opcode. |
| OP_phaddw | IA-32/AMD64 phaddw opcode. |
| OP_phaddd | IA-32/AMD64 phaddd opcode. |
| OP_phaddsw | IA-32/AMD64 phaddsw opcode. |
| OP_pmaddubsw | IA-32/AMD64 pmaddubsw opcode. |
| OP_phsubw | IA-32/AMD64 phsubw opcode. |
| OP_phsubd | IA-32/AMD64 phsubd opcode. |
| OP_phsubsw | IA-32/AMD64 phsubsw opcode. |
| OP_psignb | IA-32/AMD64 psignb opcode. |
| OP_psignw | IA-32/AMD64 psignw opcode. |
| OP_psignd | IA-32/AMD64 psignd opcode. |
| OP_pmulhrsw | IA-32/AMD64 pmulhrsw opcode. |
| OP_pabsb | IA-32/AMD64 pabsb opcode. |
| OP_pabsw | IA-32/AMD64 pabsw opcode. |
| OP_pabsd | IA-32/AMD64 pabsd opcode. |
| OP_palignr | IA-32/AMD64 palignr opcode. |
| OP_popcnt | IA-32/AMD64 popcnt opcode. |
| OP_movntss | IA-32/AMD64 movntss opcode. |
| OP_movntsd | IA-32/AMD64 movntsd opcode. |
| OP_extrq | IA-32/AMD64 extrq opcode. |
| OP_insertq | IA-32/AMD64 insertq opcode. |
| OP_lzcnt | IA-32/AMD64 lzcnt opcode. |
| OP_pblendvb | IA-32/AMD64 pblendvb opcode. |
| OP_blendvps | IA-32/AMD64 blendvps opcode. |
| OP_blendvpd | IA-32/AMD64 blendvpd opcode. |
| OP_ptest | IA-32/AMD64 ptest opcode. |
| OP_pmovsxbw | IA-32/AMD64 pmovsxbw opcode. |
| OP_pmovsxbd | IA-32/AMD64 pmovsxbd opcode. |
| OP_pmovsxbq | IA-32/AMD64 pmovsxbq opcode. |
| OP_pmovsxwd | IA-32/AMD64 pmovsxwd opcode. |
| OP_pmovsxwq | IA-32/AMD64 pmovsxwq opcode. |
| OP_pmovsxdq | IA-32/AMD64 pmovsxdq opcode. |
| OP_pmuldq | IA-32/AMD64 pmuldq opcode. |
| OP_pcmpeqq | IA-32/AMD64 pcmpeqq opcode. |
| OP_movntdqa | IA-32/AMD64 movntdqa opcode. |
| OP_packusdw | IA-32/AMD64 packusdw opcode. |
| OP_pmovzxbw | IA-32/AMD64 pmovzxbw opcode. |
| OP_pmovzxbd | IA-32/AMD64 pmovzxbd opcode. |
| OP_pmovzxbq | IA-32/AMD64 pmovzxbq opcode. |
| OP_pmovzxwd | IA-32/AMD64 pmovzxwd opcode. |
| OP_pmovzxwq | IA-32/AMD64 pmovzxwq opcode. |
| OP_pmovzxdq | IA-32/AMD64 pmovzxdq opcode. |
| OP_pcmpgtq | IA-32/AMD64 pcmpgtq opcode. |
| OP_pminsb | IA-32/AMD64 pminsb opcode. |
| OP_pminsd | IA-32/AMD64 pminsd opcode. |
| OP_pminuw | IA-32/AMD64 pminuw opcode. |
| OP_pminud | IA-32/AMD64 pminud opcode. |
| OP_pmaxsb | IA-32/AMD64 pmaxsb opcode. |
| OP_pmaxsd | IA-32/AMD64 pmaxsd opcode. |
| OP_pmaxuw | IA-32/AMD64 pmaxuw opcode. |
| OP_pmaxud | IA-32/AMD64 pmaxud opcode. |
| OP_pmulld | IA-32/AMD64 pmulld opcode. |
| OP_phminposuw | IA-32/AMD64 phminposuw opcode. |
| OP_crc32 | IA-32/AMD64 crc32 opcode. |
| OP_pextrb | IA-32/AMD64 pextrb opcode. |
| OP_pextrd | IA-32/AMD64 pextrd opcode. |
| OP_extractps | IA-32/AMD64 extractps opcode. |
| OP_roundps | IA-32/AMD64 roundps opcode. |
| OP_roundpd | IA-32/AMD64 roundpd opcode. |
| OP_roundss | IA-32/AMD64 roundss opcode. |
| OP_roundsd | IA-32/AMD64 roundsd opcode. |
| OP_blendps | IA-32/AMD64 blendps opcode. |
| OP_blendpd | IA-32/AMD64 blendpd opcode. |
| OP_pblendw | IA-32/AMD64 pblendw opcode. |
| OP_pinsrb | IA-32/AMD64 pinsrb opcode. |
| OP_insertps | IA-32/AMD64 insertps opcode. |
| OP_pinsrd | IA-32/AMD64 pinsrd opcode. |
| OP_dpps | IA-32/AMD64 dpps opcode. |
| OP_dppd | IA-32/AMD64 dppd opcode. |
| OP_mpsadbw | IA-32/AMD64 mpsadbw opcode. |
| OP_pcmpestrm | IA-32/AMD64 pcmpestrm opcode. |
| OP_pcmpestri | IA-32/AMD64 pcmpestri opcode. |
| OP_pcmpistrm | IA-32/AMD64 pcmpistrm opcode. |
| OP_pcmpistri | IA-32/AMD64 pcmpistri opcode. |
| OP_movsxd | IA-32/AMD64 movsxd opcode. |
| OP_swapgs | IA-32/AMD64 swapgs opcode. |
| OP_vmcall | IA-32/AMD64 vmcall opcode. |
| OP_vmlaunch | IA-32/AMD64 vmlaunch opcode. |
| OP_vmresume | IA-32/AMD64 vmresume opcode. |
| OP_vmxoff | IA-32/AMD64 vmxoff opcode. |
| OP_vmptrst | IA-32/AMD64 vmptrst opcode. |
| OP_vmptrld | IA-32/AMD64 vmptrld opcode. |
| OP_vmxon | IA-32/AMD64 vmxon opcode. |
| OP_vmclear | IA-32/AMD64 vmclear opcode. |
| OP_vmread | IA-32/AMD64 vmread opcode. |
| OP_vmwrite | IA-32/AMD64 vmwrite opcode. |
| OP_int1 | IA-32/AMD64 int1 opcode. |
| OP_salc | IA-32/AMD64 salc opcode. |
| OP_ffreep | IA-32/AMD64 ffreep opcode. |
| OP_vmrun | IA-32/AMD64 vmrun opcode. |
| OP_vmmcall | IA-32/AMD64 vmmcall opcode. |
| OP_vmload | IA-32/AMD64 vmload opcode. |
| OP_vmsave | IA-32/AMD64 vmsave opcode. |
| OP_stgi | IA-32/AMD64 stgi opcode. |
| OP_clgi | IA-32/AMD64 clgi opcode. |
| OP_skinit | IA-32/AMD64 skinit opcode. |
| OP_invlpga | IA-32/AMD64 invlpga opcode. |
| OP_rdtscp | IA-32/AMD64 rdtscp opcode. |
| OP_invept | IA-32/AMD64 invept opcode. |
| OP_invvpid | IA-32/AMD64 invvpid opcode. |
| OP_pclmulqdq | IA-32/AMD64 pclmulqdq opcode. |
| OP_aesimc | IA-32/AMD64 aesimc opcode. |
| OP_aesenc | IA-32/AMD64 aesenc opcode. |
| OP_aesenclast | IA-32/AMD64 aesenclast opcode. |
| OP_aesdec | IA-32/AMD64 aesdec opcode. |
| OP_aesdeclast | IA-32/AMD64 aesdeclast opcode. |
| OP_aeskeygenassist | IA-32/AMD64 aeskeygenassist opcode. |
| OP_movbe | IA-32/AMD64 movbe opcode. |
| OP_xgetbv | IA-32/AMD64 xgetbv opcode. |
| OP_xsetbv | IA-32/AMD64 xsetbv opcode. |
| OP_xsave32 | IA-32/AMD64 xsave opcode. |
| OP_xrstor32 | IA-32/AMD64 xrstor opcode. |
| OP_xsaveopt32 | IA-32/AMD64 xsaveopt opcode. |
| OP_vmovss | IA-32/AMD64 vmovss opcode. |
| OP_vmovsd | IA-32/AMD64 vmovsd opcode. |
| OP_vmovups | IA-32/AMD64 vmovups opcode. |
| OP_vmovupd | IA-32/AMD64 vmovupd opcode. |
| OP_vmovlps | IA-32/AMD64 vmovlps opcode. |
| OP_vmovsldup | IA-32/AMD64 vmovsldup opcode. |
| OP_vmovlpd | IA-32/AMD64 vmovlpd opcode. |
| OP_vmovddup | IA-32/AMD64 vmovddup opcode. |
| OP_vunpcklps | IA-32/AMD64 vunpcklps opcode. |
| OP_vunpcklpd | IA-32/AMD64 vunpcklpd opcode. |
| OP_vunpckhps | IA-32/AMD64 vunpckhps opcode. |
| OP_vunpckhpd | IA-32/AMD64 vunpckhpd opcode. |
| OP_vmovhps | IA-32/AMD64 vmovhps opcode. |
| OP_vmovshdup | IA-32/AMD64 vmovshdup opcode. |
| OP_vmovhpd | IA-32/AMD64 vmovhpd opcode. |
| OP_vmovaps | IA-32/AMD64 vmovaps opcode. |
| OP_vmovapd | IA-32/AMD64 vmovapd opcode. |
| OP_vcvtsi2ss | IA-32/AMD64 vcvtsi2ss opcode. |
| OP_vcvtsi2sd | IA-32/AMD64 vcvtsi2sd opcode. |
| OP_vmovntps | IA-32/AMD64 vmovntps opcode. |
| OP_vmovntpd | IA-32/AMD64 vmovntpd opcode. |
| OP_vcvttss2si | IA-32/AMD64 vcvttss2si opcode. |
| OP_vcvttsd2si | IA-32/AMD64 vcvttsd2si opcode. |
| OP_vcvtss2si | IA-32/AMD64 vcvtss2si opcode. |
| OP_vcvtsd2si | IA-32/AMD64 vcvtsd2si opcode. |
| OP_vucomiss | IA-32/AMD64 vucomiss opcode. |
| OP_vucomisd | IA-32/AMD64 vucomisd opcode. |
| OP_vcomiss | IA-32/AMD64 vcomiss opcode. |
| OP_vcomisd | IA-32/AMD64 vcomisd opcode. |
| OP_vmovmskps | IA-32/AMD64 vmovmskps opcode. |
| OP_vmovmskpd | IA-32/AMD64 vmovmskpd opcode. |
| OP_vsqrtps | IA-32/AMD64 vsqrtps opcode. |
| OP_vsqrtss | IA-32/AMD64 vsqrtss opcode. |
| OP_vsqrtpd | IA-32/AMD64 vsqrtpd opcode. |
| OP_vsqrtsd | IA-32/AMD64 vsqrtsd opcode. |
| OP_vrsqrtps | IA-32/AMD64 vrsqrtps opcode. |
| OP_vrsqrtss | IA-32/AMD64 vrsqrtss opcode. |
| OP_vrcpps | IA-32/AMD64 vrcpps opcode. |
| OP_vrcpss | IA-32/AMD64 vrcpss opcode. |
| OP_vandps | IA-32/AMD64 vandps opcode. |
| OP_vandpd | IA-32/AMD64 vandpd opcode. |
| OP_vandnps | IA-32/AMD64 vandnps opcode. |
| OP_vandnpd | IA-32/AMD64 vandnpd opcode. |
| OP_vorps | IA-32/AMD64 vorps opcode. |
| OP_vorpd | IA-32/AMD64 vorpd opcode. |
| OP_vxorps | IA-32/AMD64 vxorps opcode. |
| OP_vxorpd | IA-32/AMD64 vxorpd opcode. |
| OP_vaddps | IA-32/AMD64 vaddps opcode. |
| OP_vaddss | IA-32/AMD64 vaddss opcode. |
| OP_vaddpd | IA-32/AMD64 vaddpd opcode. |
| OP_vaddsd | IA-32/AMD64 vaddsd opcode. |
| OP_vmulps | IA-32/AMD64 vmulps opcode. |
| OP_vmulss | IA-32/AMD64 vmulss opcode. |
| OP_vmulpd | IA-32/AMD64 vmulpd opcode. |
| OP_vmulsd | IA-32/AMD64 vmulsd opcode. |
| OP_vcvtps2pd | IA-32/AMD64 vcvtps2pd opcode. |
| OP_vcvtss2sd | IA-32/AMD64 vcvtss2sd opcode. |
| OP_vcvtpd2ps | IA-32/AMD64 vcvtpd2ps opcode. |
| OP_vcvtsd2ss | IA-32/AMD64 vcvtsd2ss opcode. |
| OP_vcvtdq2ps | IA-32/AMD64 vcvtdq2ps opcode. |
| OP_vcvttps2dq | IA-32/AMD64 vcvttps2dq opcode. |
| OP_vcvtps2dq | IA-32/AMD64 vcvtps2dq opcode. |
| OP_vsubps | IA-32/AMD64 vsubps opcode. |
| OP_vsubss | IA-32/AMD64 vsubss opcode. |
| OP_vsubpd | IA-32/AMD64 vsubpd opcode. |
| OP_vsubsd | IA-32/AMD64 vsubsd opcode. |
| OP_vminps | IA-32/AMD64 vminps opcode. |
| OP_vminss | IA-32/AMD64 vminss opcode. |
| OP_vminpd | IA-32/AMD64 vminpd opcode. |
| OP_vminsd | IA-32/AMD64 vminsd opcode. |
| OP_vdivps | IA-32/AMD64 vdivps opcode. |
| OP_vdivss | IA-32/AMD64 vdivss opcode. |
| OP_vdivpd | IA-32/AMD64 vdivpd opcode. |
| OP_vdivsd | IA-32/AMD64 vdivsd opcode. |
| OP_vmaxps | IA-32/AMD64 vmaxps opcode. |
| OP_vmaxss | IA-32/AMD64 vmaxss opcode. |
| OP_vmaxpd | IA-32/AMD64 vmaxpd opcode. |
| OP_vmaxsd | IA-32/AMD64 vmaxsd opcode. |
| OP_vpunpcklbw | IA-32/AMD64 vpunpcklbw opcode. |
| OP_vpunpcklwd | IA-32/AMD64 vpunpcklwd opcode. |
| OP_vpunpckldq | IA-32/AMD64 vpunpckldq opcode. |
| OP_vpacksswb | IA-32/AMD64 vpacksswb opcode. |
| OP_vpcmpgtb | IA-32/AMD64 vpcmpgtb opcode. |
| OP_vpcmpgtw | IA-32/AMD64 vpcmpgtw opcode. |
| OP_vpcmpgtd | IA-32/AMD64 vpcmpgtd opcode. |
| OP_vpackuswb | IA-32/AMD64 vpackuswb opcode. |
| OP_vpunpckhbw | IA-32/AMD64 vpunpckhbw opcode. |
| OP_vpunpckhwd | IA-32/AMD64 vpunpckhwd opcode. |
| OP_vpunpckhdq | IA-32/AMD64 vpunpckhdq opcode. |
| OP_vpackssdw | IA-32/AMD64 vpackssdw opcode. |
| OP_vpunpcklqdq | IA-32/AMD64 vpunpcklqdq opcode. |
| OP_vpunpckhqdq | IA-32/AMD64 vpunpckhqdq opcode. |
| OP_vmovd | IA-32/AMD64 vmovd opcode. |
| OP_vpshufhw | IA-32/AMD64 vpshufhw opcode. |
| OP_vpshufd | IA-32/AMD64 vpshufd opcode. |
| OP_vpshuflw | IA-32/AMD64 vpshuflw opcode. |
| OP_vpcmpeqb | IA-32/AMD64 vpcmpeqb opcode. |
| OP_vpcmpeqw | IA-32/AMD64 vpcmpeqw opcode. |
| OP_vpcmpeqd | IA-32/AMD64 vpcmpeqd opcode. |
| OP_vmovq | IA-32/AMD64 vmovq opcode. |
| OP_vcmpps | IA-32/AMD64 vcmpps opcode. |
| OP_vcmpss | IA-32/AMD64 vcmpss opcode. |
| OP_vcmppd | IA-32/AMD64 vcmppd opcode. |
| OP_vcmpsd | IA-32/AMD64 vcmpsd opcode. |
| OP_vpinsrw | IA-32/AMD64 vpinsrw opcode. |
| OP_vpextrw | IA-32/AMD64 vpextrw opcode. |
| OP_vshufps | IA-32/AMD64 vshufps opcode. |
| OP_vshufpd | IA-32/AMD64 vshufpd opcode. |
| OP_vpsrlw | IA-32/AMD64 vpsrlw opcode. |
| OP_vpsrld | IA-32/AMD64 vpsrld opcode. |
| OP_vpsrlq | IA-32/AMD64 vpsrlq opcode. |
| OP_vpaddq | IA-32/AMD64 vpaddq opcode. |
| OP_vpmullw | IA-32/AMD64 vpmullw opcode. |
| OP_vpmovmskb | IA-32/AMD64 vpmovmskb opcode. |
| OP_vpsubusb | IA-32/AMD64 vpsubusb opcode. |
| OP_vpsubusw | IA-32/AMD64 vpsubusw opcode. |
| OP_vpminub | IA-32/AMD64 vpminub opcode. |
| OP_vpand | IA-32/AMD64 vpand opcode. |
| OP_vpaddusb | IA-32/AMD64 vpaddusb opcode. |
| OP_vpaddusw | IA-32/AMD64 vpaddusw opcode. |
| OP_vpmaxub | IA-32/AMD64 vpmaxub opcode. |
| OP_vpandn | IA-32/AMD64 vpandn opcode. |
| OP_vpavgb | IA-32/AMD64 vpavgb opcode. |
| OP_vpsraw | IA-32/AMD64 vpsraw opcode. |
| OP_vpsrad | IA-32/AMD64 vpsrad opcode. |
| OP_vpavgw | IA-32/AMD64 vpavgw opcode. |
| OP_vpmulhuw | IA-32/AMD64 vpmulhuw opcode. |
| OP_vpmulhw | IA-32/AMD64 vpmulhw opcode. |
| OP_vcvtdq2pd | IA-32/AMD64 vcvtdq2pd opcode. |
| OP_vcvttpd2dq | IA-32/AMD64 vcvttpd2dq opcode. |
| OP_vcvtpd2dq | IA-32/AMD64 vcvtpd2dq opcode. |
| OP_vmovntdq | IA-32/AMD64 vmovntdq opcode. |
| OP_vpsubsb | IA-32/AMD64 vpsubsb opcode. |
| OP_vpsubsw | IA-32/AMD64 vpsubsw opcode. |
| OP_vpminsw | IA-32/AMD64 vpminsw opcode. |
| OP_vpor | IA-32/AMD64 vpor opcode. |
| OP_vpaddsb | IA-32/AMD64 vpaddsb opcode. |
| OP_vpaddsw | IA-32/AMD64 vpaddsw opcode. |
| OP_vpmaxsw | IA-32/AMD64 vpmaxsw opcode. |
| OP_vpxor | IA-32/AMD64 vpxor opcode. |
| OP_vpsllw | IA-32/AMD64 vpsllw opcode. |
| OP_vpslld | IA-32/AMD64 vpslld opcode. |
| OP_vpsllq | IA-32/AMD64 vpsllq opcode. |
| OP_vpmuludq | IA-32/AMD64 vpmuludq opcode. |
| OP_vpmaddwd | IA-32/AMD64 vpmaddwd opcode. |
| OP_vpsadbw | IA-32/AMD64 vpsadbw opcode. |
| OP_vmaskmovdqu | IA-32/AMD64 vmaskmovdqu opcode. |
| OP_vpsubb | IA-32/AMD64 vpsubb opcode. |
| OP_vpsubw | IA-32/AMD64 vpsubw opcode. |
| OP_vpsubd | IA-32/AMD64 vpsubd opcode. |
| OP_vpsubq | IA-32/AMD64 vpsubq opcode. |
| OP_vpaddb | IA-32/AMD64 vpaddb opcode. |
| OP_vpaddw | IA-32/AMD64 vpaddw opcode. |
| OP_vpaddd | IA-32/AMD64 vpaddd opcode. |
| OP_vpsrldq | IA-32/AMD64 vpsrldq opcode. |
| OP_vpslldq | IA-32/AMD64 vpslldq opcode. |
| OP_vmovdqu | IA-32/AMD64 vmovdqu opcode. |
| OP_vmovdqa | IA-32/AMD64 vmovdqa opcode. |
| OP_vhaddpd | IA-32/AMD64 vhaddpd opcode. |
| OP_vhaddps | IA-32/AMD64 vhaddps opcode. |
| OP_vhsubpd | IA-32/AMD64 vhsubpd opcode. |
| OP_vhsubps | IA-32/AMD64 vhsubps opcode. |
| OP_vaddsubpd | IA-32/AMD64 vaddsubpd opcode. |
| OP_vaddsubps | IA-32/AMD64 vaddsubps opcode. |
| OP_vlddqu | IA-32/AMD64 vlddqu opcode. |
| OP_vpshufb | IA-32/AMD64 vpshufb opcode. |
| OP_vphaddw | IA-32/AMD64 vphaddw opcode. |
| OP_vphaddd | IA-32/AMD64 vphaddd opcode. |
| OP_vphaddsw | IA-32/AMD64 vphaddsw opcode. |
| OP_vpmaddubsw | IA-32/AMD64 vpmaddubsw opcode. |
| OP_vphsubw | IA-32/AMD64 vphsubw opcode. |
| OP_vphsubd | IA-32/AMD64 vphsubd opcode. |
| OP_vphsubsw | IA-32/AMD64 vphsubsw opcode. |
| OP_vpsignb | IA-32/AMD64 vpsignb opcode. |
| OP_vpsignw | IA-32/AMD64 vpsignw opcode. |
| OP_vpsignd | IA-32/AMD64 vpsignd opcode. |
| OP_vpmulhrsw | IA-32/AMD64 vpmulhrsw opcode. |
| OP_vpabsb | IA-32/AMD64 vpabsb opcode. |
| OP_vpabsw | IA-32/AMD64 vpabsw opcode. |
| OP_vpabsd | IA-32/AMD64 vpabsd opcode. |
| OP_vpalignr | IA-32/AMD64 vpalignr opcode. |
| OP_vpblendvb | IA-32/AMD64 vpblendvb opcode. |
| OP_vblendvps | IA-32/AMD64 vblendvps opcode. |
| OP_vblendvpd | IA-32/AMD64 vblendvpd opcode. |
| OP_vptest | IA-32/AMD64 vptest opcode. |
| OP_vpmovsxbw | IA-32/AMD64 vpmovsxbw opcode. |
| OP_vpmovsxbd | IA-32/AMD64 vpmovsxbd opcode. |
| OP_vpmovsxbq | IA-32/AMD64 vpmovsxbq opcode. |
| OP_vpmovsxwd | IA-32/AMD64 vpmovsxwd opcode. |
| OP_vpmovsxwq | IA-32/AMD64 vpmovsxwq opcode. |
| OP_vpmovsxdq | IA-32/AMD64 vpmovsxdq opcode. |
| OP_vpmuldq | IA-32/AMD64 vpmuldq opcode. |
| OP_vpcmpeqq | IA-32/AMD64 vpcmpeqq opcode. |
| OP_vmovntdqa | IA-32/AMD64 vmovntdqa opcode. |
| OP_vpackusdw | IA-32/AMD64 vpackusdw opcode. |
| OP_vpmovzxbw | IA-32/AMD64 vpmovzxbw opcode. |
| OP_vpmovzxbd | IA-32/AMD64 vpmovzxbd opcode. |
| OP_vpmovzxbq | IA-32/AMD64 vpmovzxbq opcode. |
| OP_vpmovzxwd | IA-32/AMD64 vpmovzxwd opcode. |
| OP_vpmovzxwq | IA-32/AMD64 vpmovzxwq opcode. |
| OP_vpmovzxdq | IA-32/AMD64 vpmovzxdq opcode. |
| OP_vpcmpgtq | IA-32/AMD64 vpcmpgtq opcode. |
| OP_vpminsb | IA-32/AMD64 vpminsb opcode. |
| OP_vpminsd | IA-32/AMD64 vpminsd opcode. |
| OP_vpminuw | IA-32/AMD64 vpminuw opcode. |
| OP_vpminud | IA-32/AMD64 vpminud opcode. |
| OP_vpmaxsb | IA-32/AMD64 vpmaxsb opcode. |
| OP_vpmaxsd | IA-32/AMD64 vpmaxsd opcode. |
| OP_vpmaxuw | IA-32/AMD64 vpmaxuw opcode. |
| OP_vpmaxud | IA-32/AMD64 vpmaxud opcode. |
| OP_vpmulld | IA-32/AMD64 vpmulld opcode. |
| OP_vphminposuw | IA-32/AMD64 vphminposuw opcode. |
| OP_vaesimc | IA-32/AMD64 vaesimc opcode. |
| OP_vaesenc | IA-32/AMD64 vaesenc opcode. |
| OP_vaesenclast | IA-32/AMD64 vaesenclast opcode. |
| OP_vaesdec | IA-32/AMD64 vaesdec opcode. |
| OP_vaesdeclast | IA-32/AMD64 vaesdeclast opcode. |
| OP_vpextrb | IA-32/AMD64 vpextrb opcode. |
| OP_vpextrd | IA-32/AMD64 vpextrd opcode. |
| OP_vextractps | IA-32/AMD64 vextractps opcode. |
| OP_vroundps | IA-32/AMD64 vroundps opcode. |
| OP_vroundpd | IA-32/AMD64 vroundpd opcode. |
| OP_vroundss | IA-32/AMD64 vroundss opcode. |
| OP_vroundsd | IA-32/AMD64 vroundsd opcode. |
| OP_vblendps | IA-32/AMD64 vblendps opcode. |
| OP_vblendpd | IA-32/AMD64 vblendpd opcode. |
| OP_vpblendw | IA-32/AMD64 vpblendw opcode. |
| OP_vpinsrb | IA-32/AMD64 vpinsrb opcode. |
| OP_vinsertps | IA-32/AMD64 vinsertps opcode. |
| OP_vpinsrd | IA-32/AMD64 vpinsrd opcode. |
| OP_vdpps | IA-32/AMD64 vdpps opcode. |
| OP_vdppd | IA-32/AMD64 vdppd opcode. |
| OP_vmpsadbw | IA-32/AMD64 vmpsadbw opcode. |
| OP_vpcmpestrm | IA-32/AMD64 vpcmpestrm opcode. |
| OP_vpcmpestri | IA-32/AMD64 vpcmpestri opcode. |
| OP_vpcmpistrm | IA-32/AMD64 vpcmpistrm opcode. |
| OP_vpcmpistri | IA-32/AMD64 vpcmpistri opcode. |
| OP_vpclmulqdq | IA-32/AMD64 vpclmulqdq opcode. |
| OP_vaeskeygenassist | IA-32/AMD64 vaeskeygenassist opcode. |
| OP_vtestps | IA-32/AMD64 vtestps opcode. |
| OP_vtestpd | IA-32/AMD64 vtestpd opcode. |
| OP_vzeroupper | IA-32/AMD64 vzeroupper opcode. |
| OP_vzeroall | IA-32/AMD64 vzeroall opcode. |
| OP_vldmxcsr | IA-32/AMD64 vldmxcsr opcode. |
| OP_vstmxcsr | IA-32/AMD64 vstmxcsr opcode. |
| OP_vbroadcastss | IA-32/AMD64 vbroadcastss opcode. |
| OP_vbroadcastsd | IA-32/AMD64 vbroadcastsd opcode. |
| OP_vbroadcastf128 | IA-32/AMD64 vbroadcastf128 opcode. |
| OP_vmaskmovps | IA-32/AMD64 vmaskmovps opcode. |
| OP_vmaskmovpd | IA-32/AMD64 vmaskmovpd opcode. |
| OP_vpermilps | IA-32/AMD64 vpermilps opcode. |
| OP_vpermilpd | IA-32/AMD64 vpermilpd opcode. |
| OP_vperm2f128 | IA-32/AMD64 vperm2f128 opcode. |
| OP_vinsertf128 | IA-32/AMD64 vinsertf128 opcode. |
| OP_vextractf128 | IA-32/AMD64 vextractf128 opcode. |
| OP_vcvtph2ps | IA-32/AMD64 vcvtph2ps opcode. |
| OP_vcvtps2ph | IA-32/AMD64 vcvtps2ph opcode. |
| OP_vfmadd132ps | IA-32/AMD64 vfmadd132ps opcode. |
| OP_vfmadd132pd | IA-32/AMD64 vfmadd132pd opcode. |
| OP_vfmadd213ps | IA-32/AMD64 vfmadd213ps opcode. |
| OP_vfmadd213pd | IA-32/AMD64 vfmadd213pd opcode. |
| OP_vfmadd231ps | IA-32/AMD64 vfmadd231ps opcode. |
| OP_vfmadd231pd | IA-32/AMD64 vfmadd231pd opcode. |
| OP_vfmadd132ss | IA-32/AMD64 vfmadd132ss opcode. |
| OP_vfmadd132sd | IA-32/AMD64 vfmadd132sd opcode. |
| OP_vfmadd213ss | IA-32/AMD64 vfmadd213ss opcode. |
| OP_vfmadd213sd | IA-32/AMD64 vfmadd213sd opcode. |
| OP_vfmadd231ss | IA-32/AMD64 vfmadd231ss opcode. |
| OP_vfmadd231sd | IA-32/AMD64 vfmadd231sd opcode. |
| OP_vfmaddsub132ps | IA-32/AMD64 vfmaddsub132ps opcode. |
| OP_vfmaddsub132pd | IA-32/AMD64 vfmaddsub132pd opcode. |
| OP_vfmaddsub213ps | IA-32/AMD64 vfmaddsub213ps opcode. |
| OP_vfmaddsub213pd | IA-32/AMD64 vfmaddsub213pd opcode. |
| OP_vfmaddsub231ps | IA-32/AMD64 vfmaddsub231ps opcode. |
| OP_vfmaddsub231pd | IA-32/AMD64 vfmaddsub231pd opcode. |
| OP_vfmsubadd132ps | IA-32/AMD64 vfmsubadd132ps opcode. |
| OP_vfmsubadd132pd | IA-32/AMD64 vfmsubadd132pd opcode. |
| OP_vfmsubadd213ps | IA-32/AMD64 vfmsubadd213ps opcode. |
| OP_vfmsubadd213pd | IA-32/AMD64 vfmsubadd213pd opcode. |
| OP_vfmsubadd231ps | IA-32/AMD64 vfmsubadd231ps opcode. |
| OP_vfmsubadd231pd | IA-32/AMD64 vfmsubadd231pd opcode. |
| OP_vfmsub132ps | IA-32/AMD64 vfmsub132ps opcode. |
| OP_vfmsub132pd | IA-32/AMD64 vfmsub132pd opcode. |
| OP_vfmsub213ps | IA-32/AMD64 vfmsub213ps opcode. |
| OP_vfmsub213pd | IA-32/AMD64 vfmsub213pd opcode. |
| OP_vfmsub231ps | IA-32/AMD64 vfmsub231ps opcode. |
| OP_vfmsub231pd | IA-32/AMD64 vfmsub231pd opcode. |
| OP_vfmsub132ss | IA-32/AMD64 vfmsub132ss opcode. |
| OP_vfmsub132sd | IA-32/AMD64 vfmsub132sd opcode. |
| OP_vfmsub213ss | IA-32/AMD64 vfmsub213ss opcode. |
| OP_vfmsub213sd | IA-32/AMD64 vfmsub213sd opcode. |
| OP_vfmsub231ss | IA-32/AMD64 vfmsub231ss opcode. |
| OP_vfmsub231sd | IA-32/AMD64 vfmsub231sd opcode. |
| OP_vfnmadd132ps | IA-32/AMD64 vfnmadd132ps opcode. |
| OP_vfnmadd132pd | IA-32/AMD64 vfnmadd132pd opcode. |
| OP_vfnmadd213ps | IA-32/AMD64 vfnmadd213ps opcode. |
| OP_vfnmadd213pd | IA-32/AMD64 vfnmadd213pd opcode. |
| OP_vfnmadd231ps | IA-32/AMD64 vfnmadd231ps opcode. |
| OP_vfnmadd231pd | IA-32/AMD64 vfnmadd231pd opcode. |
| OP_vfnmadd132ss | IA-32/AMD64 vfnmadd132ss opcode. |
| OP_vfnmadd132sd | IA-32/AMD64 vfnmadd132sd opcode. |
| OP_vfnmadd213ss | IA-32/AMD64 vfnmadd213ss opcode. |
| OP_vfnmadd213sd | IA-32/AMD64 vfnmadd213sd opcode. |
| OP_vfnmadd231ss | IA-32/AMD64 vfnmadd231ss opcode. |
| OP_vfnmadd231sd | IA-32/AMD64 vfnmadd231sd opcode. |
| OP_vfnmsub132ps | IA-32/AMD64 vfnmsub132ps opcode. |
| OP_vfnmsub132pd | IA-32/AMD64 vfnmsub132pd opcode. |
| OP_vfnmsub213ps | IA-32/AMD64 vfnmsub213ps opcode. |
| OP_vfnmsub213pd | IA-32/AMD64 vfnmsub213pd opcode. |
| OP_vfnmsub231ps | IA-32/AMD64 vfnmsub231ps opcode. |
| OP_vfnmsub231pd | IA-32/AMD64 vfnmsub231pd opcode. |
| OP_vfnmsub132ss | IA-32/AMD64 vfnmsub132ss opcode. |
| OP_vfnmsub132sd | IA-32/AMD64 vfnmsub132sd opcode. |
| OP_vfnmsub213ss | IA-32/AMD64 vfnmsub213ss opcode. |
| OP_vfnmsub213sd | IA-32/AMD64 vfnmsub213sd opcode. |
| OP_vfnmsub231ss | IA-32/AMD64 vfnmsub231ss opcode. |
| OP_vfnmsub231sd | IA-32/AMD64 vfnmsub231sd opcode. |
| OP_movq2dq | IA-32/AMD64 movq2dq opcode. |
| OP_movdq2q | IA-32/AMD64 movdq2q opcode. |
| OP_fxsave64 | IA-32/AMD64 fxsave64 opcode. |
| OP_fxrstor64 | IA-32/AMD64 fxrstor64 opcode. |
| OP_xsave64 | IA-32/AMD64 xsave64 opcode. |
| OP_xrstor64 | IA-32/AMD64 xrstor64 opcode. |
| OP_xsaveopt64 | IA-32/AMD64 xsaveopt64 opcode. |
| OP_rdrand | IA-32/AMD64 rdrand opcode. |
| OP_rdfsbase | IA-32/AMD64 rdfsbase opcode. |
| OP_rdgsbase | IA-32/AMD64 rdgsbase opcode. |
| OP_wrfsbase | IA-32/AMD64 wrfsbase opcode. |
| OP_wrgsbase | IA-32/AMD64 wrgsbase opcode. |
| OP_rdseed | IA-32/AMD64 rdseed opcode. |
| OP_vfmaddsubps | IA-32/AMD64 vfmaddsubps opcode. |
| OP_vfmaddsubpd | IA-32/AMD64 vfmaddsubpd opcode. |
| OP_vfmsubaddps | IA-32/AMD64 vfmsubaddps opcode. |
| OP_vfmsubaddpd | IA-32/AMD64 vfmsubaddpd opcode. |
| OP_vfmaddps | IA-32/AMD64 vfmaddps opcode. |
| OP_vfmaddpd | IA-32/AMD64 vfmaddpd opcode. |
| OP_vfmaddss | IA-32/AMD64 vfmaddss opcode. |
| OP_vfmaddsd | IA-32/AMD64 vfmaddsd opcode. |
| OP_vfmsubps | IA-32/AMD64 vfmsubps opcode. |
| OP_vfmsubpd | IA-32/AMD64 vfmsubpd opcode. |
| OP_vfmsubss | IA-32/AMD64 vfmsubss opcode. |
| OP_vfmsubsd | IA-32/AMD64 vfmsubsd opcode. |
| OP_vfnmaddps | IA-32/AMD64 vfnmaddps opcode. |
| OP_vfnmaddpd | IA-32/AMD64 vfnmaddpd opcode. |
| OP_vfnmaddss | IA-32/AMD64 vfnmaddss opcode. |
| OP_vfnmaddsd | IA-32/AMD64 vfnmaddsd opcode. |
| OP_vfnmsubps | IA-32/AMD64 vfnmsubps opcode. |
| OP_vfnmsubpd | IA-32/AMD64 vfnmsubpd opcode. |
| OP_vfnmsubss | IA-32/AMD64 vfnmsubss opcode. |
| OP_vfnmsubsd | IA-32/AMD64 vfnmsubsd opcode. |
| OP_vfrczps | IA-32/AMD64 vfrczps opcode. |
| OP_vfrczpd | IA-32/AMD64 vfrczpd opcode. |
| OP_vfrczss | IA-32/AMD64 vfrczss opcode. |
| OP_vfrczsd | IA-32/AMD64 vfrczsd opcode. |
| OP_vpcmov | IA-32/AMD64 vpcmov opcode. |
| OP_vpcomb | IA-32/AMD64 vpcomb opcode. |
| OP_vpcomw | IA-32/AMD64 vpcomw opcode. |
| OP_vpcomd | IA-32/AMD64 vpcomd opcode. |
| OP_vpcomq | IA-32/AMD64 vpcomq opcode. |
| OP_vpcomub | IA-32/AMD64 vpcomub opcode. |
| OP_vpcomuw | IA-32/AMD64 vpcomuw opcode. |
| OP_vpcomud | IA-32/AMD64 vpcomud opcode. |
| OP_vpcomuq | IA-32/AMD64 vpcomuq opcode. |
| OP_vpermil2pd | IA-32/AMD64 vpermil2pd opcode. |
| OP_vpermil2ps | IA-32/AMD64 vpermil2ps opcode. |
| OP_vphaddbw | IA-32/AMD64 vphaddbw opcode. |
| OP_vphaddbd | IA-32/AMD64 vphaddbd opcode. |
| OP_vphaddbq | IA-32/AMD64 vphaddbq opcode. |
| OP_vphaddwd | IA-32/AMD64 vphaddwd opcode. |
| OP_vphaddwq | IA-32/AMD64 vphaddwq opcode. |
| OP_vphadddq | IA-32/AMD64 vphadddq opcode. |
| OP_vphaddubw | IA-32/AMD64 vphaddubw opcode. |
| OP_vphaddubd | IA-32/AMD64 vphaddubd opcode. |
| OP_vphaddubq | IA-32/AMD64 vphaddubq opcode. |
| OP_vphadduwd | IA-32/AMD64 vphadduwd opcode. |
| OP_vphadduwq | IA-32/AMD64 vphadduwq opcode. |
| OP_vphaddudq | IA-32/AMD64 vphaddudq opcode. |
| OP_vphsubbw | IA-32/AMD64 vphsubbw opcode. |
| OP_vphsubwd | IA-32/AMD64 vphsubwd opcode. |
| OP_vphsubdq | IA-32/AMD64 vphsubdq opcode. |
| OP_vpmacssww | IA-32/AMD64 vpmacssww opcode. |
| OP_vpmacsswd | IA-32/AMD64 vpmacsswd opcode. |
| OP_vpmacssdql | IA-32/AMD64 vpmacssdql opcode. |
| OP_vpmacssdd | IA-32/AMD64 vpmacssdd opcode. |
| OP_vpmacssdqh | IA-32/AMD64 vpmacssdqh opcode. |
| OP_vpmacsww | IA-32/AMD64 vpmacsww opcode. |
| OP_vpmacswd | IA-32/AMD64 vpmacswd opcode. |
| OP_vpmacsdql | IA-32/AMD64 vpmacsdql opcode. |
| OP_vpmacsdd | IA-32/AMD64 vpmacsdd opcode. |
| OP_vpmacsdqh | IA-32/AMD64 vpmacsdqh opcode. |
| OP_vpmadcsswd | IA-32/AMD64 vpmadcsswd opcode. |
| OP_vpmadcswd | IA-32/AMD64 vpmadcswd opcode. |
| OP_vpperm | IA-32/AMD64 vpperm opcode. |
| OP_vprotb | IA-32/AMD64 vprotb opcode. |
| OP_vprotw | IA-32/AMD64 vprotw opcode. |
| OP_vprotd | IA-32/AMD64 vprotd opcode. |
| OP_vprotq | IA-32/AMD64 vprotq opcode. |
| OP_vpshlb | IA-32/AMD64 vpshlb opcode. |
| OP_vpshlw | IA-32/AMD64 vpshlw opcode. |
| OP_vpshld | IA-32/AMD64 vpshld opcode. |
| OP_vpshlq | IA-32/AMD64 vpshlq opcode. |
| OP_vpshab | IA-32/AMD64 vpshab opcode. |
| OP_vpshaw | IA-32/AMD64 vpshaw opcode. |
| OP_vpshad | IA-32/AMD64 vpshad opcode. |
| OP_vpshaq | IA-32/AMD64 vpshaq opcode. |
| OP_bextr | IA-32/AMD64 bextr opcode. |
| OP_blcfill | IA-32/AMD64 blcfill opcode. |
| OP_blci | IA-32/AMD64 blci opcode. |
| OP_blcic | IA-32/AMD64 blcic opcode. |
| OP_blcmsk | IA-32/AMD64 blcmsk opcode. |
| OP_blcs | IA-32/AMD64 blcs opcode. |
| OP_blsfill | IA-32/AMD64 blsfill opcode. |
| OP_blsic | IA-32/AMD64 blsic opcode. |
| OP_t1mskc | IA-32/AMD64 t1mskc opcode. |
| OP_tzmsk | IA-32/AMD64 tzmsk opcode. |
| OP_llwpcb | IA-32/AMD64 llwpcb opcode. |
| OP_slwpcb | IA-32/AMD64 slwpcb opcode. |
| OP_lwpins | IA-32/AMD64 lwpins opcode. |
| OP_lwpval | IA-32/AMD64 lwpval opcode. |
| OP_andn | IA-32/AMD64 andn opcode. |
| OP_blsr | IA-32/AMD64 blsr opcode. |
| OP_blsmsk | IA-32/AMD64 blsmsk opcode. |
| OP_blsi | IA-32/AMD64 blsi opcode. |
| OP_tzcnt | IA-32/AMD64 tzcnt opcode. |
| OP_bzhi | IA-32/AMD64 bzhi opcode. |
| OP_pext | IA-32/AMD64 pext opcode. |
| OP_pdep | IA-32/AMD64 pdep opcode. |
| OP_sarx | IA-32/AMD64 sarx opcode. |
| OP_shlx | IA-32/AMD64 shlx opcode. |
| OP_shrx | IA-32/AMD64 shrx opcode. |
| OP_rorx | IA-32/AMD64 rorx opcode. |
| OP_mulx | IA-32/AMD64 mulx opcode. |
| OP_getsec | IA-32/AMD64 getsec opcode. |
| OP_vmfunc | IA-32/AMD64 vmfunc opcode. |
| OP_invpcid | IA-32/AMD64 invpcid opcode. |
| OP_xabort | IA-32/AMD64 xabort opcode. |
| OP_xbegin | IA-32/AMD64 xbegin opcode. |
| OP_xend | IA-32/AMD64 xend opcode. |
| OP_xtest | IA-32/AMD64 xtest opcode. |
| OP_vpgatherdd | IA-32/AMD64 vpgatherdd opcode. |
| OP_vpgatherdq | IA-32/AMD64 vpgatherdq opcode. |
| OP_vpgatherqd | IA-32/AMD64 vpgatherqd opcode. |
| OP_vpgatherqq | IA-32/AMD64 vpgatherqq opcode. |
| OP_vgatherdps | IA-32/AMD64 vgatherdps opcode. |
| OP_vgatherdpd | IA-32/AMD64 vgatherdpd opcode. |
| OP_vgatherqps | IA-32/AMD64 vgatherqps opcode. |
| OP_vgatherqpd | IA-32/AMD64 vgatherqpd opcode. |
| OP_vbroadcasti128 | IA-32/AMD64 vbroadcasti128 opcode. |
| OP_vinserti128 | IA-32/AMD64 vinserti128 opcode. |
| OP_vextracti128 | IA-32/AMD64 vextracti128 opcode. |
| OP_vpmaskmovd | IA-32/AMD64 vpmaskmovd opcode. |
| OP_vpmaskmovq | IA-32/AMD64 vpmaskmovq opcode. |
| OP_vperm2i128 | IA-32/AMD64 vperm2i128 opcode. |
| OP_vpermd | IA-32/AMD64 vpermd opcode. |
| OP_vpermps | IA-32/AMD64 vpermps opcode. |
| OP_vpermq | IA-32/AMD64 vpermq opcode. |
| OP_vpermpd | IA-32/AMD64 vpermpd opcode. |
| OP_vpblendd | IA-32/AMD64 vpblendd opcode. |
| OP_vpsllvd | IA-32/AMD64 vpsllvd opcode. |
| OP_vpsllvq | IA-32/AMD64 vpsllvq opcode. |
| OP_vpsravd | IA-32/AMD64 vpsravd opcode. |
| OP_vpsrlvd | IA-32/AMD64 vpsrlvd opcode. |
| OP_vpsrlvq | IA-32/AMD64 vpsrlvq opcode. |
| OP_vpbroadcastb | IA-32/AMD64 vpbroadcastb opcode. |
| OP_vpbroadcastw | IA-32/AMD64 vpbroadcastw opcode. |
| OP_vpbroadcastd | IA-32/AMD64 vpbroadcastd opcode. |
| OP_vpbroadcastq | IA-32/AMD64 vpbroadcastq opcode. |
| OP_xsavec32 | IA-32/AMD64 xsavec opcode. |
| OP_xsavec64 | IA-32/AMD64 xsavec64 opcode. |
| OP_adox | IA-32/AMD64 adox opcode. |
| OP_adcx | IA-32/AMD64 adox opcode. |
| OP_kmovw | IA-32/AMD64 AVX-512 kmovw opcode. |
| OP_kmovb | IA-32/AMD64 AVX-512 kmovb opcode. |
| OP_kmovq | IA-32/AMD64 AVX-512 kmovq opcode. |
| OP_kmovd | IA-32/AMD64 AVX-512 kmovd opcode. |
| OP_kandw | IA-32/AMD64 AVX-512 kandw opcode. |
| OP_kandb | IA-32/AMD64 AVX-512 kandb opcode. |
| OP_kandq | IA-32/AMD64 AVX-512 kandq opcode. |
| OP_kandd | IA-32/AMD64 AVX-512 kandd opcode. |
| OP_kandnw | IA-32/AMD64 AVX-512 kandnw opcode. |
| OP_kandnb | IA-32/AMD64 AVX-512 kandnb opcode. |
| OP_kandnq | IA-32/AMD64 AVX-512 kandnq opcode. |
| OP_kandnd | IA-32/AMD64 AVX-512 kandnd opcode. |
| OP_kunpckbw | IA-32/AMD64 AVX-512 kunpckbw opcode. |
| OP_kunpckwd | IA-32/AMD64 AVX-512 kunpckwd opcode. |
| OP_kunpckdq | IA-32/AMD64 AVX-512 kunpckdq opcode. |
| OP_knotw | IA-32/AMD64 AVX-512 knotw opcode. |
| OP_knotb | IA-32/AMD64 AVX-512 knotb opcode. |
| OP_knotq | IA-32/AMD64 AVX-512 knotq opcode. |
| OP_knotd | IA-32/AMD64 AVX-512 knotd opcode. |
| OP_korw | IA-32/AMD64 AVX-512 korw opcode. |
| OP_korb | IA-32/AMD64 AVX-512 korb opcode. |
| OP_korq | IA-32/AMD64 AVX-512 korq opcode. |
| OP_kord | IA-32/AMD64 AVX-512 kord opcode. |
| OP_kxnorw | IA-32/AMD64 AVX-512 kxnorw opcode. |
| OP_kxnorb | IA-32/AMD64 AVX-512 kxnorb opcode. |
| OP_kxnorq | IA-32/AMD64 AVX-512 kxnorq opcode. |
| OP_kxnord | IA-32/AMD64 AVX-512 kxnord opcode. |
| OP_kxorw | IA-32/AMD64 AVX-512 kxorw opcode. |
| OP_kxorb | IA-32/AMD64 AVX-512 kxorb opcode. |
| OP_kxorq | IA-32/AMD64 AVX-512 kxorq opcode. |
| OP_kxord | IA-32/AMD64 AVX-512 kxord opcode. |
| OP_kaddw | IA-32/AMD64 AVX-512 kaddw opcode. |
| OP_kaddb | IA-32/AMD64 AVX-512 kaddb opcode. |
| OP_kaddq | IA-32/AMD64 AVX-512 kaddq opcode. |
| OP_kaddd | IA-32/AMD64 AVX-512 kaddd opcode. |
| OP_kortestw | IA-32/AMD64 AVX-512 kortestw opcode. |
| OP_kortestb | IA-32/AMD64 AVX-512 kortestb opcode. |
| OP_kortestq | IA-32/AMD64 AVX-512 kortestq opcode. |
| OP_kortestd | IA-32/AMD64 AVX-512 kortestd opcode. |
| OP_kshiftlw | IA-32/AMD64 AVX-512 kshiftlw opcode. |
| OP_kshiftlb | IA-32/AMD64 AVX-512 kshiftlb opcode. |
| OP_kshiftlq | IA-32/AMD64 AVX-512 kshiftlq opcode. |
| OP_kshiftld | IA-32/AMD64 AVX-512 kshiftld opcode. |
| OP_kshiftrw | IA-32/AMD64 AVX-512 kshiftrw opcode. |
| OP_kshiftrb | IA-32/AMD64 AVX-512 kshiftrb opcode. |
| OP_kshiftrq | IA-32/AMD64 AVX-512 kshiftrq opcode. |
| OP_kshiftrd | IA-32/AMD64 AVX-512 kshiftrd opcode. |
| OP_ktestw | IA-32/AMD64 AVX-512 ktestd opcode. |
| OP_ktestb | IA-32/AMD64 AVX-512 ktestd opcode. |
| OP_ktestq | IA-32/AMD64 AVX-512 ktestd opcode. |
| OP_ktestd | IA-32/AMD64 AVX-512 ktestd opcode. |
| OP_valignd | IA-32/AMD64 AVX-512 OP_valignd opcode. |
| OP_valignq | IA-32/AMD64 AVX-512 OP_valignq opcode. |
| OP_vblendmpd | IA-32/AMD64 AVX-512 OP_vblendmpd opcode. |
| OP_vblendmps | IA-32/AMD64 AVX-512 OP_vblendmps opcode. |
| OP_vbroadcastf32x2 | IA-32/AMD64 AVX-512 OP_vbroadcastf32x2 opcode. |
| OP_vbroadcastf32x4 | IA-32/AMD64 AVX-512 OP_vbroadcastf32x4 opcode. |
| OP_vbroadcastf32x8 | IA-32/AMD64 AVX-512 OP_vbroadcastf32x8 opcode. |
| OP_vbroadcastf64x2 | IA-32/AMD64 AVX-512 OP_vbroadcastf64x2 opcode. |
| OP_vbroadcastf64x4 | IA-32/AMD64 AVX-512 OP_vbroadcastf64x4 opcode. |
| OP_vbroadcasti32x2 | IA-32/AMD64 AVX-512 OP_vbroadcasti32x2 opcode. |
| OP_vbroadcasti32x4 | IA-32/AMD64 AVX-512 OP_vbroadcasti32x4 opcode. |
| OP_vbroadcasti32x8 | IA-32/AMD64 AVX-512 OP_vbroadcasti32x8 opcode. |
| OP_vbroadcasti64x2 | IA-32/AMD64 AVX-512 OP_vbroadcasti64x2 opcode. |
| OP_vbroadcasti64x4 | IA-32/AMD64 AVX-512 OP_vbroadcasti64x4 opcode. |
| OP_vcompresspd | IA-32/AMD64 AVX-512 OP_vcompresspd opcode. |
| OP_vcompressps | IA-32/AMD64 AVX-512 OP_vcompressps opcode. |
| OP_vcvtpd2qq | IA-32/AMD64 AVX-512 OP_vcvtpd2qq opcode. |
| OP_vcvtpd2udq | IA-32/AMD64 AVX-512 OP_vcvtpd2udq opcode. |
| OP_vcvtpd2uqq | IA-32/AMD64 AVX-512 OP_vcvtpd2uqq opcode. |
| OP_vcvtps2qq | IA-32/AMD64 AVX-512 OP_vcvtps2qq opcode. |
| OP_vcvtps2udq | IA-32/AMD64 AVX-512 OP_vcvtps2udq opcode. |
| OP_vcvtps2uqq | IA-32/AMD64 AVX-512 OP_vcvtps2uqq opcode. |
| OP_vcvtqq2pd | IA-32/AMD64 AVX-512 OP_vcvtqq2pd opcode. |
| OP_vcvtqq2ps | IA-32/AMD64 AVX-512 OP_vcvtqq2ps opcode. |
| OP_vcvtsd2usi | IA-32/AMD64 AVX-512 OP_vcvtsd2usi opcode. |
| OP_vcvtss2usi | IA-32/AMD64 AVX-512 OP_vcvtss2usi opcode. |
| OP_vcvttpd2qq | IA-32/AMD64 AVX-512 OP_vcvttpd2qq opcode. |
| OP_vcvttpd2udq | IA-32/AMD64 AVX-512 OP_vcvttpd2udq opcode. |
| OP_vcvttpd2uqq | IA-32/AMD64 AVX-512 OP_vcvttpd2uqq opcode. |
| OP_vcvttps2qq | IA-32/AMD64 AVX-512 OP_vcvttps2qq opcode. |
| OP_vcvttps2udq | IA-32/AMD64 AVX-512 OP_vcvttps2udq opcode. |
| OP_vcvttps2uqq | IA-32/AMD64 AVX-512 OP_vcvttps2uqq opcode. |
| OP_vcvttsd2usi | IA-32/AMD64 AVX-512 OP_vcvttsd2usi opcode. |
| OP_vcvttss2usi | IA-32/AMD64 AVX-512 OP_vcvttss2usi opcode. |
| OP_vcvtudq2pd | IA-32/AMD64 AVX-512 OP_vcvtudq2pd opcode. |
| OP_vcvtudq2ps | IA-32/AMD64 AVX-512 OP_vcvtudq2ps opcode. |
| OP_vcvtuqq2pd | IA-32/AMD64 AVX-512 OP_vcvtuqq2pd opcode. |
| OP_vcvtuqq2ps | IA-32/AMD64 AVX-512 OP_vcvtuqq2ps opcode. |
| OP_vcvtusi2sd | IA-32/AMD64 AVX-512 OP_vcvtusi2sd opcode. |
| OP_vcvtusi2ss | IA-32/AMD64 AVX-512 OP_vcvtusi2ss opcode. |
| OP_vdbpsadbw | IA-32/AMD64 AVX-512 OP_vdbpsadbw opcode. |
| OP_vexp2pd | IA-32/AMD64 AVX-512 OP_vexp2pd opcode. |
| OP_vexp2ps | IA-32/AMD64 AVX-512 OP_vexp2ps opcode. |
| OP_vexpandpd | IA-32/AMD64 AVX-512 OP_vexpandpd opcode. |
| OP_vexpandps | IA-32/AMD64 AVX-512 OP_vexpandps opcode. |
| OP_vextractf32x4 | IA-32/AMD64 AVX-512 OP_vextractf32x4 opcode. |
| OP_vextractf32x8 | IA-32/AMD64 AVX-512 OP_vextractf32x8 opcode. |
| OP_vextractf64x2 | IA-32/AMD64 AVX-512 OP_vextractf64x2 opcode. |
| OP_vextractf64x4 | IA-32/AMD64 AVX-512 OP_vextractf64x4 opcode. |
| OP_vextracti32x4 | IA-32/AMD64 AVX-512 OP_vextracti32x4 opcode. |
| OP_vextracti32x8 | IA-32/AMD64 AVX-512 OP_vextracti32x8 opcode. |
| OP_vextracti64x2 | IA-32/AMD64 AVX-512 OP_vextracti64x2 opcode. |
| OP_vextracti64x4 | IA-32/AMD64 AVX-512 OP_vextracti64x4 opcode. |
| OP_vfixupimmpd | IA-32/AMD64 AVX-512 OP_vfixupimmpd opcode. |
| OP_vfixupimmps | IA-32/AMD64 AVX-512 OP_vfixupimmps opcode. |
| OP_vfixupimmsd | IA-32/AMD64 AVX-512 OP_vfixupimmsd opcode. |
| OP_vfixupimmss | IA-32/AMD64 AVX-512 OP_vfixupimmss opcode. |
| OP_vfpclasspd | IA-32/AMD64 AVX-512 OP_vfpclasspd opcode. |
| OP_vfpclassps | IA-32/AMD64 AVX-512 OP_vfpclassps opcode. |
| OP_vfpclasssd | IA-32/AMD64 AVX-512 OP_vfpclasssd opcode. |
| OP_vfpclassss | IA-32/AMD64 AVX-512 OP_vfpclassss opcode. |
| OP_vgatherpf0dpd | IA-32/AMD64 AVX-512 OP_vgatherpf0dps opcode. |
| OP_vgatherpf0dps | IA-32/AMD64 AVX-512 OP_vgatherpf0dps opcode. |
| OP_vgatherpf0qpd | IA-32/AMD64 AVX-512 OP_vgatherpf0qpd opcode. |
| OP_vgatherpf0qps | IA-32/AMD64 AVX-512 OP_vgatherpf0qps opcode. |
| OP_vgatherpf1dpd | IA-32/AMD64 AVX-512 OP_vgatherpf1dpd opcode. |
| OP_vgatherpf1dps | IA-32/AMD64 AVX-512 OP_vgatherpf1dps opcode. |
| OP_vgatherpf1qpd | IA-32/AMD64 AVX-512 OP_vgatherpf1qpd opcode. |
| OP_vgatherpf1qps | IA-32/AMD64 AVX-512 OP_vgatherpf1qps opcode. |
| OP_vgetexppd | IA-32/AMD64 AVX-512 OP_vgetexppd opcode. |
| OP_vgetexpps | IA-32/AMD64 AVX-512 OP_vgetexpps opcode. |
| OP_vgetexpsd | IA-32/AMD64 AVX-512 OP_vgetexpsd opcode. |
| OP_vgetexpss | IA-32/AMD64 AVX-512 OP_vgetexpss opcode. |
| OP_vgetmantpd | IA-32/AMD64 AVX-512 OP_vgetmantpd opcode. |
| OP_vgetmantps | IA-32/AMD64 AVX-512 OP_vgetmantps opcode. |
| OP_vgetmantsd | IA-32/AMD64 AVX-512 OP_vgetmantsd opcode. |
| OP_vgetmantss | IA-32/AMD64 AVX-512 OP_vgetmantss opcode. |
| OP_vinsertf32x4 | IA-32/AMD64 AVX-512 OP_vinsertf32x4 opcode. |
| OP_vinsertf32x8 | IA-32/AMD64 AVX-512 OP_vinsertf32x8 opcode. |
| OP_vinsertf64x2 | IA-32/AMD64 AVX-512 OP_vinsertf64x2 opcode. |
| OP_vinsertf64x4 | IA-32/AMD64 AVX-512 OP_vinsertf64x4 opcode. |
| OP_vinserti32x4 | IA-32/AMD64 AVX-512 OP_vinserti32x4 opcode. |
| OP_vinserti32x8 | IA-32/AMD64 AVX-512 OP_vinserti32x8 opcode. |
| OP_vinserti64x2 | IA-32/AMD64 AVX-512 OP_vinserti64x2 opcode. |
| OP_vinserti64x4 | IA-32/AMD64 AVX-512 OP_vinserti64x4 opcode. |
| OP_vmovdqa32 | IA-32/AMD64 AVX-512 OP_vmovdqa32 opcode. |
| OP_vmovdqa64 | IA-32/AMD64 AVX-512 OP_vmovdqa64 opcode. |
| OP_vmovdqu16 | IA-32/AMD64 AVX-512 OP_vmovdqu16 opcode. |
| OP_vmovdqu32 | IA-32/AMD64 AVX-512 OP_vmovdqu32 opcode. |
| OP_vmovdqu64 | IA-32/AMD64 AVX-512 OP_vmovdqu64 opcode. |
| OP_vmovdqu8 | IA-32/AMD64 AVX-512 OP_vmovdqu8 opcode. |
| OP_vpabsq | IA-32/AMD64 AVX-512 OP_vpabsq opcode. |
| OP_vpandd | IA-32/AMD64 AVX-512 OP_vpandd opcode. |
| OP_vpandnd | IA-32/AMD64 AVX-512 OP_vpandnd opcode. |
| OP_vpandnq | IA-32/AMD64 AVX-512 OP_vpandnq opcode. |
| OP_vpandq | IA-32/AMD64 AVX-512 OP_vpandq opcode. |
| OP_vpblendmb | IA-32/AMD64 AVX-512 OP_vpblendmb opcode. |
| OP_vpblendmd | IA-32/AMD64 AVX-512 OP_vpblendmd opcode. |
| OP_vpblendmq | IA-32/AMD64 AVX-512 OP_vpblendmq opcode. |
| OP_vpblendmw | IA-32/AMD64 AVX-512 OP_vpblendmw opcode. |
| OP_vpbroadcastmb2q | IA-32/AMD64 AVX-512 OP_vpbroadcastmb2q opcode. |
| OP_vpbroadcastmw2d | IA-32/AMD64 AVX-512 OP_vpbroadcastmw2d opcode. |
| OP_vpcmpb | IA-32/AMD64 AVX-512 OP_vpcmpb opcode. |
| OP_vpcmpd | IA-32/AMD64 AVX-512 OP_vpcmpd opcode. |
| OP_vpcmpq | IA-32/AMD64 AVX-512 OP_vpcmpq opcode. |
| OP_vpcmpub | IA-32/AMD64 AVX-512 OP_vpcmpub opcode. |
| OP_vpcmpud | IA-32/AMD64 AVX-512 OP_vpcmpud opcode. |
| OP_vpcmpuq | IA-32/AMD64 AVX-512 OP_vpcmpuq opcode. |
| OP_vpcmpuw | IA-32/AMD64 AVX-512 OP_vpcmpuw opcode. |
| OP_vpcmpw | IA-32/AMD64 AVX-512 OP_vpcmpw opcode. |
| OP_vpcompressd | IA-32/AMD64 AVX-512 OP_vpcompressd opcode. |
| OP_vpcompressq | IA-32/AMD64 AVX-512 OP_vpcompressq opcode. |
| OP_vpconflictd | IA-32/AMD64 AVX-512 OP_vpconflictd opcode. |
| OP_vpconflictq | IA-32/AMD64 AVX-512 OP_vpconflictq opcode. |
| OP_vpermb | IA-32/AMD64 AVX-512 OP_vpermb opcode. |
| OP_vpermi2b | IA-32/AMD64 AVX-512 OP_vpermi2b opcode. |
| OP_vpermi2d | IA-32/AMD64 AVX-512 OP_vpermi2d opcode. |
| OP_vpermi2pd | IA-32/AMD64 AVX-512 OP_vpermi2pd opcode. |
| OP_vpermi2ps | IA-32/AMD64 AVX-512 OP_vpermi2ps opcode. |
| OP_vpermi2q | IA-32/AMD64 AVX-512 OP_vpermi2q opcode. |
| OP_vpermi2w | IA-32/AMD64 AVX-512 OP_vpermi2w opcode. |
| OP_vpermt2b | IA-32/AMD64 AVX-512 OP_vpermt2b opcode. |
| OP_vpermt2d | IA-32/AMD64 AVX-512 OP_vpermt2d opcode. |
| OP_vpermt2pd | IA-32/AMD64 AVX-512 OP_vpermt2pd opcode. |
| OP_vpermt2ps | IA-32/AMD64 AVX-512 OP_vpermt2ps opcode. |
| OP_vpermt2q | IA-32/AMD64 AVX-512 OP_vpermt2q opcode. |
| OP_vpermt2w | IA-32/AMD64 AVX-512 OP_vpermt2w opcode. |
| OP_vpermw | IA-32/AMD64 AVX-512 OP_vpermw opcode. |
| OP_vpexpandd | IA-32/AMD64 AVX-512 OP_vpexpandd opcode. |
| OP_vpexpandq | IA-32/AMD64 AVX-512 OP_vpexpandq opcode. |
| OP_vpextrq | IA-32/AMD64 AVX-512 OP_vpextrq opcode. |
| OP_vpinsrq | IA-32/AMD64 AVX-512 OP_vpinsrq opcode. |
| OP_vplzcntd | IA-32/AMD64 AVX-512 OP_vplzcntd opcode. |
| OP_vplzcntq | IA-32/AMD64 AVX-512 OP_vplzcntq opcode. |
| OP_vpmadd52huq | IA-32/AMD64 AVX-512 OP_vpmadd52huq opcode. |
| OP_vpmadd52luq | IA-32/AMD64 AVX-512 OP_vpmadd52luq opcode. |
| OP_vpmaxsq | IA-32/AMD64 AVX-512 OP_vpmaxsq opcode. |
| OP_vpmaxuq | IA-32/AMD64 AVX-512 OP_vpmaxuq opcode. |
| OP_vpminsq | IA-32/AMD64 AVX-512 OP_vpminsq opcode. |
| OP_vpminuq | IA-32/AMD64 AVX-512 OP_vpminuq opcode. |
| OP_vpmovb2m | IA-32/AMD64 AVX-512 OP_vpmovb2m opcode. |
| OP_vpmovd2m | IA-32/AMD64 AVX-512 OP_vpmovd2m opcode. |
| OP_vpmovdb | IA-32/AMD64 AVX-512 OP_vpmovdb opcode. |
| OP_vpmovdw | IA-32/AMD64 AVX-512 OP_vpmovdw opcode. |
| OP_vpmovm2b | IA-32/AMD64 AVX-512 OP_vpmovm2b opcode. |
| OP_vpmovm2d | IA-32/AMD64 AVX-512 OP_vpmovm2d opcode. |
| OP_vpmovm2q | IA-32/AMD64 AVX-512 OP_vpmovm2q opcode. |
| OP_vpmovm2w | IA-32/AMD64 AVX-512 OP_vpmovm2w opcode. |
| OP_vpmovq2m | IA-32/AMD64 AVX-512 OP_vpmovq2m opcode. |
| OP_vpmovqb | IA-32/AMD64 AVX-512 OP_vpmovqb opcode. |
| OP_vpmovqd | IA-32/AMD64 AVX-512 OP_vpmovqd opcode. |
| OP_vpmovqw | IA-32/AMD64 AVX-512 OP_vpmovqw opcode. |
| OP_vpmovsdb | IA-32/AMD64 AVX-512 OP_vpmovsdb opcode. |
| OP_vpmovsdw | IA-32/AMD64 AVX-512 OP_vpmovsdw opcode. |
| OP_vpmovsqb | IA-32/AMD64 AVX-512 OP_vpmovsqb opcode. |
| OP_vpmovsqd | IA-32/AMD64 AVX-512 OP_vpmovsqd opcode. |
| OP_vpmovsqw | IA-32/AMD64 AVX-512 OP_vpmovsqw opcode. |
| OP_vpmovswb | IA-32/AMD64 AVX-512 OP_vpmovswb opcode. |
| OP_vpmovusdb | IA-32/AMD64 AVX-512 OP_vpmovusdb opcode. |
| OP_vpmovusdw | IA-32/AMD64 AVX-512 OP_vpmovusdw opcode. |
| OP_vpmovusqb | IA-32/AMD64 AVX-512 OP_vpmovusqb opcode. |
| OP_vpmovusqd | IA-32/AMD64 AVX-512 OP_vpmovusqd opcode. |
| OP_vpmovusqw | IA-32/AMD64 AVX-512 OP_vpmovusqw opcode. |
| OP_vpmovuswb | IA-32/AMD64 AVX-512 OP_vpmovuswb opcode. |
| OP_vpmovw2m | IA-32/AMD64 AVX-512 OP_vpmovw2m opcode. |
| OP_vpmovwb | IA-32/AMD64 AVX-512 OP_vpmovwb opcode. |
| OP_vpmullq | IA-32/AMD64 AVX-512 OP_vpmullq opcode. |
| OP_vpord | IA-32/AMD64 AVX-512 OP_vpord opcode. |
| OP_vporq | IA-32/AMD64 AVX-512 OP_vporq opcode. |
| OP_vprold | IA-32/AMD64 AVX-512 OP_vprold opcode. |
| OP_vprolq | IA-32/AMD64 AVX-512 OP_vprolq opcode. |
| OP_vprolvd | IA-32/AMD64 AVX-512 OP_vprolvd opcode. |
| OP_vprolvq | IA-32/AMD64 AVX-512 OP_vprolvq opcode. |
| OP_vprord | IA-32/AMD64 AVX-512 OP_vprord opcode. |
| OP_vprorq | IA-32/AMD64 AVX-512 OP_vprorq opcode. |
| OP_vprorvd | IA-32/AMD64 AVX-512 OP_vprorvd opcode. |
| OP_vprorvq | IA-32/AMD64 AVX-512 OP_vprorvq opcode. |
| OP_vpscatterdd | IA-32/AMD64 AVX-512 OP_vpscatterdd opcode. |
| OP_vpscatterdq | IA-32/AMD64 AVX-512 OP_vpscatterdq opcode. |
| OP_vpscatterqd | IA-32/AMD64 AVX-512 OP_vpscatterqd opcode. |
| OP_vpscatterqq | IA-32/AMD64 AVX-512 OP_vpscatterqq opcode. |
| OP_vpsllvw | IA-32/AMD64 AVX-512 OP_vpsllvw opcode. |
| OP_vpsraq | IA-32/AMD64 AVX-512 OP_vpsraq opcode. |
| OP_vpsravq | IA-32/AMD64 AVX-512 OP_vpsravq opcode. |
| OP_vpsravw | IA-32/AMD64 AVX-512 OP_vpsravw opcode. |
| OP_vpsrlvw | IA-32/AMD64 AVX-512 OP_vpsrlvw opcode. |
| OP_vpternlogd | IA-32/AMD64 AVX-512 OP_vpternlogd opcode. |
| OP_vpternlogq | IA-32/AMD64 AVX-512 OP_vpternlogd opcode. |
| OP_vptestmb | IA-32/AMD64 AVX-512 OP_vptestmb opcode. |
| OP_vptestmd | IA-32/AMD64 AVX-512 OP_vptestmd opcode. |
| OP_vptestmq | IA-32/AMD64 AVX-512 OP_vptestmq opcode. |
| OP_vptestmw | IA-32/AMD64 AVX-512 OP_vptestmw opcode. |
| OP_vptestnmb | IA-32/AMD64 AVX-512 OP_vptestnmb opcode. |
| OP_vptestnmd | IA-32/AMD64 AVX-512 OP_vptestnmd opcode. |
| OP_vptestnmq | IA-32/AMD64 AVX-512 OP_vptestnmq opcode. |
| OP_vptestnmw | IA-32/AMD64 AVX-512 OP_vptestnmw opcode. |
| OP_vpxord | IA-32/AMD64 AVX-512 OP_vpxordvpxord opcode. |
| OP_vpxorq | IA-32/AMD64 AVX-512 OP_vpxorq opcode. |
| OP_vrangepd | IA-32/AMD64 AVX-512 OP_vrangepd opcode. |
| OP_vrangeps | IA-32/AMD64 AVX-512 OP_vrangeps opcode. |
| OP_vrangesd | IA-32/AMD64 AVX-512 OP_vrangesd opcode. |
| OP_vrangess | IA-32/AMD64 AVX-512 OP_vrangess opcode. |
| OP_vrcp14pd | IA-32/AMD64 AVX-512 OP_vrcp14pd opcode. |
| OP_vrcp14ps | IA-32/AMD64 AVX-512 OP_vrcp14ps opcode. |
| OP_vrcp14sd | IA-32/AMD64 AVX-512 OP_vrcp14sd opcode. |
| OP_vrcp14ss | IA-32/AMD64 AVX-512 OP_vrcp14ss opcode. |
| OP_vrcp28pd | IA-32/AMD64 AVX-512 OP_vrcp28pd opcode. |
| OP_vrcp28ps | IA-32/AMD64 AVX-512 OP_vrcp28ps opcode. |
| OP_vrcp28sd | IA-32/AMD64 AVX-512 OP_vrcp28sd opcode. |
| OP_vrcp28ss | IA-32/AMD64 AVX-512 OP_vrcp28ss opcode. |
| OP_vreducepd | IA-32/AMD64 AVX-512 OP_vreducepd opcode. |
| OP_vreduceps | IA-32/AMD64 AVX-512 OP_vreduceps opcode. |
| OP_vreducesd | IA-32/AMD64 AVX-512 OP_vreducesd opcode. |
| OP_vreducess | IA-32/AMD64 AVX-512 OP_vreducess opcode. |
| OP_vrndscalepd | IA-32/AMD64 AVX-512 OP_vrndscalepd opcode. |
| OP_vrndscaleps | IA-32/AMD64 AVX-512 OP_vrndscaleps opcode. |
| OP_vrndscalesd | IA-32/AMD64 AVX-512 OP_vrndscalesd opcode. |
| OP_vrndscaless | IA-32/AMD64 AVX-512 OP_vrndscaless opcode. |
| OP_vrsqrt14pd | IA-32/AMD64 AVX-512 OP_vrsqrt14pd opcode. |
| OP_vrsqrt14ps | IA-32/AMD64 AVX-512 OP_vrsqrt14ps opcode. |
| OP_vrsqrt14sd | IA-32/AMD64 AVX-512 OP_vrsqrt14sd opcode. |
| OP_vrsqrt14ss | IA-32/AMD64 AVX-512 OP_vrsqrt14ss opcode. |
| OP_vrsqrt28pd | IA-32/AMD64 AVX-512 OP_vrsqrt28pd opcode. |
| OP_vrsqrt28ps | IA-32/AMD64 AVX-512 OP_vrsqrt28ps opcode. |
| OP_vrsqrt28sd | IA-32/AMD64 AVX-512 OP_vrsqrt28sd opcode. |
| OP_vrsqrt28ss | IA-32/AMD64 AVX-512 OP_vrsqrt28ss opcode. |
| OP_vscalefpd | IA-32/AMD64 AVX-512 OP_vscalepd opcode. |
| OP_vscalefps | IA-32/AMD64 AVX-512 OP_vscaleps opcode. |
| OP_vscalefsd | IA-32/AMD64 AVX-512 OP_vscalesd opcode. |
| OP_vscalefss | IA-32/AMD64 AVX-512 OP_vscalesss opcode. |
| OP_vscatterdpd | IA-32/AMD64 AVX-512 OP_vscatterdpd opcode. |
| OP_vscatterdps | IA-32/AMD64 AVX-512 OP_vscatterdps opcode. |
| OP_vscatterqpd | IA-32/AMD64 AVX-512 OP_vscatterqpd opcode. |
| OP_vscatterqps | IA-32/AMD64 AVX-512 OP_vscatterqps opcode. |
| OP_vscatterpf0dpd | IA-32/AMD64 AVX-512 OP_vscatterpf0dpd opcode. |
| OP_vscatterpf0dps | IA-32/AMD64 AVX-512 OP_vscatterpf0dps opcode. |
| OP_vscatterpf0qpd | IA-32/AMD64 AVX-512 OP_vscatterpf0qpd opcode. |
| OP_vscatterpf0qps | IA-32/AMD64 AVX-512 OP_vscatterpf0qps opcode. |
| OP_vscatterpf1dpd | IA-32/AMD64 AVX-512 OP_vscatterpf1dpd opcode. |
| OP_vscatterpf1dps | IA-32/AMD64 AVX-512 OP_vscatterpf1dps opcode. |
| OP_vscatterpf1qpd | IA-32/AMD64 AVX-512 OP_vscatterpf1qpd opcode. |
| OP_vscatterpf1qps | IA-32/AMD64 AVX-512 OP_vscatterpf1qps opcode. |
| OP_vshuff32x4 | IA-32/AMD64 AVX-512 OP_vshuff32x4 opcode. |
| OP_vshuff64x2 | IA-32/AMD64 AVX-512 OP_vshuff64x2 opcode. |
| OP_vshufi32x4 | IA-32/AMD64 AVX-512 OP_vshufi32x4 opcode. |
| OP_vshufi64x2 | IA-32/AMD64 AVX-512 OP_vshufi64x2 opcode. |
| OP_sha1msg1 | IA-32/AMD64 SHA OP_sha1msg1 opcode. |
| OP_sha1msg2 | IA-32/AMD64 SHA OP_sha1msg2 opcode. |
| OP_sha1nexte | IA-32/AMD64 SHA OP_sha1nexte opcode. |
| OP_sha1rnds4 | IA-32/AMD64 SHA OP_sha1rnds4 opcode. |
| OP_sha256msg1 | IA-32/AMD64 SHA OP_sha2msg1 opcode. |
| OP_sha256msg2 | IA-32/AMD64 SHA OP_sha2msg2 opcode. |
| OP_sha256rnds2 | IA-32/AMD64 SHA OP_sha2rnds2 opcode. |
| OP_bndcl | IA-32/AMD64 MPX OP_bndcl opcode. |
| OP_bndcn | IA-32/AMD64 MPX OP_bndcn opcode. |
| OP_bndcu | IA-32/AMD64 MPX OP_bndcu opcode. |
| OP_bndldx | IA-32/AMD64 MPX OP_bndldx opcode. |
| OP_bndmk | IA-32/AMD64 MPX OP_bndmk opcode. |
| OP_bndmov | IA-32/AMD64 MPX OP_bndmov opcode. |
| OP_bndstx | IA-32/AMD64 MPX OP_bndstx opcode. |
| OP_ptwrite | IA-32/AMD64 PT OP_ptwrite opcode. |
| OP_monitorx | AMD64 monitorx opcode. |
| OP_mwaitx | AMD64 mwaitx opcode. |
| OP_rdpkru | IA-32/AMD64 MPK rdpkru opcode. |
| OP_wrpkru | IA-32/AMD64 MPK wrpkru opcode. |
| OP_encls | IA-32/AMD64 SGX encls opcode. |
| OP_enclu | IA-32/AMD64 SGX enclu opcode. |
| OP_enclv | IA-32/AMD64 SGX enclv opcode. |
| OP_vpdpbusd | IA-32/AMD64 vpdpbusd opcode. |
| OP_vpdpbusds | IA-32/AMD64 vpdpbusds opcode. |
| OP_vpdpwssd | IA-32/AMD64 vpdpwssd opcode. |
| OP_vpdpwssds | IA-32/AMD64 vpdpwssds opcode. |
| OP_vcvtne2ps2bf16 | IA-32/AMD64 vcvtne2ps2bf16 opcode. |
| OP_vcvtneps2bf16 | IA-32/AMD64 vcvtneps2bf16 opcode. |
| OP_vdpbf16ps | IA-32/AMD64 vdpbf16ps opcode. |
| OP_FIRST | First real opcode. |
| OP_LAST | Last real opcode. |
| OPSZ_NA | Sentinel value: not a valid size. |
| OPSZ_0 | 0 bytes, for "sizeless" operands (for Intel, code 'm': used for both start addresses (lea, invlpg) and implicit constants (rol, fldl2e, etc.) |
| OPSZ_1 | 1 byte (for Intel, code 'b') |
| OPSZ_2 | 2 bytes (for Intel, code 'w') |
| OPSZ_4 | 4 bytes (for Intel, code 'd','si') |
| OPSZ_6 | 6 bytes (for Intel, code 'p','s') |
| OPSZ_8 | 8 bytes (for Intel, code 'q','pi') |
| OPSZ_10 | Intel 's' 64-bit, or double extended precision floating point (latter used by fld, fstp, fbld, fbstp) |
| OPSZ_16 | 16 bytes (for Intel, code 'dq','ps','pd','ss','sd', or AMD 'o') |
| OPSZ_14 | FPU operating environment with short data size (fldenv, fnstenv) |
| OPSZ_28 | FPU operating environment with normal data size (fldenv, fnstenv) |
| OPSZ_94 | FPU state with short data size (fnsave, frstor) |
| OPSZ_108 | FPU state with normal data size (fnsave, frstor) |
| OPSZ_512 | FPU, MMX, XMM state (fxsave, fxrstor) |
| OPSZ_2_short1 | The following sizes (OPSZ_*_short*) vary according to the cs segment and the operand size prefix. This IR assumes that the cs segment is set to the default operand size. The operand size prefix then functions to shrink the size. The IR does not explicitly mark the prefix; rather, a shortened size is requested in the operands themselves, with the IR adding the prefix at encode time. Normally the fixed sizes above should be used rather than these variable sizes, which are used internally by the IR and should only be externally specified when building an operand in order to be flexible and allow other operands to decide the size for the instruction (the prefix applies to the entire instruction). Intel 'c': 2/1 bytes ("2/1" means 2 bytes normally, but if another operand requests a short size then this size can accommodate by shifting to its short size, which is 1 byte). |
| OPSZ_4_short2 | Intel 'z': 4/2 bytes |
| OPSZ_4_rex8_short2 | Intel 'v': 8/4/2 bytes |
| OPSZ_4_rex8 | Intel 'd/q' (like 'v' but never 2 bytes) or 'y'. |
| OPSZ_6_irex10_short4 | Intel 'p': On Intel processors this is 10/6/4 bytes for segment selector + address. On AMD processors this is 6/4 bytes for segment selector + address (rex is ignored). |
| OPSZ_8_short2 | partially resolved 4x8_short2 |
| OPSZ_8_short4 | Intel 'a': pair of 4_short2 (bound) |
| OPSZ_28_short14 | FPU operating env variable data size (fldenv, fnstenv) |
| OPSZ_108_short94 | FPU state with variable data size (fnsave, frstor) |
| OPSZ_4x8 | Varies by 32-bit versus 64-bit processor mode. Full register size with no variation by prefix. Used for control and debug register moves and for Intel MPX. |
| OPSZ_6x10 | Intel 's': 6-byte (10-byte for 64-bit mode) table base + limit |
| OPSZ_4x8_short2 | Stack operands not only vary by operand size specifications but also by 32-bit versus 64-bit processor mode. Intel 'v'/'d64' for stack operations. Also 64-bit address-size specified operands, which are short4 rather than short2 in 64-bit mode (but short2 in 32-bit mode). Note that this IR does not distinguish extra stack operations performed by OP_enter w/ non-zero immed. |
| OPSZ_4x8_short2xi8 | Intel 'f64': 4_short2 for 32-bit, 8_short2 for 64-bit AMD, always 8 for 64-bit Intel |
| OPSZ_4_short2xi4 | Intel 'f64': 4_short2 for 32-bit or 64-bit AMD, always 4 for 64-bit Intel |
| OPSZ_1_reg4 | The following 3 sizes differ based on whether the modrm chooses a register or memory. Intel Rd/Mb: zero-extends if reg; used by pextrb |
| OPSZ_2_reg4 | Intel Rd/Mw: zero-extends if reg; used by pextrw |
| OPSZ_4_reg16 | Intel Udq/Md: 4 bytes of xmm or 4 bytes of memory; used by insertps. |
| OPSZ_xsave | Size is > 512 bytes: use cpuid to determine. Used for FPU, MMX, XMM, etc. state by xsave and xrstor. |
| OPSZ_12 | 12 bytes: 32-bit iret |
| OPSZ_32 | 32 bytes: pusha/popa Also Intel 'qq','pd','ps','x': 32 bytes (256 bits) |
| OPSZ_40 | 40 bytes: 64-bit iret |
| OPSZ_32_short16 | unresolved pusha/popa |
| OPSZ_8_rex16 | cmpxcgh8b/cmpxchg16b |
| OPSZ_8_rex16_short4 | Intel 'v' * 2 (far call/ret) |
| OPSZ_12_rex40_short6 | unresolved iret |
| OPSZ_16_vex32 | 16 or 32 bytes depending on VEX.L (AMD/Intel 'x'). |
| OPSZ_15 | All but one byte of an xmm register (used by OP_vpinsrb). |
| OPSZ_3 | 3 bytes |
| OPSZ_1b | 1 bit |
| OPSZ_2b | 2 bits |
| OPSZ_3b | 3 bits |
| OPSZ_4b | 4 bits |
| OPSZ_5b | 5 bits |
| OPSZ_6b | 6 bits |
| OPSZ_7b | 7 bits |
| OPSZ_9b | 9 bits |
| OPSZ_10b | 10 bits |
| OPSZ_11b | 11 bits |
| OPSZ_12b | 12 bits |
| OPSZ_20b | 20 bits |
| OPSZ_25b | 25 bits |
| OPSZ_VAR_REGLIST | At encode or decode time, the size will match the size of the register list operand in the containing instruction's operands. |
| OPSZ_20 | 20 bytes. Needed for load/store of register lists. |
| OPSZ_24 | 24 bytes. Needed for load/store of register lists. |
| OPSZ_36 | 36 bytes. Needed for load/store of register lists. |
| OPSZ_44 | 44 bytes. Needed for load/store of register lists. |
| OPSZ_48 | 48 bytes. Needed for load/store of register lists. |
| OPSZ_52 | 52 bytes. Needed for load/store of register lists. |
| OPSZ_56 | 56 bytes. Needed for load/store of register lists. |
| OPSZ_60 | 60 bytes. Needed for load/store of register lists. |
| OPSZ_64 | 64 bytes. Needed for load/store of register lists. Also Intel: 64 bytes (512 bits) |
| OPSZ_68 | 68 bytes. Needed for load/store of register lists. |
| OPSZ_72 | 72 bytes. Needed for load/store of register lists. |
| OPSZ_76 | 76 bytes. Needed for load/store of register lists. |
| OPSZ_80 | 80 bytes. Needed for load/store of register lists. |
| OPSZ_84 | 84 bytes. Needed for load/store of register lists. |
| OPSZ_88 | 88 bytes. Needed for load/store of register lists. |
| OPSZ_92 | 92 bytes. Needed for load/store of register lists. |
| OPSZ_96 | 96 bytes. Needed for load/store of register lists. |
| OPSZ_100 | 100 bytes. Needed for load/store of register lists. |
| OPSZ_104 | 104 bytes. Needed for load/store of register lists. |
| OPSZ_112 | 112 bytes. Needed for load/store of register lists. |
| OPSZ_116 | 116 bytes. Needed for load/store of register lists. |
| OPSZ_120 | 120 bytes. Needed for load/store of register lists. |
| OPSZ_124 | 124 bytes. Needed for load/store of register lists. |
| OPSZ_128 | 128 bytes. Needed for load/store of register lists. |
| OPSZ_SCALABLE | Scalable size for SVE vector registers. |
| OPSZ_SCALABLE_PRED | Scalable size for SVE predicate registers. |
| OPSZ_16_vex32_evex64 | 16, 32, or 64 bytes depending on EVEX.L and EVEX.LL'. |
| OPSZ_vex32_evex64 | 32 or 64 bytes depending on EVEX.L and EVEX.LL'. |
| OPSZ_16_of_32_evex64 | 128 bits: half of YMM or quarter of ZMM depending on EVEX.LL'. |
| OPSZ_32_of_64 | 256 bits: half of ZMM. |
| OPSZ_4_of_32_evex64 | 32 bits: can be part of YMM or ZMM register. |
| OPSZ_8_of_32_evex64 | 64 bits: can be part of YMM or ZMM register. |
| OPSZ_8x16 | 8 or 16 bytes, but not based on rex prefix, instead dependent on 32-bit/64-bit mode. |
| VENDOR_INTEL | proc_get_vendor() processor identification: Intel |
| VENDOR_AMD | proc_get_vendor() processor identification: AMD |
| VENDOR_ARM | proc_get_vendor() processor identification: ARM |
| VENDOR_UNKNOWN | proc_get_vendor() processor identification: unknown |
| DR_MAP_PRIVATE | If set, changes to mapped memory are private to the mapping process and are not reflected in the underlying file. If not set, changes are visible to other processes that map the same file, and will be propagated to the file itself. |
| DR_MAP_FIXED | If set, indicates that the passed-in start address is required rather than a hint. On Linux, this has the same semantics as mmap with MAP_FIXED: i.e., any existing mapping in [addr,addr+size) will be unmapped. This flag is not supported on Windows. |
| DR_MAP_IMAGE | If set, loads the specified file as an executable image, rather than a data file. This flag is not supported on Linux. |
| DR_MAP_CACHE_REACHABLE | If set, loads the specified file at a location that is reachable from the code cache and client libraries by a 32-bit displacement. If not set, the mapped file is not guaranteed to be reachable from the cache. |
| DRMGR_PRIORITY_APP2APP_DRBBDUP | Priority of drbbdup's app2app stage. |
| DRMGR_PRIORITY_INSERT_DRBBDUP | Priority of drbbdup's insert stage. |
| DRMGR_PRIORITY_INSERT_DRREG_HIGH | Priority of drreg analysis and pre-insert |
| DRMGR_PRIORITY_INSERT_DRREG_LOW | Priority of drreg post-insert |
| DRMGR_PRIORITY_FAULT_DRREG | Priority of drreg fault handling event |
| DRSYM_TYPE_OTHER | Unknown type, cannot downcast. |
| DRSYM_TYPE_INT | Integer, cast to drsym_int_type_t. |
| DRSYM_TYPE_PTR | Pointer, cast to drsym_ptr_type_t. |
| DRSYM_TYPE_FUNC | Function, cast to drsym_func_type_t. |
| DRSYM_TYPE_VOID | Void. No further information. |
| DRSYM_TYPE_COMPOUND | Struct, union, or class; cast to drsym_compound_type_t. |
| DRMGR_PRIORITY_APP2APP_DRWRAP | Priority of drwrap_replace() |
| DRMGR_PRIORITY_INSERT_DRWRAP | Priority of drwrap_wrap() |
| DRMGR_PRIORITY_FAULT_DRWRAP | Priority of fault handling event |
| DRMGR_PRIORITY_FAULT_DRX | Priority of drx fault handling event. |