DynamoRIO
Macros | Enumerations
dr_ir_macros_arm.h File Reference

ARM-specific instruction creation convenience macros. More...

Macros

#define OPND_CREATE_ABSMEM(addr, size)   opnd_create_rel_addr(addr, size)
 
#define OPND_CREATE_NEG_REG(reg)   opnd_create_reg_ex(reg, 0, DR_OPND_NEGATED)
 
#define OPND_CREATE_INT(val)   OPND_CREATE_INTPTR(val)
 
#define OPND_CREATE_INT_MSR_NZCVQ()   opnd_create_immed_int(EFLAGS_MSR_NZCVQ, OPSZ_4b)
 
#define OPND_CREATE_INT_MSR_G()   opnd_create_immed_int(EFLAGS_MSR_G, OPSZ_4b)
 
#define OPND_CREATE_INT_MSR_NZCVQG()   opnd_create_immed_int(EFLAGS_MSR_NZCVQG, OPSZ_4b)
 
#define OPND_CREATE_MEMLIST(base)    opnd_create_base_disp(base, DR_REG_NULL, 0, 0, OPSZ_VAR_REGLIST)
 
#define INSTR_CREATE_pop(dc, Rd)
 
#define INSTR_CREATE_pop_list(dc, list_len, ...)    INSTR_CREATE_ldm_wb((dc), OPND_CREATE_MEMLIST(DR_REG_XSP), list_len, __VA_ARGS__)
 
#define INSTR_CREATE_push(dc, Rt)
 
#define INSTR_CREATE_push_list(dc, list_len, ...)    INSTR_CREATE_stmdb_wb((dc), OPND_CREATE_MEMLIST(DR_REG_XSP), list_len, __VA_ARGS__)
 
#define INSTR_CREATE_neg(dc, Rd, Rn)    INSTR_CREATE_rsb((dc), (Rd), (Rn), OPND_CREATE_INT16(0))
 
Platform-independent macros
#define XINST_CREATE_debug_instr(dc)   INSTR_CREATE_bkpt((dc), OPND_CREATE_INT8(1))
 
#define XINST_CREATE_load(dc, r, m)   INSTR_CREATE_ldr((dc), (r), (m))
 
#define XINST_CREATE_load_1byte_zext4(dc, r, m)   INSTR_CREATE_ldrb((dc), (r), (m))
 
#define XINST_CREATE_load_1byte(dc, r, m)   INSTR_CREATE_ldrb((dc), (r), (m))
 
#define XINST_CREATE_load_2bytes(dc, r, m)   INSTR_CREATE_ldrh((dc), (r), (m))
 
#define XINST_CREATE_store(dc, m, r)   INSTR_CREATE_str((dc), (m), (r))
 
#define XINST_CREATE_store_1byte(dc, m, r)   INSTR_CREATE_strb((dc), (m), (r))
 
#define XINST_CREATE_store_2bytes(dc, m, r)   INSTR_CREATE_strh((dc), (m), (r))
 
#define XINST_CREATE_store_pair(dc, m, r1, r2)   INSTR_CREATE_strd((dc), (m), (r1), (r2))
 
#define XINST_CREATE_load_pair(dc, r1, r2, m)   INSTR_CREATE_ldrd((dc), (r1), (r2), (m))
 
#define XINST_CREATE_move(dc, d, s)   INSTR_CREATE_mov((dc), (d), (s))
 
#define XINST_CREATE_load_simd(dc, r, m)   INSTR_CREATE_vldr((dc), (r), (m))
 
#define XINST_CREATE_store_simd(dc, m, r)   INSTR_CREATE_vstr((dc), (m), (r))
 
#define XINST_CREATE_jump_mem(dc, m)    INSTR_CREATE_ldr((dc), opnd_create_reg(DR_REG_PC), (m))
 
#define XINST_CREATE_jump_reg(dc, r)   INSTR_CREATE_bx((dc), (r))
 
#define XINST_CREATE_load_int(dc, r, i)
 
#define XINST_CREATE_return(dc)   INSTR_CREATE_pop(dc, opnd_create_reg(DR_REG_PC))
 
#define XINST_CREATE_jump(dc, t)   INSTR_CREATE_b((dc), (t))
 
#define XINST_CREATE_call(dc, t)   INSTR_CREATE_bl((dc), (t))
 
#define XINST_CREATE_jump_short(dc, t)
 
#define XINST_CREATE_jump_cond(dc, pred, t)    (INSTR_PRED(INSTR_CREATE_b((dc), (t)), (pred)))
 
#define XINST_CREATE_add(dc, d, s)   INSTR_CREATE_add((dc), (d), (d), (s))
 
#define XINST_CREATE_add_2src(dc, d, s1, s2)   INSTR_CREATE_add((dc), (d), (s1), (s2))
 
#define XINST_CREATE_add_sll(dc, d, s1, s2_toshift, shift_amount)
 
#define XINST_CREATE_add_s(dc, d, s)   INSTR_CREATE_adds((dc), (d), (d), (s))
 
#define XINST_CREATE_sub(dc, d, s)   INSTR_CREATE_sub((dc), (d), (d), (s))
 
#define XINST_CREATE_sub_s(dc, d, s)   INSTR_CREATE_subs((dc), (d), (d), (s))
 
#define XINST_CREATE_and_s(dc, d, s)   INSTR_CREATE_ands((dc), (d), (d), (s))
 
#define XINST_CREATE_slr_s(dc, d, s)   INSTR_CREATE_lsrs((dc), (d), (d), (s))
 
#define XINST_CREATE_cmp(dc, s1, s2)   INSTR_CREATE_cmp((dc), (s1), (s2))
 
#define XINST_CREATE_interrupt(dc, i)   INSTR_CREATE_svc(dc, (i))
 
#define XINST_CREATE_nop(dc)   INSTR_CREATE_nop(dc)
 
#define XINST_CREATE_call_reg(dc, r)   INSTR_CREATE_blx_ind(dc, r)
 
Signature: (pc)
#define INSTR_CREATE_b_short(dc, pc)   instr_create_0dst_1src((dc), OP_b_short, (pc))
 
#define INSTR_CREATE_b(dc, pc)   instr_create_0dst_1src((dc), OP_b, (pc))
 
#define INSTR_CREATE_b_short(dc, pc)   instr_create_0dst_1src((dc), OP_b_short, (pc))
 
#define INSTR_CREATE_bl(dc, pc)    instr_create_1dst_1src((dc), OP_bl, opnd_create_reg(DR_REG_LR), (pc))
 
#define INSTR_CREATE_blx(dc, pc)    instr_create_1dst_1src((dc), OP_blx, opnd_create_reg(DR_REG_LR), (pc))
 
Signature: ()
#define INSTR_CREATE_clrex(dc)   instr_create_0dst_0src((dc), OP_clrex)
 
#define INSTR_CREATE_dcps1(dc)   instr_create_0dst_0src((dc), OP_dcps1)
 
#define INSTR_CREATE_dcps2(dc)   instr_create_0dst_0src((dc), OP_dcps2)
 
#define INSTR_CREATE_dcps3(dc)   instr_create_0dst_0src((dc), OP_dcps3)
 
#define INSTR_CREATE_enterx(dc)   instr_create_0dst_0src((dc), OP_enterx)
 
#define INSTR_CREATE_eret(dc)    instr_create_0dst_1src((dc), OP_eret, opnd_create_reg(DR_REG_LR))
 
#define INSTR_CREATE_leavex(dc)   instr_create_0dst_0src((dc), OP_leavex)
 
#define INSTR_CREATE_nop(dc)   instr_create_0dst_0src((dc), OP_nop)
 
#define INSTR_CREATE_sev(dc)   instr_create_0dst_0src((dc), OP_sev)
 
#define INSTR_CREATE_sevl(dc)   instr_create_0dst_0src((dc), OP_sevl)
 
#define INSTR_CREATE_wfe(dc)   instr_create_0dst_0src((dc), OP_wfe)
 
#define INSTR_CREATE_wfi(dc)   instr_create_0dst_0src((dc), OP_wfi)
 
#define INSTR_CREATE_yield(dc)   instr_create_0dst_0src((dc), OP_yield)
 
Signature: (Rd)
#define INSTR_CREATE_vmrs(dc, Rd)    instr_create_1dst_1src((dc), OP_vmrs, (Rd), opnd_create_reg(DR_REG_FPSCR))
 
Signature: (Rm)
#define INSTR_CREATE_blx_ind(dc, Rm)    instr_create_1dst_1src((dc), OP_blx_ind, opnd_create_reg(DR_REG_LR), (Rm))
 
#define INSTR_CREATE_bx(dc, Rm)   instr_create_0dst_1src((dc), OP_bx, (Rm))
 
#define INSTR_CREATE_bxj(dc, Rm)   instr_create_0dst_1src((dc), OP_bxj, (Rm))
 
Signature: (Rt)
#define INSTR_CREATE_vmsr(dc, Rt)    instr_create_1dst_1src((dc), OP_vmsr, opnd_create_reg(DR_REG_FPSCR), (Rt))
 
Signature: (Rd, Rm)
#define INSTR_CREATE_clz(dc, Rd, Rm)   instr_create_1dst_1src((dc), OP_clz, (Rd), (Rm))
 
#define INSTR_CREATE_rbit(dc, Rd, Rm)   instr_create_1dst_1src((dc), OP_rbit, (Rd), (Rm))
 
#define INSTR_CREATE_rev(dc, Rd, Rm)   instr_create_1dst_1src((dc), OP_rev, (Rd), (Rm))
 
#define INSTR_CREATE_rev16(dc, Rd, Rm)   instr_create_1dst_1src((dc), OP_rev16, (Rd), (Rm))
 
#define INSTR_CREATE_revsh(dc, Rd, Rm)   instr_create_1dst_1src((dc), OP_revsh, (Rd), (Rm))
 
#define INSTR_CREATE_rrx(dc, Rd, Rm)   instr_create_1dst_1src((dc), OP_rrx, (Rd), (Rm))
 
#define INSTR_CREATE_rrxs(dc, Rd, Rm)   instr_create_1dst_1src((dc), OP_rrxs, (Rd), (Rm))
 
Signature: (Rd, Rn)
#define INSTR_CREATE_sxtb(dc, Rd, Rn)   instr_create_1dst_1src((dc), OP_sxtb, (Rd), (Rn))
 
#define INSTR_CREATE_sxth(dc, Rd, Rn)   instr_create_1dst_1src((dc), OP_sxth, (Rd), (Rn))
 
#define INSTR_CREATE_uxtb(dc, Rd, Rn)   instr_create_1dst_1src((dc), OP_uxtb, (Rd), (Rn))
 
#define INSTR_CREATE_uxth(dc, Rd, Rn)   instr_create_1dst_1src((dc), OP_uxth, (Rd), (Rn))
 
Signature: (pc, Rn)
#define INSTR_CREATE_cbnz(dc, pc, Rn)   instr_create_0dst_2src((dc), OP_cbnz, (pc), (Rn))
 
#define INSTR_CREATE_cbz(dc, pc, Rn)   instr_create_0dst_2src((dc), OP_cbz, (pc), (Rn))
 
Signature: (Rd, statreg)
#define INSTR_CREATE_mrs(dc, Rd, statreg)    instr_create_1dst_1src((dc), OP_mrs, (Rd), (statreg))
 
Signature: (Rd, Rm, Rn)
#define INSTR_CREATE_qsub(dc, Rd, Rm, Rn)    instr_create_1dst_2src((dc), OP_qsub, (Rd), (Rm), (Rn))
 
Signature: (Rd, Rn, Rm)
#define INSTR_CREATE_crc32b(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_crc32b, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_crc32cb(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_crc32cb, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_crc32ch(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_crc32ch, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_crc32cw(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_crc32cw, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_crc32h(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_crc32h, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_crc32w(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_crc32w, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_mul(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_mul, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_muls(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_muls, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_qadd(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_qadd, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_qadd16(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_qadd16, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_qadd8(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_qadd8, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_qasx(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_qasx, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_qdadd(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_qdadd, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_qdsub(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_qdsub, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_qsax(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_qsax, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_qsub16(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_qsub16, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_qsub8(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_qsub8, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_sadd16(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_sadd16, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_sadd8(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_sadd8, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_sasx(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_sasx, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_sdiv(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_sdiv, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_sel(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_sel, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_shadd16(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_shadd16, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_shadd8(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_shadd8, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_shasx(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_shasx, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_shsax(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_shsax, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_shsub16(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_shsub16, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_shsub8(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_shsub8, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_smmul(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_smmul, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_smmulr(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_smmulr, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_smuad(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_smuad, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_smuadx(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_smuadx, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_smulbb(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_smulbb, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_smulbt(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_smulbt, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_smultb(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_smultb, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_smultt(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_smultt, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_smulwb(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_smulwb, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_smulwt(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_smulwt, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_smusd(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_smusd, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_smusdx(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_smusdx, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_ssax(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_ssax, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_ssub16(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_ssub16, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_ssub8(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_ssub8, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_uadd16(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_uadd16, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_uadd8(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_uadd8, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_uasx(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_uasx, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_udiv(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_udiv, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_uhadd16(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_uhadd16, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_uhadd8(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_uhadd8, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_uhasx(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_uhasx, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_uhsax(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_uhsax, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_uhsub16(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_uhsub16, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_uhsub8(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_uhsub8, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_uqadd16(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_uqadd16, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_uqadd8(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_uqadd8, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_uqasx(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_uqasx, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_uqsax(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_uqsax, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_uqsub16(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_uqsub16, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_uqsub8(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_uqsub8, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_usad8(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_usad8, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_usax(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_usax, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_usub16(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_usub16, (Rd), (Rn), (Rm))
 
#define INSTR_CREATE_usub8(dc, Rd, Rn, Rm)    instr_create_1dst_2src((dc), OP_usub8, (Rd), (Rn), (Rm))
 
Signature: (Rd, Rn, Rm, Ra)
#define INSTR_CREATE_mla(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_mla, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_mlas(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_mlas, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_mls(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_mls, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_smlabb(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_smlabb, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_smlabt(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_smlabt, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_smlad(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_smlad, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_smladx(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_smladx, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_smlatb(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_smlatb, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_smlatt(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_smlatt, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_smlawb(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_smlawb, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_smlawt(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_smlawt, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_smlsd(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_smlsd, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_smlsdx(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_smlsdx, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_smmla(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_smmla, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_smmlar(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_smmlar, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_smmls(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_smmls, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_smmlsr(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_smmlsr, (Rd), (Rn), (Rm), (Ra))
 
#define INSTR_CREATE_usada8(dc, Rd, Rn, Rm, Ra)    instr_create_1dst_3src((dc), OP_usada8, (Rd), (Rn), (Rm), (Ra))
 
Signature: (Rd, Rd2, Rn, Rm)
#define INSTR_CREATE_smlal(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_4src((dc), OP_smlal, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_smlalbb(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_4src((dc), OP_smlalbb, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_smlalbt(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_4src((dc), OP_smlalbt, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_smlald(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_4src((dc), OP_smlald, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_smlaldx(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_4src((dc), OP_smlaldx, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_smlals(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_4src((dc), OP_smlals, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_smlaltb(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_4src((dc), OP_smlaltb, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_smlaltt(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_4src((dc), OP_smlaltt, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_smlsld(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_4src((dc), OP_smlsld, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_smlsldx(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_4src((dc), OP_smlsldx, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_smull(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_2src((dc), OP_smull, (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_smulls(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_2src((dc), OP_smulls, (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_umaal(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_4src((dc), OP_umaal, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_umlal(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_4src((dc), OP_umlal, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_umlals(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_4src((dc), OP_umlals, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_umull(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_2src((dc), OP_umull, (Rd), (Rd2), (Rn), (Rm))
 
#define INSTR_CREATE_umulls(dc, Rd, Rd2, Rn, Rm)    instr_create_2dst_2src((dc), OP_umulls, (Rd), (Rd2), (Rn), (Rm))
 
Signature: (imm)
#define INSTR_CREATE_bkpt(dc, imm)   instr_create_0dst_1src((dc), OP_bkpt, (imm))
 
#define INSTR_CREATE_cps(dc, imm)   instr_create_0dst_1src((dc), OP_cps, (imm))
 
#define INSTR_CREATE_cpsid(dc, imm)   instr_create_0dst_1src((dc), OP_cpsid, (imm))
 
#define INSTR_CREATE_cpsie(dc, imm)   instr_create_0dst_1src((dc), OP_cpsie, (imm))
 
#define INSTR_CREATE_dbg(dc, imm)   instr_create_0dst_1src((dc), OP_dbg, (imm))
 
#define INSTR_CREATE_dmb(dc, imm)   instr_create_0dst_1src((dc), OP_dmb, (imm))
 
#define INSTR_CREATE_dsb(dc, imm)   instr_create_0dst_1src((dc), OP_dsb, (imm))
 
#define INSTR_CREATE_eret_imm(dc, imm)    instr_create_0dst_2src((dc), OP_eret, opnd_create_reg(DR_REG_LR), (imm))
 
#define dr_ir_macros_arm_hlt(dc, imm)   instr_create_0dst_1src((dc), OP_hlt, (imm))
 
#define dr_ir_macros_arm_hvc(dc, imm)   instr_create_0dst_1src((dc), OP_hvc, (imm))
 
#define INSTR_CREATE_isb(dc, imm)   instr_create_0dst_1src((dc), OP_isb, (imm))
 
#define INSTR_CREATE_setend(dc, imm)   instr_create_0dst_1src((dc), OP_setend, (imm))
 
#define INSTR_CREATE_smc(dc, imm)   instr_create_0dst_1src((dc), OP_smc, (imm))
 
#define INSTR_CREATE_svc(dc, imm)   instr_create_0dst_1src((dc), OP_svc, (imm))
 
#define INSTR_CREATE_udf(dc, imm)   instr_create_0dst_1src((dc), OP_udf, (imm))
 
Signature: (Rd, imm)
#define INSTR_CREATE_movt(dc, Rd, imm)   instr_create_1dst_1src((dc), OP_movt, (Rd), (imm))
 
#define INSTR_CREATE_movw(dc, Rd, imm)   instr_create_1dst_1src((dc), OP_movw, (Rd), (imm))
 
#define INSTR_CREATE_mrs_priv(dc, Rd, imm)    instr_create_1dst_1src((dc), OP_mrs_priv, (Rd), (imm))
 
#define INSTR_CREATE_vmrs_imm(dc, Rd, imm)    instr_create_1dst_1src((dc), OP_vmrs, (Rd), (imm))
 
Signature: (Rt, imm)
#define INSTR_CREATE_vmsr_imm(dc, Rt, imm)    instr_create_0dst_2src((dc), OP_vmsr, (Rt), (imm))
 
Signature: (imm, Rm)
#define INSTR_CREATE_msr_priv(dc, imm, Rm)    instr_create_0dst_2src((dc), OP_msr_priv, (imm), (Rm))
 
Signature: (imm, imm2)
#define INSTR_CREATE_cpsid_noflags(dc, imm, imm2)    instr_create_0dst_2src((dc), OP_cpsid, (imm), (imm2))
 
#define INSTR_CREATE_cpsie_noflags(dc, imm, imm2)    instr_create_0dst_2src((dc), OP_cpsie, (imm), (imm2))
 
#define INSTR_CREATE_it(dc, imm, imm2)   instr_create_0dst_2src((dc), OP_it, (imm), (imm2))
 
Signature: (Rd, Rm_or_imm)
#define INSTR_CREATE_mov(dc, Rd, Rm_or_imm)    instr_create_1dst_1src((dc), OP_mov, (Rd), (Rm_or_imm))
 
#define INSTR_CREATE_movs(dc, Rd, Rm_or_imm)    instr_create_1dst_1src((dc), OP_movs, (Rd), (Rm_or_imm))
 
#define INSTR_CREATE_mvn(dc, Rd, Rm_or_imm)
 
#define INSTR_CREATE_mvns(dc, Rd, Rm_or_imm)
 
Signature: (Rn, Rm_or_imm)
#define INSTR_CREATE_cmn(dc, Rn, Rm_or_imm)
 
#define INSTR_CREATE_cmp(dc, Rn, Rm_or_imm)
 
#define INSTR_CREATE_teq(dc, Rn, Rm_or_imm)
 
#define INSTR_CREATE_tst(dc, Rn, Rm_or_imm)
 
Signature: (Rd, Rm, imm)
#define INSTR_CREATE_sxtb16(dc, Rd, Rm, imm)    instr_create_1dst_2src((dc), OP_sxtb16, (Rd), (Rm), (imm))
 
#define INSTR_CREATE_sxtb_imm(dc, Rd, Rm, imm)    instr_create_1dst_2src((dc), OP_sxtb, (Rd), (Rm), (imm))
 
#define INSTR_CREATE_sxth_imm(dc, Rd, Rm, imm)    instr_create_1dst_2src((dc), OP_sxth, (Rd), (Rm), (imm))
 
#define INSTR_CREATE_uxtb16(dc, Rd, Rm, imm)    instr_create_1dst_2src((dc), OP_uxtb16, (Rd), (Rm), (imm))
 
#define INSTR_CREATE_uxtb_imm(dc, Rd, Rm, imm)    instr_create_1dst_2src((dc), OP_uxtb, (Rd), (Rm), (imm))
 
#define INSTR_CREATE_uxth_imm(dc, Rd, Rm, imm)    instr_create_1dst_2src((dc), OP_uxth, (Rd), (Rm), (imm))
 
Signature: (Rd, Rn, imm)
#define INSTR_CREATE_addw(dc, Rd, Rn, imm)    instr_create_1dst_2src((dc), OP_addw, (Rd), (Rn), (imm))
 
#define INSTR_CREATE_subw(dc, Rd, Rn, imm)    instr_create_1dst_2src((dc), OP_subw, (Rd), (Rn), (imm))
 
Signature: (Rd, imm, Rm)
#define INSTR_CREATE_ssat16(dc, Rd, imm, Rm)    instr_create_1dst_2src((dc), OP_ssat16, (Rd), (imm), (Rm))
 
#define INSTR_CREATE_usat16(dc, Rd, imm, Rm)    instr_create_1dst_2src((dc), OP_usat16, (Rd), (imm), (Rm))
 
Signature: (Rd, imm, imm2)
#define INSTR_CREATE_bfc(dc, Rd, imm, imm2)    instr_create_1dst_3src((dc), OP_bfc, (Rd), (imm), (imm2), (Rd))
 
Signature: (Rd, Rn, Rm_or_imm)
#define INSTR_CREATE_adc(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_adcs(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_add(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_adds(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_and(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_ands(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_asr(dc, Rd, Rn, Rm_or_imm)    instr_create_1dst_2src((dc), OP_asr, (Rd), (Rn), (Rm_or_imm))
 
#define INSTR_CREATE_asrs(dc, Rd, Rn, Rm_or_imm)    instr_create_1dst_2src((dc), OP_asrs, (Rd), (Rn), (Rm_or_imm))
 
#define INSTR_CREATE_bic(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_bics(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_eor(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_eors(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_lsl(dc, Rd, Rn, Rm_or_imm)    instr_create_1dst_2src((dc), OP_lsl, (Rd), (Rn), (Rm_or_imm))
 
#define INSTR_CREATE_lsls(dc, Rd, Rn, Rm_or_imm)    instr_create_1dst_2src((dc), OP_lsls, (Rd), (Rn), (Rm_or_imm))
 
#define INSTR_CREATE_lsr(dc, Rd, Rn, Rm_or_imm)    instr_create_1dst_2src((dc), OP_lsr, (Rd), (Rn), (Rm_or_imm))
 
#define INSTR_CREATE_lsrs(dc, Rd, Rn, Rm_or_imm)    instr_create_1dst_2src((dc), OP_lsrs, (Rd), (Rn), (Rm_or_imm))
 
#define INSTR_CREATE_orn(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_orns(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_orr(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_orrs(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_ror(dc, Rd, Rn, Rm_or_imm)    instr_create_1dst_2src((dc), OP_ror, (Rd), (Rn), (Rm_or_imm))
 
#define INSTR_CREATE_rors(dc, Rd, Rn, Rm_or_imm)    instr_create_1dst_2src((dc), OP_rors, (Rd), (Rn), (Rm_or_imm))
 
#define INSTR_CREATE_rsb(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_rsbs(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_rsc(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_rscs(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_sbc(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_sbcs(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_sub(dc, Rd, Rn, Rm_or_imm)
 
#define INSTR_CREATE_subs(dc, Rd, Rn, Rm_or_imm)
 
Signature: (Rd, statreg, imm)
#define INSTR_CREATE_mrs_priv_spsr(dc, Rd, statreg, imm)    instr_create_1dst_2src((dc), OP_mrs_priv, (Rd), (statreg), (imm))
 
Signature: (statreg, imm, Rm)
#define INSTR_CREATE_msr_priv_spsr(dc, statreg, imm, Rm)    instr_create_1dst_2src((dc), OP_msr_priv, (statreg), (imm), (Rm))
 
Signature: (statreg, imm, imm2)
#define INSTR_CREATE_msr_imm(dc, statreg, imm, imm2)    instr_create_1dst_2src((dc), OP_msr, (statreg), (imm), (imm2))
 
Signature: (statreg, imm_msr, Rm)
#define INSTR_CREATE_msr(dc, statreg, imm_msr, Rm)    instr_create_1dst_2src((dc), OP_msr, (statreg), (imm_msr), (Rm))
 
Signature: (Rd, Rn, Rm, imm)
#define INSTR_CREATE_sxtab(dc, Rd, Rn, Rm, imm)    instr_create_1dst_3src((dc), OP_sxtab, (Rd), (Rn), (Rm), (imm))
 
#define INSTR_CREATE_sxtab16(dc, Rd, Rn, Rm, imm)    instr_create_1dst_3src((dc), OP_sxtab16, (Rd), (Rn), (Rm), (imm))
 
#define INSTR_CREATE_sxtah(dc, Rd, Rn, Rm, imm)    instr_create_1dst_3src((dc), OP_sxtah, (Rd), (Rn), (Rm), (imm))
 
#define INSTR_CREATE_uxtab(dc, Rd, Rn, Rm, imm)    instr_create_1dst_3src((dc), OP_uxtab, (Rd), (Rn), (Rm), (imm))
 
#define INSTR_CREATE_uxtab16(dc, Rd, Rn, Rm, imm)    instr_create_1dst_3src((dc), OP_uxtab16, (Rd), (Rn), (Rm), (imm))
 
#define INSTR_CREATE_uxtah(dc, Rd, Rn, Rm, imm)    instr_create_1dst_3src((dc), OP_uxtah, (Rd), (Rn), (Rm), (imm))
 
Signature: (Rd, Rm, imm, imm2)
#define INSTR_CREATE_bfi(dc, Rd, Rm, imm, imm2)    instr_create_1dst_4src((dc), OP_bfi, (Rd), (Rm), (imm), (imm2), (Rd))
 
#define INSTR_CREATE_sbfx(dc, Rd, Rm, imm, imm2)    instr_create_1dst_3src((dc), OP_sbfx, (Rd), (Rm), (imm), (imm2))
 
#define INSTR_CREATE_ubfx(dc, Rd, Rm, imm, imm2)    instr_create_1dst_3src((dc), OP_ubfx, (Rd), (Rm), (imm), (imm2))
 
Signature: (Rd, Rm, shift, Rs)
#define INSTR_CREATE_mvn_shreg(dc, Rd, Rm, shift, Rs)
 
#define INSTR_CREATE_mvns_shreg(dc, Rd, Rm, shift, Rs)
 
Signature: (Rn, Rm, shift, Rs)
#define INSTR_CREATE_cmn_shreg(dc, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_cmp_shreg(dc, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_teq_shreg(dc, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_tst_shreg(dc, Rn, Rm, shift, Rs)
 
Signature: (Rd, Rn, Rm, shift, Rs)
#define INSTR_CREATE_adc_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_adcs_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_add_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_adds_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_and_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_ands_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_bic_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_bics_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_eor_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_eors_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_orr_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_orrs_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_rsb_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_rsbs_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_rsc_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_rscs_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_sbc_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_sbcs_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_sub_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
#define INSTR_CREATE_subs_shreg(dc, Rd, Rn, Rm, shift, Rs)
 
Signature: (Rd, Rm, shift, imm)
#define INSTR_CREATE_mvn_shimm(dc, Rd, Rm, shift, imm)
 
#define INSTR_CREATE_mvns_shimm(dc, Rd, Rm, shift, imm)
 
Signature: (Rn, Rm, shift, imm)
#define INSTR_CREATE_cmn_shimm(dc, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_cmp_shimm(dc, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_teq_shimm(dc, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_tst_shimm(dc, Rn, Rm, shift, imm)
 
Signature: (Rd, Rn, Rm, shift, imm)
#define INSTR_CREATE_adc_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_adcs_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_add_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_adds_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_and_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_ands_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_bic_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_bics_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_eor_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_eors_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_orn_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_orns_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_orr_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_orrs_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_pkhbt_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_pkhtb_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_rsb_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_rsbs_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_rsc_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_rscs_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_sbc_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_sbcs_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_sub_shimm(dc, Rd, Rn, Rm, shift, imm)
 
#define INSTR_CREATE_subs_shimm(dc, Rd, Rn, Rm, shift, imm)
 
Signature: (Rd, imm, Rm, shift, imm2)
#define INSTR_CREATE_ssat_shimm(dc, Rd, imm, Rm, shift, imm2)
 
#define INSTR_CREATE_usat_shimm(dc, Rd, imm, Rm, shift, imm2)
 
Signature: (mem)
#define INSTR_CREATE_pld(dc, mem)   instr_create_0dst_1src((dc), OP_pld, (mem))
 
#define INSTR_CREATE_pldw(dc, mem)   instr_create_0dst_1src((dc), OP_pldw, (mem))
 
#define INSTR_CREATE_pli(dc, mem)   instr_create_0dst_1src((dc), OP_pli, (mem))
 
#define INSTR_CREATE_tbb(dc, mem)   instr_create_0dst_1src((dc), OP_tbb, (mem))
 
#define INSTR_CREATE_tbh(dc, mem)   instr_create_0dst_1src((dc), OP_tbh, (mem))
 
Signature: (Rd, mem)
#define INSTR_CREATE_lda(dc, Rd, mem)   instr_create_1dst_1src((dc), OP_lda, (Rd), (mem))
 
#define INSTR_CREATE_ldab(dc, Rd, mem)   instr_create_1dst_1src((dc), OP_ldab, (Rd), (mem))
 
#define INSTR_CREATE_ldaex(dc, Rd, mem)    instr_create_1dst_1src((dc), OP_ldaex, (Rd), (mem))
 
#define INSTR_CREATE_ldaexb(dc, Rd, mem)    instr_create_1dst_1src((dc), OP_ldaexb, (Rd), (mem))
 
#define INSTR_CREATE_ldaexh(dc, Rd, mem)    instr_create_1dst_1src((dc), OP_ldaexh, (Rd), (mem))
 
#define INSTR_CREATE_ldah(dc, Rd, mem)   instr_create_1dst_1src((dc), OP_ldah, (Rd), (mem))
 
#define INSTR_CREATE_ldr(dc, Rd, mem)   instr_create_1dst_1src((dc), OP_ldr, (Rd), (mem))
 
#define INSTR_CREATE_ldrb(dc, Rd, mem)   instr_create_1dst_1src((dc), OP_ldrb, (Rd), (mem))
 
#define INSTR_CREATE_ldrbt(dc, Rd, mem)    instr_create_1dst_1src((dc), OP_ldrbt, (Rd), (mem))
 
#define INSTR_CREATE_ldrex(dc, Rd, mem)    instr_create_1dst_1src((dc), OP_ldrex, (Rd), (mem))
 
#define INSTR_CREATE_ldrexb(dc, Rd, mem)    instr_create_1dst_1src((dc), OP_ldrexb, (Rd), (mem))
 
#define INSTR_CREATE_ldrexh(dc, Rd, mem)    instr_create_1dst_1src((dc), OP_ldrexh, (Rd), (mem))
 
#define INSTR_CREATE_ldrh(dc, Rd, mem)   instr_create_1dst_1src((dc), OP_ldrh, (Rd), (mem))
 
#define INSTR_CREATE_ldrht(dc, Rd, mem)    instr_create_1dst_1src((dc), OP_ldrht, (Rd), (mem))
 
#define INSTR_CREATE_ldrsb(dc, Rd, mem)    instr_create_1dst_1src((dc), OP_ldrsb, (Rd), (mem))
 
#define INSTR_CREATE_ldrsbt(dc, Rd, mem)    instr_create_1dst_1src((dc), OP_ldrsbt, (Rd), (mem))
 
#define INSTR_CREATE_ldrsh(dc, Rd, mem)    instr_create_1dst_1src((dc), OP_ldrsh, (Rd), (mem))
 
#define INSTR_CREATE_ldrsht(dc, Rd, mem)    instr_create_1dst_1src((dc), OP_ldrsht, (Rd), (mem))
 
#define INSTR_CREATE_ldrt(dc, Rd, mem)   instr_create_1dst_1src((dc), OP_ldrt, (Rd), (mem))
 
Signature: (mem, Rm)
#define INSTR_CREATE_stl(dc, mem, Rm)   instr_create_1dst_1src((dc), OP_stl, (mem), (Rm))
 
#define INSTR_CREATE_stlb(dc, mem, Rm)   instr_create_1dst_1src((dc), OP_stlb, (mem), (Rm))
 
#define INSTR_CREATE_stlh(dc, mem, Rm)   instr_create_1dst_1src((dc), OP_stlh, (mem), (Rm))
 
Signature: (mem, Rt)
#define INSTR_CREATE_str(dc, mem, Rt)   instr_create_1dst_1src((dc), OP_str, (mem), (Rt))
 
#define INSTR_CREATE_strb(dc, mem, Rt)   instr_create_1dst_1src((dc), OP_strb, (mem), (Rt))
 
#define INSTR_CREATE_strbt(dc, mem, Rt)    instr_create_1dst_1src((dc), OP_strbt, (mem), (Rt))
 
#define INSTR_CREATE_strh(dc, mem, Rt)   instr_create_1dst_1src((dc), OP_strh, (mem), (Rt))
 
#define INSTR_CREATE_strht(dc, mem, Rt)    instr_create_1dst_1src((dc), OP_strht, (mem), (Rt))
 
#define INSTR_CREATE_strt(dc, mem, Rt)   instr_create_1dst_1src((dc), OP_strt, (mem), (Rt))
 
Signature: (statreg, mem)
#define INSTR_CREATE_rfe(dc, statreg, mem)    instr_create_1dst_1src((dc), OP_rfe, (statreg), (mem))
 
#define INSTR_CREATE_rfe_wb(dc, statreg, mem)
 
#define INSTR_CREATE_rfeda(dc, statreg, mem)    instr_create_1dst_1src((dc), OP_rfeda, (statreg), (mem))
 
#define INSTR_CREATE_rfeda_wb(dc, statreg, mem)
 
#define INSTR_CREATE_rfedb(dc, statreg, mem)    instr_create_1dst_1src((dc), OP_rfedb, (statreg), (mem))
 
#define INSTR_CREATE_rfedb_wb(dc, statreg, mem)
 
#define INSTR_CREATE_rfeib(dc, statreg, mem)    instr_create_1dst_1src((dc), OP_rfeib, (statreg), (mem))
 
#define INSTR_CREATE_rfeib_wb(dc, statreg, mem)
 
Signature: (Rd, Rd2, mem)
#define INSTR_CREATE_ldaexd(dc, Rd, Rd2, mem)    instr_create_2dst_1src((dc), OP_ldaexd, (Rd), (Rd2), (mem))
 
#define INSTR_CREATE_ldrd(dc, Rd, Rd2, mem)    instr_create_2dst_1src((dc), OP_ldrd, (Rd), (Rd2), (mem))
 
#define INSTR_CREATE_ldrexd(dc, Rd, Rd2, mem)    instr_create_2dst_1src((dc), OP_ldrexd, (Rd), (Rd2), (mem))
 
Signature: (Rd, mem, Rm)
#define INSTR_CREATE_ldrh_wbreg(dc, Rd, mem, Rm)
 
#define INSTR_CREATE_ldrht_wbreg(dc, Rd, mem, Rm)
 
#define INSTR_CREATE_ldrsb_wbreg(dc, Rd, mem, Rm)
 
#define INSTR_CREATE_ldrsbt_wbreg(dc, Rd, mem, Rm)
 
#define INSTR_CREATE_ldrsh_wbreg(dc, Rd, mem, Rm)
 
#define INSTR_CREATE_ldrsht_wbreg(dc, Rd, mem, Rm)
 
#define INSTR_CREATE_swp(dc, Rd, mem, Rm)    instr_create_2dst_2src((dc), OP_swp, (mem), (Rd), (mem), (Rm))
 
#define INSTR_CREATE_swpb(dc, Rd, mem, Rm)    instr_create_2dst_2src((dc), OP_swpb, (mem), (Rd), (mem), (Rm))
 
Signature: (mem, Rd, Rm)
#define INSTR_CREATE_stlex(dc, mem, Rd, Rm)    instr_create_2dst_1src((dc), OP_stlex, (mem), (Rd), (Rm))
 
#define INSTR_CREATE_stlexb(dc, mem, Rd, Rm)    instr_create_2dst_1src((dc), OP_stlexb, (mem), (Rd), (Rm))
 
#define INSTR_CREATE_stlexh(dc, mem, Rd, Rm)    instr_create_2dst_1src((dc), OP_stlexh, (mem), (Rd), (Rm))
 
#define INSTR_CREATE_strex(dc, mem, Rd, Rm)    instr_create_2dst_1src((dc), OP_strex, (mem), (Rd), (Rm))
 
#define INSTR_CREATE_strexb(dc, mem, Rd, Rm)    instr_create_2dst_1src((dc), OP_strexb, (mem), (Rd), (Rm))
 
#define INSTR_CREATE_strexh(dc, mem, Rd, Rm)    instr_create_2dst_1src((dc), OP_strexh, (mem), (Rd), (Rm))
 
Signature: (mem, Rt, Rm)
#define INSTR_CREATE_strh_wbreg(dc, mem, Rt, Rm)
 
#define INSTR_CREATE_strht_wbreg(dc, mem, Rt, Rm)
 
Signature: (mem, Rt, Rt2)
#define INSTR_CREATE_strd(dc, mem, Rt, Rt2)    instr_create_1dst_2src((dc), OP_strd, (mem), (Rt), (Rt2))
 
Signature: (Rd, Rd2, mem, Rm)
#define INSTR_CREATE_ldrd_wbreg(dc, Rd, Rd2, mem, Rm)
 
Signature: (mem, Rd, Rt, Rt2)
#define INSTR_CREATE_stlexd(dc, mem, Rd, Rt, Rt2)    instr_create_2dst_2src((dc), OP_stlexd, (mem), (Rd), (Rt), (Rt2))
 
#define INSTR_CREATE_strexd(dc, mem, Rd, Rt, Rt2)    instr_create_2dst_2src((dc), OP_strexd, (mem), (Rd), (Rt), (Rt2))
 
Signature: (mem, Rt, Rt2, Rm)
#define INSTR_CREATE_strd_wbreg(dc, mem, Rt, Rt2, Rm)
 
Signature: (Rd, mem, imm)
#define INSTR_CREATE_ldr_wbimm(dc, Rd, mem, imm)
 
#define INSTR_CREATE_ldrb_wbimm(dc, Rd, mem, imm)
 
#define INSTR_CREATE_ldrbt_wbimm(dc, Rd, mem, imm)
 
#define INSTR_CREATE_ldrh_wbimm(dc, Rd, mem, imm)
 
#define INSTR_CREATE_ldrht_wbimm(dc, Rd, mem, imm)
 
#define INSTR_CREATE_ldrsb_wbimm(dc, Rd, mem, imm)
 
#define INSTR_CREATE_ldrsbt_wbimm(dc, Rd, mem, imm)
 
#define INSTR_CREATE_ldrsh_wbimm(dc, Rd, mem, imm)
 
#define INSTR_CREATE_ldrsht_wbimm(dc, Rd, mem, imm)
 
#define INSTR_CREATE_ldrt_wbimm(dc, Rd, mem, imm)
 
Signature: (mem, Rt, imm)
#define INSTR_CREATE_str_wbimm(dc, mem, Rt, imm)
 
#define INSTR_CREATE_strb_wbimm(dc, mem, Rt, imm)
 
#define INSTR_CREATE_strbt_wbimm(dc, mem, Rt, imm)
 
#define INSTR_CREATE_strh_wbimm(dc, mem, Rt, imm)
 
#define INSTR_CREATE_strht_wbimm(dc, mem, Rt, imm)
 
#define INSTR_CREATE_strt_wbimm(dc, mem, Rt, imm)
 
Signature: (mem, imm, statreg)
#define INSTR_CREATE_srs(dc, mem, imm, statreg)
 
#define INSTR_CREATE_srs_wbimm(dc, mem, imm, statreg)
 
#define INSTR_CREATE_srsda(dc, mem, imm, statreg)
 
#define INSTR_CREATE_srsda_wbimm(dc, mem, imm, statreg)
 
#define INSTR_CREATE_srsdb(dc, mem, imm, statreg)
 
#define INSTR_CREATE_srsdb_wbimm(dc, mem, imm, statreg)
 
#define INSTR_CREATE_srsib(dc, mem, imm, statreg)
 
#define INSTR_CREATE_srsib_wbimm(dc, mem, imm, statreg)
 
Signature: (Rd, Rd2, mem, imm)
#define INSTR_CREATE_ldrd_wbimm(dc, Rd, Rd2, mem, imm)
 
Signature: (mem, Rt, Rt2, imm)
#define INSTR_CREATE_strd_wbimm(dc, mem, Rt, Rt2, imm)
 
Signature: (Rd, mem, Rm, shift, imm)
#define INSTR_CREATE_ldr_wbreg(dc, Rd, mem, Rm, shift, imm)
 
#define INSTR_CREATE_ldrb_wbreg(dc, Rd, mem, Rm, shift, imm)
 
#define INSTR_CREATE_ldrbt_wbreg(dc, Rd, mem, Rm, shift, imm)
 
#define INSTR_CREATE_ldrt_wbreg(dc, Rd, mem, Rm, shift, imm)
 
Signature: (mem, Rt, Rm, shift, imm)
#define INSTR_CREATE_str_wbreg(dc, mem, Rt, Rm, shift, imm)
 
#define INSTR_CREATE_strb_wbreg(dc, mem, Rt, Rm, shift, imm)
 
#define INSTR_CREATE_strbt_wbreg(dc, mem, Rt, Rm, shift, imm)
 
#define INSTR_CREATE_strt_wbreg(dc, mem, Rt, Rm, shift, imm)
 
Signature: (mem, list_len, ...)
#define INSTR_CREATE_ldm(dc, mem, list_len, ...)    instr_create_Ndst_Msrc_vardst((dc), OP_ldm, 0, 1, list_len, 0, (mem), __VA_ARGS__)
 
#define INSTR_CREATE_ldm_priv(dc, mem, list_len, ...)
 
#define INSTR_CREATE_ldm_priv_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_ldm_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_ldmda(dc, mem, list_len, ...)    instr_create_Ndst_Msrc_vardst((dc), OP_ldmda, 0, 1, list_len, 0, (mem), __VA_ARGS__)
 
#define INSTR_CREATE_ldmda_priv(dc, mem, list_len, ...)
 
#define INSTR_CREATE_ldmda_priv_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_ldmda_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_ldmdb(dc, mem, list_len, ...)    instr_create_Ndst_Msrc_vardst((dc), OP_ldmdb, 0, 1, list_len, 0, (mem), __VA_ARGS__)
 
#define INSTR_CREATE_ldmdb_priv(dc, mem, list_len, ...)
 
#define INSTR_CREATE_ldmdb_priv_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_ldmdb_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_ldmib(dc, mem, list_len, ...)    instr_create_Ndst_Msrc_vardst((dc), OP_ldmib, 0, 1, list_len, 0, (mem), __VA_ARGS__)
 
#define INSTR_CREATE_ldmib_priv(dc, mem, list_len, ...)
 
#define INSTR_CREATE_ldmib_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_stm(dc, mem, list_len, ...)    instr_create_Ndst_Msrc_varsrc((dc), OP_stm, 1, 0, list_len, 0, (mem), __VA_ARGS__)
 
#define INSTR_CREATE_stm_priv(dc, mem, list_len, ...)
 
#define INSTR_CREATE_stm_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_stmda(dc, mem, list_len, ...)    instr_create_Ndst_Msrc_varsrc((dc), OP_stmda, 1, 0, list_len, 0, (mem), __VA_ARGS__)
 
#define INSTR_CREATE_stmda_priv(dc, mem, list_len, ...)
 
#define INSTR_CREATE_stmda_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_stmdb(dc, mem, list_len, ...)    instr_create_Ndst_Msrc_varsrc((dc), OP_stmdb, 1, 0, list_len, 0, (mem), __VA_ARGS__)
 
#define INSTR_CREATE_stmdb_priv(dc, mem, list_len, ...)
 
#define INSTR_CREATE_stmdb_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_stmib(dc, mem, list_len, ...)    instr_create_Ndst_Msrc_varsrc((dc), OP_stmib, 1, 0, list_len, 0, (mem), __VA_ARGS__)
 
#define INSTR_CREATE_stmib_priv(dc, mem, list_len, ...)
 
#define INSTR_CREATE_stmib_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_vld1_dup_8(dc, mem, list_len, ...)
 
#define INSTR_CREATE_vld1_dup_8_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_vld2_dup_8(dc, mem, list_len, ...)
 
#define INSTR_CREATE_vld2_dup_8_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_vld3_dup_8(dc, mem, list_len, ...)
 
#define INSTR_CREATE_vld3_dup_8_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_vld4_dup_8(dc, mem, list_len, ...)
 
#define INSTR_CREATE_vld4_dup_8_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_vldm(dc, mem, list_len, ...)    instr_create_Ndst_Msrc_vardst((dc), OP_vldm, 0, 1, list_len, 0, (mem), __VA_ARGS__)
 
#define INSTR_CREATE_vldm_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_vldmdb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_vstm(dc, mem, list_len, ...)    instr_create_Ndst_Msrc_varsrc((dc), OP_vstm, 1, 0, list_len, 0, (mem), __VA_ARGS__)
 
#define INSTR_CREATE_vstm_wb(dc, mem, list_len, ...)
 
#define INSTR_CREATE_vstmdb(dc, mem, list_len, ...)
 
Signature: (mem, Rm, list_len, ...)
#define INSTR_CREATE_vld1_dup_8_wbreg(dc, mem, Rm, list_len, ...)
 
#define INSTR_CREATE_vld2_dup_8_wbreg(dc, mem, Rm, list_len, ...)
 
#define INSTR_CREATE_vld3_dup_8_wbreg(dc, mem, Rm, list_len, ...)
 
#define INSTR_CREATE_vld4_dup_8_wbreg(dc, mem, Rm, list_len, ...)
 
Signature: (mem, imm, list_len, ...)
#define INSTR_CREATE_vld1_16(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld1_16_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld1_32(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld1_32_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld1_64(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld1_64_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld1_8(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld1_8_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld1_dup_16(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld1_dup_16_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld1_dup_32(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld1_dup_32_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld2_16(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld2_16_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld2_32(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld2_32_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld2_8(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld2_8_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld2_dup_16(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld2_dup_16_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld2_dup_32(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld2_dup_32_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld2_lane_8(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld2_lane_8_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld3_16(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld3_16_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld3_32(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld3_32_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld3_8(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld3_8_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld3_dup_16(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld3_dup_16_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld3_dup_32(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld3_dup_32_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld3_lane_8(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld3_lane_8_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld4_16(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld4_16_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld4_32(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld4_32_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld4_8(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld4_8_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld4_dup_16(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld4_dup_16_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld4_dup_32(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld4_dup_32_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld4_lane_8(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vld4_lane_8_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst1_16(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst1_16_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst1_32(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst1_32_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst1_64(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst1_64_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst1_8(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst1_8_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst2_16(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst2_16_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst2_32(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst2_32_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst2_8(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst2_8_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst3_16(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst3_16_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst3_32(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst3_32_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst3_8(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst3_8_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst3_lane_16(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst3_lane_16_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst3_lane_32(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst3_lane_32_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst3_lane_8(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst3_lane_8_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst4_16(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst4_16_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst4_32(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst4_32_wbimm(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst4_8(dc, mem, imm, list_len, ...)
 
#define INSTR_CREATE_vst4_8_wbimm(dc, mem, imm, list_len, ...)
 
Signature: (mem, imm, Rm, list_len, ...)
#define INSTR_CREATE_vld1_16_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld1_32_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld1_64_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld1_8_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld1_dup_16_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld1_dup_32_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld2_16_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld2_32_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld2_8_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld2_dup_16_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld2_dup_32_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld2_lane_8_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld3_16_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld3_32_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld3_8_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld3_dup_16_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld3_dup_32_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld3_lane_8_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld4_16_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld4_32_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld4_8_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld4_dup_16_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld4_dup_32_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vld4_lane_8_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst1_16_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst1_32_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst1_64_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst1_8_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst2_16_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst2_32_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst2_8_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst3_16_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst3_32_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst3_8_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst3_lane_16_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst3_lane_32_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst3_lane_8_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst4_16_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst4_32_wbreg(dc, mem, imm, Rm, list_len, ...)
 
#define INSTR_CREATE_vst4_8_wbreg(dc, mem, imm, Rm, list_len, ...)
 
Signature: (mem, imm, imm2, list_len, ...)
#define INSTR_CREATE_vld2_lane_16(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vld2_lane_16_wbimm(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vld2_lane_32(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vld2_lane_32_wbimm(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vld3_lane_16(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vld3_lane_16_wbimm(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vld3_lane_32(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vld3_lane_32_wbimm(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vld4_lane_16(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vld4_lane_16_wbimm(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vld4_lane_32(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vld4_lane_32_wbimm(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vst2_lane_16(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vst2_lane_16_wbimm(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vst2_lane_32(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vst2_lane_32_wbimm(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vst2_lane_8(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vst2_lane_8_wbimm(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vst4_lane_16(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vst4_lane_16_wbimm(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vst4_lane_32(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vst4_lane_32_wbimm(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vst4_lane_8(dc, mem, imm, imm2, list_len, ...)
 
#define INSTR_CREATE_vst4_lane_8_wbimm(dc, mem, imm, imm2, list_len, ...)
 
Signature: (mem, imm, imm2, Rm, list_len, ...)
#define INSTR_CREATE_vld2_lane_16_wbreg(dc, mem, imm, imm2, Rm, list_len, ...)
 
#define INSTR_CREATE_vld2_lane_32_wbreg(dc, mem, imm, imm2, Rm, list_len, ...)
 
#define INSTR_CREATE_vld3_lane_16_wbreg(dc, mem, imm, imm2, Rm, list_len, ...)
 
#define INSTR_CREATE_vld3_lane_32_wbreg(dc, mem, imm, imm2, Rm, list_len, ...)
 
#define INSTR_CREATE_vld4_lane_16_wbreg(dc, mem, imm, imm2, Rm, list_len, ...)
 
#define INSTR_CREATE_vld4_lane_32_wbreg(dc, mem, imm, imm2, Rm, list_len, ...)
 
#define INSTR_CREATE_vst2_lane_16_wbreg(dc, mem, imm, imm2, Rm, list_len, ...)
 
#define INSTR_CREATE_vst2_lane_32_wbreg(dc, mem, imm, imm2, Rm, list_len, ...)
 
#define INSTR_CREATE_vst2_lane_8_wbreg(dc, mem, imm, imm2, Rm, list_len, ...)
 
#define INSTR_CREATE_vst4_lane_16_wbreg(dc, mem, imm, imm2, Rm, list_len, ...)
 
#define INSTR_CREATE_vst4_lane_32_wbreg(dc, mem, imm, imm2, Rm, list_len, ...)
 
#define INSTR_CREATE_vst4_lane_8_wbreg(dc, mem, imm, imm2, Rm, list_len, ...)
 
Signature: (Ra, Rd, imm, imm2, cpreg)
#define INSTR_CREATE_mrrc(dc, Ra, Rd, imm, imm2, cpreg)    instr_create_2dst_3src((dc), OP_mrrc, (Ra), (Rd), (imm), (imm2), (cpreg))
 
#define INSTR_CREATE_mrrc2(dc, Ra, Rd, imm, imm2, cpreg)    instr_create_2dst_3src((dc), OP_mrrc2, (Ra), (Rd), (imm), (imm2), (cpreg))
 
Signature: (cpreg, Rn, Rt, imm, imm2)
#define INSTR_CREATE_mcrr(dc, cpreg, Rn, Rt, imm, imm2)    instr_create_1dst_4src((dc), OP_mcrr, (cpreg), (Rn), (Rt), (imm), (imm2))
 
#define INSTR_CREATE_mcrr2(dc, cpreg, Rn, Rt, imm, imm2)    instr_create_1dst_4src((dc), OP_mcrr2, (cpreg), (Rn), (Rt), (imm), (imm2))
 
Signature: (cpreg, cpreg2, imm, imm2, Rt)
#define INSTR_CREATE_mcr2(dc, cpreg, cpreg2, imm, imm2, Rt)    instr_create_2dst_3src((dc), OP_mcr2, (cpreg), (cpreg2), (imm), (imm2), (Rt))
 
Signature: (cpreg, imm, imm2, cpreg2, cpreg3)
#define INSTR_CREATE_cdp2(dc, cpreg, imm, imm2, cpreg2, cpreg3)    instr_create_1dst_4src((dc), OP_cdp2, (cpreg), (imm), (imm2), (cpreg2), (cpreg3))
 
Signature: (Rd, imm, imm2, cpreg, cpreg2, imm3)
#define INSTR_CREATE_mrc(dc, Rd, imm, imm2, cpreg, cpreg2, imm3)    instr_create_1dst_5src((dc), OP_mrc, (Rd), (imm), (imm2), (cpreg), (cpreg2), (imm3))
 
#define INSTR_CREATE_mrc2(dc, Rd, imm, imm2, cpreg, cpreg2, imm3)    instr_create_1dst_5src((dc), OP_mrc2, (Rd), (imm), (imm2), (cpreg), (cpreg2), (imm3))
 
Signature: (cpreg, cpreg2, imm, imm2, Rt, imm3)
#define INSTR_CREATE_mcr(dc, cpreg, cpreg2, imm, imm2, Rt, imm3)    instr_create_2dst_4src((dc), OP_mcr, (cpreg), (cpreg2), (imm), (imm2), (Rt), (imm3))
 
Signature: (cpreg, imm, imm2, cpreg2, cpreg3, imm3)
#define INSTR_CREATE_cdp(dc, cpreg, imm, imm2, cpreg2, cpreg3, imm3)
 
Signature: (cpreg, mem, imm)
#define INSTR_CREATE_ldc(dc, cpreg, mem, imm)    instr_create_1dst_2src((dc), OP_ldc, (cpreg), (mem), (imm))
 
#define INSTR_CREATE_ldcl(dc, cpreg, mem, imm)    instr_create_1dst_2src((dc), OP_ldcl, (cpreg), (mem), (imm))
 
Signature: (mem, imm, cpreg, imm2)
#define INSTR_CREATE_stc(dc, mem, imm, cpreg, imm2)    instr_create_1dst_3src((dc), OP_stc, (mem), (imm), (cpreg), (imm2))
 
#define INSTR_CREATE_stc2(dc, mem, imm, cpreg, imm2)    instr_create_1dst_3src((dc), OP_stc2, (mem), (imm), (cpreg), (imm2))
 
#define INSTR_CREATE_stc2_wbimm(dc, mem, imm, cpreg, imm2)
 
#define INSTR_CREATE_stc2l(dc, mem, imm, cpreg, imm2)    instr_create_1dst_3src((dc), OP_stc2l, (mem), (imm), (cpreg), (imm2))
 
#define INSTR_CREATE_stc2l_wbimm(dc, mem, imm, cpreg, imm2)
 
#define INSTR_CREATE_stc_wbimm(dc, mem, imm, cpreg, imm2)
 
#define INSTR_CREATE_stcl(dc, mem, imm, cpreg, imm2)    instr_create_1dst_3src((dc), OP_stcl, (mem), (imm), (cpreg), (imm2))
 
#define INSTR_CREATE_stcl_wbimm(dc, mem, imm, cpreg, imm2)
 
Signature: (cpreg, mem, imm, imm2)
#define INSTR_CREATE_ldc2_option(dc, cpreg, mem, imm, imm2)    instr_create_1dst_3src((dc), OP_ldc2, (cpreg), (mem), (imm), (imm2))
 
#define INSTR_CREATE_ldc2_wbimm(dc, cpreg, mem, imm, imm2)
 
#define INSTR_CREATE_ldc2l_option(dc, cpreg, mem, imm, imm2)    instr_create_1dst_3src((dc), OP_ldc2l, (cpreg), (mem), (imm), (imm2))
 
#define INSTR_CREATE_ldc2l_wbimm(dc, cpreg, mem, imm, imm2)
 
#define INSTR_CREATE_ldc_option(dc, cpreg, mem, imm, imm2)    instr_create_1dst_3src((dc), OP_ldc, (cpreg), (mem), (imm), (imm2))
 
#define INSTR_CREATE_ldc_wbimm(dc, cpreg, mem, imm, imm2)
 
#define INSTR_CREATE_ldcl_option(dc, cpreg, mem, imm, imm2)    instr_create_1dst_3src((dc), OP_ldcl, (cpreg), (mem), (imm), (imm2))
 
#define INSTR_CREATE_ldcl_wbimm(dc, cpreg, mem, imm, imm2)
 
Signature: (Rd, Vn)
#define INSTR_CREATE_vmov_s2g(dc, Rd, Vn)    instr_create_1dst_1src((dc), OP_vmov, (Rd), (Vn))
 
Signature: (Vd, Vm)
#define INSTR_CREATE_aesd_8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_aesd_8, (Vd), (Vm))
 
#define INSTR_CREATE_aese_8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_aese_8, (Vd), (Vm))
 
#define INSTR_CREATE_aesimc_8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_aesimc_8, (Vd), (Vm))
 
#define INSTR_CREATE_aesmc_8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_aesmc_8, (Vd), (Vm))
 
#define INSTR_CREATE_sha1h_32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_sha1h_32, (Vd), (Vm))
 
#define INSTR_CREATE_sha1su1_32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_sha1su1_32, (Vd), (Vm))
 
#define INSTR_CREATE_sha256su0_32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_sha256su0_32, (Vd), (Vm))
 
#define INSTR_CREATE_vabs_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vabs_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vabs_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vabs_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vabs_s16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vabs_s16, (Vd), (Vm))
 
#define INSTR_CREATE_vabs_s32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vabs_s32, (Vd), (Vm))
 
#define INSTR_CREATE_vabs_s8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vabs_s8, (Vd), (Vm))
 
#define INSTR_CREATE_vcls_s16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcls_s16, (Vd), (Vm))
 
#define INSTR_CREATE_vcls_s32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcls_s32, (Vd), (Vm))
 
#define INSTR_CREATE_vcls_s8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcls_s8, (Vd), (Vm))
 
#define INSTR_CREATE_vclz_i16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vclz_i16, (Vd), (Vm))
 
#define INSTR_CREATE_vclz_i32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vclz_i32, (Vd), (Vm))
 
#define INSTR_CREATE_vclz_i8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vclz_i8, (Vd), (Vm))
 
#define INSTR_CREATE_vcnt_8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcnt_8, (Vd), (Vm))
 
#define INSTR_CREATE_vcvt_f16_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvt_f16_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvt_f32_f16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvt_f32_f16, (Vd), (Vm))
 
#define INSTR_CREATE_vcvt_f32_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvt_f32_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vcvt_f32_s32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvt_f32_s32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvt_f32_u32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvt_f32_u32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvt_f64_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvt_f64_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvt_f64_s32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvt_f64_s32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvt_f64_u32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvt_f64_u32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvt_s32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvt_s32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvt_s32_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvt_s32_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vcvt_u32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvt_u32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvt_u32_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvt_u32_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vcvta_s32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvta_s32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvta_s32_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvta_s32_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vcvta_u32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvta_u32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvta_u32_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvta_u32_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtb_f16_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtb_f16_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtb_f16_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtb_f16_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtb_f32_f16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtb_f32_f16, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtb_f64_f16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtb_f64_f16, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtm_s32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtm_s32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtm_s32_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtm_s32_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtm_u32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtm_u32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtm_u32_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtm_u32_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtn_s32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtn_s32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtn_s32_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtn_s32_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtn_u32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtn_u32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtn_u32_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtn_u32_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtp_s32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtp_s32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtp_s32_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtp_s32_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtp_u32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtp_u32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtp_u32_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtp_u32_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtr_s32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtr_s32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtr_s32_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtr_s32_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtr_u32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtr_u32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtr_u32_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtr_u32_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtt_f16_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtt_f16_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtt_f16_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtt_f16_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtt_f32_f16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtt_f32_f16, (Vd), (Vm))
 
#define INSTR_CREATE_vcvtt_f64_f16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vcvtt_f64_f16, (Vd), (Vm))
 
#define INSTR_CREATE_vmovl_s16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vmovl_s16, (Vd), (Vm))
 
#define INSTR_CREATE_vmovl_s32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vmovl_s32, (Vd), (Vm))
 
#define INSTR_CREATE_vmovl_s8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vmovl_s8, (Vd), (Vm))
 
#define INSTR_CREATE_vmovl_u16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vmovl_u16, (Vd), (Vm))
 
#define INSTR_CREATE_vmovl_u32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vmovl_u32, (Vd), (Vm))
 
#define INSTR_CREATE_vmovl_u8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vmovl_u8, (Vd), (Vm))
 
#define INSTR_CREATE_vmovn_i16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vmovn_i16, (Vd), (Vm))
 
#define INSTR_CREATE_vmovn_i32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vmovn_i32, (Vd), (Vm))
 
#define INSTR_CREATE_vmovn_i64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vmovn_i64, (Vd), (Vm))
 
#define INSTR_CREATE_vmvn(dc, Vd, Vm)   instr_create_1dst_1src((dc), OP_vmvn, (Vd), (Vm))
 
#define INSTR_CREATE_vneg_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vneg_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vneg_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vneg_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vneg_s16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vneg_s16, (Vd), (Vm))
 
#define INSTR_CREATE_vneg_s32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vneg_s32, (Vd), (Vm))
 
#define INSTR_CREATE_vneg_s8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vneg_s8, (Vd), (Vm))
 
#define INSTR_CREATE_vpadal_s16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vpadal_s16, (Vd), (Vm))
 
#define INSTR_CREATE_vpadal_s32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vpadal_s32, (Vd), (Vm))
 
#define INSTR_CREATE_vpadal_s8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vpadal_s8, (Vd), (Vm))
 
#define INSTR_CREATE_vpadal_u16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vpadal_u16, (Vd), (Vm))
 
#define INSTR_CREATE_vpadal_u32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vpadal_u32, (Vd), (Vm))
 
#define INSTR_CREATE_vpadal_u8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vpadal_u8, (Vd), (Vm))
 
#define INSTR_CREATE_vpaddl_s16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vpaddl_s16, (Vd), (Vm))
 
#define INSTR_CREATE_vpaddl_s32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vpaddl_s32, (Vd), (Vm))
 
#define INSTR_CREATE_vpaddl_s8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vpaddl_s8, (Vd), (Vm))
 
#define INSTR_CREATE_vpaddl_u16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vpaddl_u16, (Vd), (Vm))
 
#define INSTR_CREATE_vpaddl_u32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vpaddl_u32, (Vd), (Vm))
 
#define INSTR_CREATE_vpaddl_u8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vpaddl_u8, (Vd), (Vm))
 
#define INSTR_CREATE_vqabs_s16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vqabs_s16, (Vd), (Vm))
 
#define INSTR_CREATE_vqabs_s32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vqabs_s32, (Vd), (Vm))
 
#define INSTR_CREATE_vqabs_s8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vqabs_s8, (Vd), (Vm))
 
#define INSTR_CREATE_vqmovn_s16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vqmovn_s16, (Vd), (Vm))
 
#define INSTR_CREATE_vqmovn_s32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vqmovn_s32, (Vd), (Vm))
 
#define INSTR_CREATE_vqmovn_s64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vqmovn_s64, (Vd), (Vm))
 
#define INSTR_CREATE_vqmovn_u16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vqmovn_u16, (Vd), (Vm))
 
#define INSTR_CREATE_vqmovn_u32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vqmovn_u32, (Vd), (Vm))
 
#define INSTR_CREATE_vqmovn_u64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vqmovn_u64, (Vd), (Vm))
 
#define INSTR_CREATE_vqmovun_s16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vqmovun_s16, (Vd), (Vm))
 
#define INSTR_CREATE_vqmovun_s32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vqmovun_s32, (Vd), (Vm))
 
#define INSTR_CREATE_vqmovun_s64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vqmovun_s64, (Vd), (Vm))
 
#define INSTR_CREATE_vqneg_s16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vqneg_s16, (Vd), (Vm))
 
#define INSTR_CREATE_vqneg_s32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vqneg_s32, (Vd), (Vm))
 
#define INSTR_CREATE_vqneg_s8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vqneg_s8, (Vd), (Vm))
 
#define INSTR_CREATE_vrecpe_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrecpe_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vrecpe_u32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrecpe_u32, (Vd), (Vm))
 
#define INSTR_CREATE_vrev16_16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrev16_16, (Vd), (Vm))
 
#define INSTR_CREATE_vrev16_8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrev16_8, (Vd), (Vm))
 
#define INSTR_CREATE_vrev32_16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrev32_16, (Vd), (Vm))
 
#define INSTR_CREATE_vrev32_32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrev32_32, (Vd), (Vm))
 
#define INSTR_CREATE_vrev32_8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrev32_8, (Vd), (Vm))
 
#define INSTR_CREATE_vrev64_16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrev64_16, (Vd), (Vm))
 
#define INSTR_CREATE_vrev64_32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrev64_32, (Vd), (Vm))
 
#define INSTR_CREATE_vrev64_8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrev64_8, (Vd), (Vm))
 
#define INSTR_CREATE_vrinta_f32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrinta_f32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vrinta_f64_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrinta_f64_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vrintm_f32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrintm_f32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vrintm_f64_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrintm_f64_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vrintn_f32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrintn_f32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vrintn_f64_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrintn_f64_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vrintp_f32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrintp_f32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vrintp_f64_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrintp_f64_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vrintr_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrintr_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vrintr_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrintr_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vrintx_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrintx_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vrintx_f32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrintx_f32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vrintx_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrintx_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vrintz_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrintz_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vrintz_f32_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrintz_f32_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vrintz_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrintz_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vrsqrte_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrsqrte_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vrsqrte_u32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vrsqrte_u32, (Vd), (Vm))
 
#define INSTR_CREATE_vsqrt_f32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vsqrt_f32, (Vd), (Vm))
 
#define INSTR_CREATE_vsqrt_f64(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vsqrt_f64, (Vd), (Vm))
 
#define INSTR_CREATE_vswp(dc, Vd, Vm)   instr_create_1dst_1src((dc), OP_vswp, (Vd), (Vm))
 
#define INSTR_CREATE_vtrn_16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vtrn_16, (Vd), (Vm))
 
#define INSTR_CREATE_vtrn_32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vtrn_32, (Vd), (Vm))
 
#define INSTR_CREATE_vtrn_8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vtrn_8, (Vd), (Vm))
 
#define INSTR_CREATE_vuzp_16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vuzp_16, (Vd), (Vm))
 
#define INSTR_CREATE_vuzp_32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vuzp_32, (Vd), (Vm))
 
#define INSTR_CREATE_vuzp_8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vuzp_8, (Vd), (Vm))
 
#define INSTR_CREATE_vzip_16(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vzip_16, (Vd), (Vm))
 
#define INSTR_CREATE_vzip_32(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vzip_32, (Vd), (Vm))
 
#define INSTR_CREATE_vzip_8(dc, Vd, Vm)    instr_create_1dst_1src((dc), OP_vzip_8, (Vd), (Vm))
 
Signature: (Vd, Rt)
#define INSTR_CREATE_vdup_16(dc, Vd, Rt)    instr_create_1dst_1src((dc), OP_vdup_16, (Vd), (Rt))
 
#define INSTR_CREATE_vdup_32(dc, Vd, Rt)    instr_create_1dst_1src((dc), OP_vdup_32, (Vd), (Rt))
 
#define INSTR_CREATE_vdup_8(dc, Vd, Rt)    instr_create_1dst_1src((dc), OP_vdup_8, (Vd), (Rt))
 
#define INSTR_CREATE_vmov_g2s(dc, Vd, Rt)    instr_create_1dst_1src((dc), OP_vmov, (Vd), (Rt))
 
Signature: (Ra, Rd, Vm)
#define INSTR_CREATE_vmov_s2gg(dc, Ra, Rd, Vm)    instr_create_2dst_1src((dc), OP_vmov, (Ra), (Rd), (Vm))
 
Signature: (Vd, Vn, Vm)
#define INSTR_CREATE_sha1c_32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_sha1c_32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_sha1m_32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_sha1m_32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_sha1p_32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_sha1p_32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_sha1su0_32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_sha1su0_32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_sha256h2_32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_sha256h2_32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_sha256h_32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_sha256h_32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_sha256su1_32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_sha256su1_32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaba_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaba_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaba_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaba_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaba_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaba_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaba_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaba_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaba_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaba_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaba_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaba_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabal_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabal_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabal_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabal_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabal_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabal_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabal_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabal_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabal_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabal_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabal_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabal_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabd_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabd_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabd_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabd_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabd_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabd_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabd_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabd_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabd_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabd_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabd_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabd_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabdl_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabdl_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabdl_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabdl_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabdl_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabdl_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabdl_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabdl_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabdl_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabdl_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vabdl_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vabdl_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vacge_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vacge_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vacgt_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vacgt_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vadd_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vadd_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vadd_f64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vadd_f64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vadd_i16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vadd_i16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vadd_i32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vadd_i32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vadd_i64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vadd_i64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vadd_i8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vadd_i8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaddhn_i16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaddhn_i16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaddhn_i32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaddhn_i32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaddhn_i64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaddhn_i64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaddl_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaddl_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaddl_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaddl_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaddl_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaddl_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaddl_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaddl_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaddl_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaddl_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaddl_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaddl_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaddw_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaddw_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaddw_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaddw_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaddw_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaddw_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaddw_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaddw_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaddw_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaddw_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vaddw_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vaddw_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vand(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vand, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vbic(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vbic, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vbif(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vbif, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vbit(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vbit, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vbsl(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vbsl, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vcge_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vcge_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vcge_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vcge_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vcge_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vcge_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vcgt_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vcgt_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vcgt_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vcgt_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vcgt_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vcgt_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vdiv_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vdiv_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vdiv_f64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vdiv_f64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_veor(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_veor, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vfma_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vfma_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vfma_f64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vfma_f64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vfms_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vfms_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vfms_f64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vfms_f64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vfnma_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vfnma_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vfnma_f64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vfnma_f64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vfnms_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vfnms_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vfnms_f64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vfnms_f64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vhadd_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vhadd_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vhadd_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vhadd_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vhadd_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vhadd_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vhadd_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vhadd_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vhadd_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vhadd_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vhadd_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vhadd_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vhsub_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vhsub_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vhsub_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vhsub_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vhsub_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vhsub_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vhsub_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vhsub_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vhsub_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vhsub_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vhsub_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vhsub_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmax_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmax_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmax_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmax_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmax_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmax_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmax_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmax_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmax_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmax_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmax_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmax_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmax_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmax_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmaxnm_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmaxnm_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmaxnm_f64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmaxnm_f64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmin_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmin_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmin_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmin_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmin_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmin_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmin_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmin_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmin_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmin_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmin_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmin_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmin_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmin_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vminnm_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vminnm_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vminnm_f64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vminnm_f64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmla_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmla_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmla_f64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmla_f64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmla_i16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmla_i16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmla_i32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmla_i32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmla_i8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmla_i8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmlal_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmlal_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmlal_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmlal_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmlal_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmlal_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmlal_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmlal_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmlal_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmlal_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmlal_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmlal_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmls_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmls_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmls_f64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmls_f64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmls_i16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmls_i16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmls_i32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmls_i32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmls_i8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmls_i8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmlsl_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmlsl_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmlsl_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmlsl_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmlsl_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmlsl_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmlsl_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmlsl_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmlsl_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmlsl_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmlsl_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmlsl_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmul_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmul_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmul_f64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmul_f64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmul_i16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmul_i16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmul_i32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmul_i32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmul_i8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmul_i8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmul_p32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmul_p32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmul_p8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmul_p8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmull_p32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmull_p32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmull_p8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmull_p8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmull_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmull_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmull_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmull_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmull_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmull_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmull_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmull_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmull_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmull_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vmull_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vmull_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vnmla_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vnmla_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vnmla_f64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vnmla_f64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vnmls_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vnmls_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vnmls_f64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vnmls_f64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vnmul_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vnmul_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vnmul_f64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vnmul_f64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vorn(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vorn, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vorr(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vorr, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpadd_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpadd_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpadd_i16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpadd_i16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpadd_i32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpadd_i32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpadd_i8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpadd_i8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpmax_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpmax_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpmax_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpmax_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpmax_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpmax_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpmax_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpmax_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpmax_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpmax_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpmax_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpmax_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpmax_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpmax_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpmin_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpmin_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpmin_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpmin_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpmin_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpmin_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpmin_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpmin_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpmin_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpmin_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpmin_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpmin_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vpmin_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vpmin_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqadd_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqadd_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqadd_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqadd_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqadd_s64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqadd_s64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqadd_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqadd_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqadd_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqadd_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqadd_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqadd_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqadd_u64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqadd_u64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqadd_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqadd_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqdmlal_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqdmlal_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqdmlal_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqdmlal_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqdmlsl_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqdmlsl_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqdmlsl_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqdmlsl_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqdmulh_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqdmulh_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqdmulh_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqdmulh_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqdmull_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqdmull_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqdmull_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqdmull_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqrdmulh_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqrdmulh_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqrdmulh_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqrdmulh_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqrshl_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqrshl_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqrshl_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqrshl_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqrshl_s64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqrshl_s64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqrshl_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqrshl_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqrshl_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqrshl_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqrshl_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqrshl_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqrshl_u64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqrshl_u64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqrshl_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqrshl_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqsub_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqsub_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqsub_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqsub_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqsub_s64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqsub_s64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqsub_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqsub_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqsub_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqsub_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqsub_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqsub_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqsub_u64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqsub_u64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vqsub_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vqsub_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vraddhn_i16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vraddhn_i16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vraddhn_i32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vraddhn_i32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vraddhn_i64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vraddhn_i64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrecps_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrecps_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrhadd_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrhadd_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrhadd_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrhadd_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrhadd_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrhadd_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrhadd_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrhadd_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrhadd_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrhadd_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrhadd_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrhadd_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrshl_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrshl_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrshl_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrshl_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrshl_s64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrshl_s64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrshl_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrshl_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrshl_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrshl_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrshl_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrshl_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrshl_u64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrshl_u64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrshl_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrshl_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrsqrts_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrsqrts_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrsubhn_i16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrsubhn_i16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrsubhn_i32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrsubhn_i32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vrsubhn_i64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vrsubhn_i64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vshl_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vshl_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vshl_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vshl_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vshl_s64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vshl_s64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vshl_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vshl_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vshl_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vshl_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vshl_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vshl_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vshl_u64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vshl_u64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vshl_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vshl_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsub_f32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsub_f32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsub_f64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsub_f64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsub_i16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsub_i16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsub_i32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsub_i32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsub_i64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsub_i64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsub_i8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsub_i8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsubhn_i16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsubhn_i16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsubhn_i32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsubhn_i32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsubhn_i64(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsubhn_i64, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsubl_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsubl_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsubl_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsubl_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsubl_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsubl_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsubl_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsubl_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsubl_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsubl_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsubl_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsubl_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsubw_s16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsubw_s16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsubw_s32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsubw_s32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsubw_s8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsubw_s8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsubw_u16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsubw_u16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsubw_u32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsubw_u32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vsubw_u8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vsubw_u8, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vtst_16(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vtst_16, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vtst_32(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vtst_32, (Vd), (Vn), (Vm))
 
#define INSTR_CREATE_vtst_8(dc, Vd, Vn, Vm)    instr_create_1dst_2src((dc), OP_vtst_8, (Vd), (Vn), (Vm))
 
Signature: (Vd, Rt, Rt2)
#define INSTR_CREATE_vmov_gg2s(dc, Vd, Rt, Rt2)    instr_create_1dst_2src((dc), OP_vmov, (Vd), (Rt), (Rt2))
 
Signature: (Rd, Rd2, Vt, Vt2)
#define INSTR_CREATE_vmov_ss2gg(dc, Rd, Rd2, Vt, Vt2)    instr_create_2dst_2src((dc), OP_vmov, (Rd), (Rd2), (Vt), (Vt2))
 
Signature: (Vd, Vd2, Rt, Rt2)
#define INSTR_CREATE_vmov_gg2ss(dc, Vd, Vd2, Rt, Rt2)    instr_create_2dst_2src((dc), OP_vmov, (Vd), (Vd2), (Rt), (Rt2))
 
Signature: (Vd, imm)
#define INSTR_CREATE_vbic_i16(dc, Vd, imm)    instr_create_1dst_1src((dc), OP_vbic_i16, (Vd), (imm))
 
#define INSTR_CREATE_vbic_i32(dc, Vd, imm)    instr_create_1dst_1src((dc), OP_vbic_i32, (Vd), (imm))
 
#define INSTR_CREATE_vmov_i16(dc, Vd, imm)    instr_create_1dst_1src((dc), OP_vmov_i16, (Vd), (imm))
 
#define INSTR_CREATE_vmov_i32(dc, Vd, imm)    instr_create_1dst_1src((dc), OP_vmov_i32, (Vd), (imm))
 
#define INSTR_CREATE_vmov_i64(dc, Vd, imm)    instr_create_1dst_1src((dc), OP_vmov_i64, (Vd), (imm))
 
#define INSTR_CREATE_vmov_i8(dc, Vd, imm)    instr_create_1dst_1src((dc), OP_vmov_i8, (Vd), (imm))
 
#define INSTR_CREATE_vmvn_i16(dc, Vd, imm)    instr_create_1dst_1src((dc), OP_vmvn_i16, (Vd), (imm))
 
#define INSTR_CREATE_vmvn_i32(dc, Vd, imm)    instr_create_1dst_1src((dc), OP_vmvn_i32, (Vd), (imm))
 
#define INSTR_CREATE_vorr_i16(dc, Vd, imm)    instr_create_1dst_1src((dc), OP_vorr_i16, (Vd), (imm))
 
#define INSTR_CREATE_vorr_i32(dc, Vd, imm)    instr_create_1dst_1src((dc), OP_vorr_i32, (Vd), (imm))
 
Signature: (Vd, Vm_or_imm)
#define INSTR_CREATE_vmov_f32(dc, Vd, Vm_or_imm)    instr_create_1dst_1src((dc), OP_vmov_f32, (Vd), (Vm_or_imm))
 
#define INSTR_CREATE_vmov_f64(dc, Vd, Vm_or_imm)    instr_create_1dst_1src((dc), OP_vmov_f64, (Vd), (Vm_or_imm))
 
Signature: (Vt, Vm_or_imm)
#define INSTR_CREATE_vcmp_f32(dc, Vt, Vm_or_imm)
 
#define INSTR_CREATE_vcmp_f64(dc, Vt, Vm_or_imm)
 
#define INSTR_CREATE_vcmpe_f32(dc, Vt, Vm_or_imm)
 
#define INSTR_CREATE_vcmpe_f64(dc, Vt, Vm_or_imm)
 
Signature: (Rd, Vn, imm)
#define INSTR_CREATE_vmov_32_s2g(dc, Rd, Vn, imm)    instr_create_1dst_2src((dc), OP_vmov_32, (Rd), (Vn), (imm))
 
#define INSTR_CREATE_vmov_s16(dc, Rd, Vn, imm)    instr_create_1dst_2src((dc), OP_vmov_s16, (Rd), (Vn), (imm))
 
#define INSTR_CREATE_vmov_s8(dc, Rd, Vn, imm)    instr_create_1dst_2src((dc), OP_vmov_s8, (Rd), (Vn), (imm))
 
#define INSTR_CREATE_vmov_u16(dc, Rd, Vn, imm)    instr_create_1dst_2src((dc), OP_vmov_u16, (Rd), (Vn), (imm))
 
#define INSTR_CREATE_vmov_u8(dc, Rd, Vn, imm)    instr_create_1dst_2src((dc), OP_vmov_u8, (Rd), (Vn), (imm))
 
Signature: (Vd, Vm, imm)
#define INSTR_CREATE_vcle_f32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcle_f32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcle_s16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcle_s16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcle_s32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcle_s32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcle_s8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcle_s8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vclt_f32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vclt_f32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vclt_s16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vclt_s16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vclt_s32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vclt_s32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vclt_s8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vclt_s8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_f32_s16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_f32_s16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_f32_s32_imm(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_f32_s32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_f32_u16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_f32_u16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_f32_u32_imm(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_f32_u32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_f64_s16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_f64_s16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_f64_s32_imm(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_f64_s32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_f64_u16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_f64_u16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_f64_u32_imm(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_f64_u32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_s16_f32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_s16_f32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_s16_f64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_s16_f64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_s32_f32_imm(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_s32_f32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_s32_f64_imm(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_s32_f64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_u16_f32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_u16_f32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_u16_f64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_u16_f64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_u32_f32_imm(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_u32_f32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vcvt_u32_f64_imm(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vcvt_u32_f64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vdup_16_imm(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vdup_16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vdup_32_imm(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vdup_32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vdup_8_imm(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vdup_8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqrshrn_s16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqrshrn_s16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqrshrn_s32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqrshrn_s32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqrshrn_s64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqrshrn_s64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqrshrn_u16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqrshrn_u16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqrshrn_u32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqrshrn_u32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqrshrn_u64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqrshrn_u64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqrshrun_s16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqrshrun_s16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqrshrun_s32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqrshrun_s32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqrshrun_s64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqrshrun_s64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqshlu_s16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqshlu_s16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqshlu_s32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqshlu_s32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqshlu_s64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqshlu_s64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqshlu_s8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqshlu_s8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqshrn_s16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqshrn_s16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqshrn_s32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqshrn_s32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqshrn_s64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqshrn_s64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqshrn_u16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqshrn_u16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqshrn_u32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqshrn_u32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqshrn_u64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqshrn_u64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqshrun_s16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqshrun_s16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqshrun_s32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqshrun_s32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vqshrun_s64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vqshrun_s64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrshr_s16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrshr_s16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrshr_s32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrshr_s32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrshr_s64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrshr_s64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrshr_s8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrshr_s8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrshr_u16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrshr_u16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrshr_u32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrshr_u32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrshr_u64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrshr_u64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrshr_u8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrshr_u8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrshrn_i16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrshrn_i16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrshrn_i32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrshrn_i32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrshrn_i64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrshrn_i64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrsra_s16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrsra_s16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrsra_s32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrsra_s32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrsra_s64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrsra_s64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrsra_s8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrsra_s8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrsra_u16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrsra_u16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrsra_u32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrsra_u32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrsra_u64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrsra_u64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vrsra_u8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vrsra_u8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshl_i16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshl_i16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshl_i32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshl_i32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshl_i64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshl_i64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshl_i8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshl_i8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshll_i16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshll_i16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshll_i32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshll_i32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshll_i8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshll_i8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshll_s16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshll_s16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshll_s32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshll_s32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshll_s8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshll_s8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshll_u16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshll_u16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshll_u32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshll_u32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshll_u8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshll_u8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshr_s16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshr_s16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshr_s32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshr_s32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshr_s64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshr_s64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshr_s8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshr_s8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshr_u16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshr_u16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshr_u32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshr_u32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshr_u64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshr_u64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshr_u8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshr_u8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshrn_i16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshrn_i16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshrn_i32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshrn_i32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vshrn_i64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vshrn_i64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsli_16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsli_16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsli_32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsli_32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsli_64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsli_64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsli_8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsli_8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsra_s16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsra_s16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsra_s32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsra_s32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsra_s64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsra_s64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsra_s8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsra_s8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsra_u16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsra_u16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsra_u32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsra_u32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsra_u64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsra_u64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsra_u8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsra_u8, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsri_16(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsri_16, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsri_32(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsri_32, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsri_64(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsri_64, (Vd), (Vm), (imm))
 
#define INSTR_CREATE_vsri_8(dc, Vd, Vm, imm)    instr_create_1dst_2src((dc), OP_vsri_8, (Vd), (Vm), (imm))
 
Signature: (Vd, Rt, imm)
#define INSTR_CREATE_vmov_16(dc, Vd, Rt, imm)    instr_create_1dst_2src((dc), OP_vmov_16, (Vd), (Rt), (imm))
 
#define INSTR_CREATE_vmov_32_g2s(dc, Vd, Rt, imm)    instr_create_1dst_2src((dc), OP_vmov_32, (Vd), (Rt), (imm))
 
#define INSTR_CREATE_vmov_8(dc, Vd, Rt, imm)    instr_create_1dst_2src((dc), OP_vmov_8, (Vd), (Rt), (imm))
 
Signature: (Vd, Vn, Vm_or_imm)
#define INSTR_CREATE_vceq_f32(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vceq_f32, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vceq_i16(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vceq_i16, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vceq_i32(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vceq_i32, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vceq_i8(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vceq_i8, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vcge_f32(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vcge_f32, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vcge_s16(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vcge_s16, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vcge_s32(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vcge_s32, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vcge_s8(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vcge_s8, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vcgt_f32(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vcgt_f32, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vcgt_s16(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vcgt_s16, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vcgt_s32(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vcgt_s32, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vcgt_s8(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vcgt_s8, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vqshl_s16(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vqshl_s16, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vqshl_s32(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vqshl_s32, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vqshl_s64(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vqshl_s64, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vqshl_s8(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vqshl_s8, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vqshl_u16(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vqshl_u16, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vqshl_u32(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vqshl_u32, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vqshl_u64(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vqshl_u64, (Vd), (Vn), (Vm_or_imm))
 
#define INSTR_CREATE_vqshl_u8(dc, Vd, Vn, Vm_or_imm)    instr_create_1dst_2src((dc), OP_vqshl_u8, (Vd), (Vn), (Vm_or_imm))
 
Signature: (Vd, Vn, Vm, imm)
#define INSTR_CREATE_vext(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vext, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmla_f32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmla_f32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmla_i16_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmla_i16, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmla_i32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmla_i32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmlal_s16_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmlal_s16, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmlal_s32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmlal_s32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmlal_u16_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmlal_u16, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmlal_u32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmlal_u32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmls_f32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmls_f32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmls_i16_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmls_i16, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmls_i32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmls_i32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmlsl_s16_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmlsl_s16, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmlsl_s32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmlsl_s32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmlsl_u16_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmlsl_u16, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmlsl_u32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmlsl_u32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmul_f32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmul_f32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmul_i16_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmul_i16, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmul_i32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmul_i32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmull_s16_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmull_s16, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmull_s32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmull_s32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmull_u16_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmull_u16, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vmull_u32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vmull_u32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vqdmlal_s16_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vqdmlal_s16, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vqdmlal_s32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vqdmlal_s32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vqdmlsl_s16_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vqdmlsl_s16, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vqdmlsl_s32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vqdmlsl_s32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vqdmulh_s16_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vqdmulh_s16, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vqdmulh_s32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vqdmulh_s32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vqdmull_s16_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vqdmull_s16, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vqdmull_s32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vqdmull_s32, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vqrdmulh_s16_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vqrdmulh_s16, (Vd), (Vn), (Vm), (imm))
 
#define INSTR_CREATE_vqrdmulh_s32_imm(dc, Vd, Vn, Vm, imm)    instr_create_1dst_3src((dc), OP_vqrdmulh_s32, (Vd), (Vn), (Vm), (imm))
 
Signature: (Vd, imm, Vn, Vm)
#define INSTR_CREATE_vsel_eq_f32(dc, Vd, imm, Vn, Vm)    instr_create_1dst_3src((dc), OP_vsel_eq_f32, (Vd), (imm), (Vn), (Vm))
 
#define INSTR_CREATE_vsel_eq_f64(dc, Vd, imm, Vn, Vm)    instr_create_1dst_3src((dc), OP_vsel_eq_f64, (Vd), (imm), (Vn), (Vm))
 
#define INSTR_CREATE_vsel_ge_f32(dc, Vd, imm, Vn, Vm)    instr_create_1dst_3src((dc), OP_vsel_ge_f32, (Vd), (imm), (Vn), (Vm))
 
#define INSTR_CREATE_vsel_ge_f64(dc, Vd, imm, Vn, Vm)    instr_create_1dst_3src((dc), OP_vsel_ge_f64, (Vd), (imm), (Vn), (Vm))
 
#define INSTR_CREATE_vsel_gt_f32(dc, Vd, imm, Vn, Vm)    instr_create_1dst_3src((dc), OP_vsel_gt_f32, (Vd), (imm), (Vn), (Vm))
 
#define INSTR_CREATE_vsel_gt_f64(dc, Vd, imm, Vn, Vm)    instr_create_1dst_3src((dc), OP_vsel_gt_f64, (Vd), (imm), (Vn), (Vm))
 
#define INSTR_CREATE_vsel_vs_f32(dc, Vd, imm, Vn, Vm)    instr_create_1dst_3src((dc), OP_vsel_vs_f32, (Vd), (imm), (Vn), (Vm))
 
#define INSTR_CREATE_vsel_vs_f64(dc, Vd, imm, Vn, Vm)    instr_create_1dst_3src((dc), OP_vsel_vs_f64, (Vd), (imm), (Vn), (Vm))
 
Signature: (Vd, mem)
#define INSTR_CREATE_vldr(dc, Vd, mem)   instr_create_1dst_1src((dc), OP_vldr, (Vd), (mem))
 
Signature: (mem, Vt)
#define INSTR_CREATE_vstr(dc, mem, Vt)   instr_create_1dst_1src((dc), OP_vstr, (mem), (Vt))
 
Signature: (Vd, mem, imm)
#define INSTR_CREATE_vld1_lane_8(dc, Vd, mem, imm)    instr_create_1dst_2src((dc), OP_vld1_lane_8, (Vd), (mem), (imm))
 
#define INSTR_CREATE_vld1_lane_8_wbimm(dc, Vd, mem, imm)
 
Signature: (mem, Vt, imm)
#define INSTR_CREATE_vst1_lane_8(dc, mem, Vt, imm)    instr_create_1dst_2src((dc), OP_vst1_lane_8, (mem), (Vt), (imm))
 
#define INSTR_CREATE_vst1_lane_8_wbimm(dc, mem, Vt, imm)
 
Signature: (Vd, mem, imm, Rm)
#define INSTR_CREATE_vld1_lane_8_wbreg(dc, Vd, mem, imm, Rm)
 
Signature: (Vd, mem, imm, imm2)
#define INSTR_CREATE_vld1_lane_16(dc, Vd, mem, imm, imm2)    instr_create_1dst_3src((dc), OP_vld1_lane_16, (Vd), (mem), (imm), (imm2))
 
#define INSTR_CREATE_vld1_lane_16_wbimm(dc, Vd, mem, imm, imm2)
 
#define INSTR_CREATE_vld1_lane_32(dc, Vd, mem, imm, imm2)    instr_create_1dst_3src((dc), OP_vld1_lane_32, (Vd), (mem), (imm), (imm2))
 
#define INSTR_CREATE_vld1_lane_32_wbimm(dc, Vd, mem, imm, imm2)
 
Signature: (mem, Vt, imm, Rm)
#define INSTR_CREATE_vst1_lane_8_wbreg(dc, mem, Vt, imm, Rm)
 
Signature: (mem, Vt, imm, imm2)
#define INSTR_CREATE_vst1_lane_16(dc, mem, Vt, imm, imm2)    instr_create_1dst_3src((dc), OP_vst1_lane_16, (mem), (Vt), (imm), (imm2))
 
#define INSTR_CREATE_vst1_lane_16_wbimm(dc, mem, Vt, imm, imm2)
 
#define INSTR_CREATE_vst1_lane_32(dc, mem, Vt, imm, imm2)    instr_create_1dst_3src((dc), OP_vst1_lane_32, (mem), (Vt), (imm), (imm2))
 
#define INSTR_CREATE_vst1_lane_32_wbimm(dc, mem, Vt, imm, imm2)
 
Signature: (Vd, mem, imm, imm2, Rm)
#define INSTR_CREATE_vld1_lane_16_wbreg(dc, Vd, mem, imm, imm2, Rm)
 
#define INSTR_CREATE_vld1_lane_32_wbreg(dc, Vd, mem, imm, imm2, Rm)
 
Signature: (mem, Vt, imm, imm2, Rm)
#define INSTR_CREATE_vst1_lane_16_wbreg(dc, mem, Vt, imm, imm2, Rm)
 
#define INSTR_CREATE_vst1_lane_32_wbreg(dc, mem, Vt, imm, imm2, Rm)
 
Signature: (Vd, Vm, list_len, ...)
#define INSTR_CREATE_vtbl_8(dc, Vd, Vm, list_len, ...)
 
#define INSTR_CREATE_vtbx_8(dc, Vd, Vm, list_len, ...)
 

Enumerations

enum  {
  DR_VG_NUM_ARGS = 5,
  DR_NOTE_ANNOTATION = DR_NOTE_FIRST_RESERVED + 1 ,
  DR_NOTE_CLEAN_CALL_END,
  DR_NOTE_REG_BARRIER ,
  EFLAGS_CF = 0x00000001,
  EFLAGS_PF = 0x00000004,
  EFLAGS_AF = 0x00000010,
  EFLAGS_ZF = 0x00000040,
  EFLAGS_SF = 0x00000080,
  EFLAGS_DF = 0x00000400,
  EFLAGS_OF = 0x00000800,
  EFLAGS_ARITH = EFLAGS_CF | EFLAGS_PF | EFLAGS_AF | EFLAGS_ZF | EFLAGS_SF | EFLAGS_OF,
  DR_DMB_OSHLD = 1,
  DR_DMB_OSHST = 2,
  DR_DMB_OSH = 3,
  DR_DMB_NSHLD = 5,
  DR_DMB_NSHST = 6,
  DR_DMB_NSH = 7,
  DR_DMB_ISHLD = 9,
  DR_DMB_ISHST = 10,
  DR_DMB_ISH = 11,
  DR_DMB_LD = 13,
  DR_DMB_ST = 14,
  DR_DMB_SY = 15 ,
  OP_UNDECODED,
  OP_CONTD,
  OP_LABEL,
  OP_adc,
  OP_adcs,
  OP_add,
  OP_adds,
  OP_addw,
  OP_aesd_8,
  OP_aese_8,
  OP_aesimc_8,
  OP_aesmc_8,
  OP_and,
  OP_ands,
  OP_asr,
  OP_asrs,
  OP_b,
  OP_b_short,
  OP_bfc,
  OP_bfi,
  OP_bic,
  OP_bics,
  OP_bkpt,
  OP_bl,
  OP_blx,
  OP_blx_ind,
  OP_bx,
  OP_bxj,
  OP_cbnz,
  OP_cbz,
  OP_cdp,
  OP_cdp2,
  OP_clrex,
  OP_clz,
  OP_cmn,
  OP_cmp,
  OP_cps,
  OP_cpsid,
  OP_cpsie,
  OP_crc32b,
  OP_crc32cb,
  OP_crc32h,
  OP_crc32ch,
  OP_crc32w,
  OP_crc32cw,
  OP_dbg,
  OP_dcps1,
  OP_dcps2,
  OP_dcps3,
  OP_dmb,
  OP_dsb,
  OP_enterx,
  OP_eor,
  OP_eors,
  OP_eret,
  OP_hlt,
  OP_hvc,
  OP_isb,
  OP_it,
  OP_lda,
  OP_ldab,
  OP_ldaex,
  OP_ldaexb,
  OP_ldaexd,
  OP_ldaexh,
  OP_ldah,
  OP_ldc,
  OP_ldc2,
  OP_ldc2l,
  OP_ldcl,
  OP_ldm,
  OP_ldm_priv,
  OP_ldmda,
  OP_ldmda_priv,
  OP_ldmdb,
  OP_ldmdb_priv,
  OP_ldmib,
  OP_ldmib_priv,
  OP_ldr,
  OP_ldrb,
  OP_ldrbt,
  OP_ldrd,
  OP_ldrex,
  OP_ldrexb,
  OP_ldrexd,
  OP_ldrexh,
  OP_ldrh,
  OP_ldrht,
  OP_ldrsb,
  OP_ldrsbt,
  OP_ldrsh,
  OP_ldrsht,
  OP_ldrt,
  OP_leavex,
  OP_lsl,
  OP_lsls,
  OP_lsr,
  OP_lsrs,
  OP_mcr,
  OP_mcr2,
  OP_mcrr,
  OP_mcrr2,
  OP_mla,
  OP_mlas,
  OP_mls,
  OP_mov,
  OP_movs,
  OP_movt,
  OP_movw,
  OP_mrc,
  OP_mrc2,
  OP_mrrc,
  OP_mrrc2,
  OP_mrs,
  OP_mrs_priv,
  OP_msr,
  OP_msr_priv,
  OP_mul,
  OP_muls,
  OP_mvn,
  OP_mvns,
  OP_nop,
  OP_orn,
  OP_orns,
  OP_orr,
  OP_orrs,
  OP_pkhbt,
  OP_pkhtb,
  OP_pld,
  OP_pldw,
  OP_pli,
  OP_qadd,
  OP_qadd16,
  OP_qadd8,
  OP_qasx,
  OP_qdadd,
  OP_qdsub,
  OP_qsax,
  OP_qsub,
  OP_qsub16,
  OP_qsub8,
  OP_rbit,
  OP_rev,
  OP_rev16,
  OP_revsh,
  OP_rfe,
  OP_rfeda,
  OP_rfedb,
  OP_rfeib,
  OP_ror,
  OP_rors,
  OP_rrx,
  OP_rrxs,
  OP_rsb,
  OP_rsbs,
  OP_rsc,
  OP_rscs,
  OP_sadd16,
  OP_sadd8,
  OP_sasx,
  OP_sbc,
  OP_sbcs,
  OP_sbfx,
  OP_sdiv,
  OP_sel,
  OP_setend,
  OP_sev,
  OP_sevl,
  OP_sha1c_32,
  OP_sha1h_32,
  OP_sha1m_32,
  OP_sha1p_32,
  OP_sha1su0_32,
  OP_sha1su1_32,
  OP_sha256h2_32,
  OP_sha256h_32,
  OP_sha256su0_32,
  OP_sha256su1_32,
  OP_shadd16,
  OP_shadd8,
  OP_shasx,
  OP_shsax,
  OP_shsub16,
  OP_shsub8,
  OP_smc,
  OP_smlabb,
  OP_smlabt,
  OP_smlad,
  OP_smladx,
  OP_smlal,
  OP_smlalbb,
  OP_smlalbt,
  OP_smlald,
  OP_smlaldx,
  OP_smlals,
  OP_smlaltb,
  OP_smlaltt,
  OP_smlatb,
  OP_smlatt,
  OP_smlawb,
  OP_smlawt,
  OP_smlsd,
  OP_smlsdx,
  OP_smlsld,
  OP_smlsldx,
  OP_smmla,
  OP_smmlar,
  OP_smmls,
  OP_smmlsr,
  OP_smmul,
  OP_smmulr,
  OP_smuad,
  OP_smuadx,
  OP_smulbb,
  OP_smulbt,
  OP_smull,
  OP_smulls,
  OP_smultb,
  OP_smultt,
  OP_smulwb,
  OP_smulwt,
  OP_smusd,
  OP_smusdx,
  OP_srs,
  OP_srsda,
  OP_srsdb,
  OP_srsib,
  OP_ssat,
  OP_ssat16,
  OP_ssax,
  OP_ssub16,
  OP_ssub8,
  OP_stc,
  OP_stc2,
  OP_stc2l,
  OP_stcl,
  OP_stl,
  OP_stlb,
  OP_stlex,
  OP_stlexb,
  OP_stlexd,
  OP_stlexh,
  OP_stlh,
  OP_stm,
  OP_stm_priv,
  OP_stmda,
  OP_stmda_priv,
  OP_stmdb,
  OP_stmdb_priv,
  OP_stmib,
  OP_stmib_priv,
  OP_str,
  OP_strb,
  OP_strbt,
  OP_strd,
  OP_strex,
  OP_strexb,
  OP_strexd,
  OP_strexh,
  OP_strh,
  OP_strht,
  OP_strt,
  OP_sub,
  OP_subs,
  OP_subw,
  OP_svc,
  OP_swp,
  OP_swpb,
  OP_sxtab,
  OP_sxtab16,
  OP_sxtah,
  OP_sxtb,
  OP_sxtb16,
  OP_sxth,
  OP_tbb,
  OP_tbh,
  OP_teq,
  OP_tst,
  OP_uadd16,
  OP_uadd8,
  OP_uasx,
  OP_ubfx,
  OP_udf,
  OP_udiv,
  OP_uhadd16,
  OP_uhadd8,
  OP_uhasx,
  OP_uhsax,
  OP_uhsub16,
  OP_uhsub8,
  OP_umaal,
  OP_umlal,
  OP_umlals,
  OP_umull,
  OP_umulls,
  OP_uqadd16,
  OP_uqadd8,
  OP_uqasx,
  OP_uqsax,
  OP_uqsub16,
  OP_uqsub8,
  OP_usad8,
  OP_usada8,
  OP_usat,
  OP_usat16,
  OP_usax,
  OP_usub16,
  OP_usub8,
  OP_uxtab,
  OP_uxtab16,
  OP_uxtah,
  OP_uxtb,
  OP_uxtb16,
  OP_uxth,
  OP_vaba_s16,
  OP_vaba_s32,
  OP_vaba_s8,
  OP_vaba_u16,
  OP_vaba_u32,
  OP_vaba_u8,
  OP_vabal_s16,
  OP_vabal_s32,
  OP_vabal_s8,
  OP_vabal_u16,
  OP_vabal_u32,
  OP_vabal_u8,
  OP_vabd_s16,
  OP_vabd_s32,
  OP_vabd_s8,
  OP_vabd_u16,
  OP_vabd_u32,
  OP_vabd_u8,
  OP_vabdl_s16,
  OP_vabdl_s32,
  OP_vabdl_s8,
  OP_vabdl_u16,
  OP_vabdl_u32,
  OP_vabdl_u8,
  OP_vabs_f32,
  OP_vabs_f64,
  OP_vabs_s16,
  OP_vabs_s32,
  OP_vabs_s8,
  OP_vacge_f32,
  OP_vacgt_f32,
  OP_vadd_f32,
  OP_vadd_f64,
  OP_vadd_i16,
  OP_vadd_i32,
  OP_vadd_i64,
  OP_vadd_i8,
  OP_vaddhn_i16,
  OP_vaddhn_i32,
  OP_vaddhn_i64,
  OP_vaddl_s16,
  OP_vaddl_s32,
  OP_vaddl_s8,
  OP_vaddl_u16,
  OP_vaddl_u32,
  OP_vaddl_u8,
  OP_vaddw_s16,
  OP_vaddw_s32,
  OP_vaddw_s8,
  OP_vaddw_u16,
  OP_vaddw_u32,
  OP_vaddw_u8,
  OP_vand,
  OP_vbic,
  OP_vbic_i16,
  OP_vbic_i32,
  OP_vbif,
  OP_vbit,
  OP_vbsl,
  OP_vceq_f32,
  OP_vceq_i16,
  OP_vceq_i32,
  OP_vceq_i8,
  OP_vcge_f32,
  OP_vcge_s16,
  OP_vcge_s32,
  OP_vcge_s8,
  OP_vcge_u16,
  OP_vcge_u32,
  OP_vcge_u8,
  OP_vcgt_f32,
  OP_vcgt_s16,
  OP_vcgt_s32,
  OP_vcgt_s8,
  OP_vcgt_u16,
  OP_vcgt_u32,
  OP_vcgt_u8,
  OP_vcle_f32,
  OP_vcle_s16,
  OP_vcle_s32,
  OP_vcle_s8,
  OP_vcls_s16,
  OP_vcls_s32,
  OP_vcls_s8,
  OP_vclt_f32,
  OP_vclt_s16,
  OP_vclt_s32,
  OP_vclt_s8,
  OP_vclz_i16,
  OP_vclz_i32,
  OP_vclz_i8,
  OP_vcmp_f32,
  OP_vcmp_f64,
  OP_vcmpe_f32,
  OP_vcmpe_f64,
  OP_vcnt_8,
  OP_vcvt_f16_f32,
  OP_vcvt_f32_f16,
  OP_vcvt_f32_f64,
  OP_vcvt_f32_s16,
  OP_vcvt_f32_s32,
  OP_vcvt_f32_u16,
  OP_vcvt_f32_u32,
  OP_vcvt_f64_f32,
  OP_vcvt_f64_s16,
  OP_vcvt_f64_s32,
  OP_vcvt_f64_u16,
  OP_vcvt_f64_u32,
  OP_vcvt_s16_f32,
  OP_vcvt_s16_f64,
  OP_vcvt_s32_f32,
  OP_vcvt_s32_f64,
  OP_vcvt_u16_f32,
  OP_vcvt_u16_f64,
  OP_vcvt_u32_f32,
  OP_vcvt_u32_f64,
  OP_vcvta_s32_f32,
  OP_vcvta_s32_f64,
  OP_vcvta_u32_f32,
  OP_vcvta_u32_f64,
  OP_vcvtb_f16_f32,
  OP_vcvtb_f16_f64,
  OP_vcvtb_f32_f16,
  OP_vcvtb_f64_f16,
  OP_vcvtm_s32_f32,
  OP_vcvtm_s32_f64,
  OP_vcvtm_u32_f32,
  OP_vcvtm_u32_f64,
  OP_vcvtn_s32_f32,
  OP_vcvtn_s32_f64,
  OP_vcvtn_u32_f32,
  OP_vcvtn_u32_f64,
  OP_vcvtp_s32_f32,
  OP_vcvtp_s32_f64,
  OP_vcvtp_u32_f32,
  OP_vcvtp_u32_f64,
  OP_vcvtr_s32_f32,
  OP_vcvtr_s32_f64,
  OP_vcvtr_u32_f32,
  OP_vcvtr_u32_f64,
  OP_vcvtt_f16_f32,
  OP_vcvtt_f16_f64,
  OP_vcvtt_f32_f16,
  OP_vcvtt_f64_f16,
  OP_vdiv_f32,
  OP_vdiv_f64,
  OP_vdup_16,
  OP_vdup_32,
  OP_vdup_8,
  OP_veor,
  OP_vext,
  OP_vfma_f32,
  OP_vfma_f64,
  OP_vfms_f32,
  OP_vfms_f64,
  OP_vfnma_f32,
  OP_vfnma_f64,
  OP_vfnms_f32,
  OP_vfnms_f64,
  OP_vhadd_s16,
  OP_vhadd_s32,
  OP_vhadd_s8,
  OP_vhadd_u16,
  OP_vhadd_u32,
  OP_vhadd_u8,
  OP_vhsub_s16,
  OP_vhsub_s32,
  OP_vhsub_s8,
  OP_vhsub_u16,
  OP_vhsub_u32,
  OP_vhsub_u8,
  OP_vld1_16,
  OP_vld1_32,
  OP_vld1_64,
  OP_vld1_8,
  OP_vld1_dup_16,
  OP_vld1_dup_32,
  OP_vld1_dup_8,
  OP_vld1_lane_16,
  OP_vld1_lane_32,
  OP_vld1_lane_8,
  OP_vld2_16,
  OP_vld2_32,
  OP_vld2_8,
  OP_vld2_dup_16,
  OP_vld2_dup_32,
  OP_vld2_dup_8,
  OP_vld2_lane_16,
  OP_vld2_lane_32,
  OP_vld2_lane_8,
  OP_vld3_16,
  OP_vld3_32,
  OP_vld3_8,
  OP_vld3_dup_16,
  OP_vld3_dup_32,
  OP_vld3_dup_8,
  OP_vld3_lane_16,
  OP_vld3_lane_32,
  OP_vld3_lane_8,
  OP_vld4_16,
  OP_vld4_32,
  OP_vld4_8,
  OP_vld4_dup_16,
  OP_vld4_dup_32,
  OP_vld4_dup_8,
  OP_vld4_lane_16,
  OP_vld4_lane_32,
  OP_vld4_lane_8,
  OP_vldm,
  OP_vldmdb,
  OP_vldr,
  OP_vmax_f32,
  OP_vmax_s16,
  OP_vmax_s32,
  OP_vmax_s8,
  OP_vmax_u16,
  OP_vmax_u32,
  OP_vmax_u8,
  OP_vmaxnm_f32,
  OP_vmaxnm_f64,
  OP_vmin_f32,
  OP_vmin_s16,
  OP_vmin_s32,
  OP_vmin_s8,
  OP_vmin_u16,
  OP_vmin_u32,
  OP_vmin_u8,
  OP_vminnm_f32,
  OP_vminnm_f64,
  OP_vmla_f32,
  OP_vmla_f64,
  OP_vmla_i16,
  OP_vmla_i32,
  OP_vmla_i8,
  OP_vmlal_s16,
  OP_vmlal_s32,
  OP_vmlal_s8,
  OP_vmlal_u16,
  OP_vmlal_u32,
  OP_vmlal_u8,
  OP_vmls_f32,
  OP_vmls_f64,
  OP_vmls_i16,
  OP_vmls_i32,
  OP_vmls_i8,
  OP_vmlsl_s16,
  OP_vmlsl_s32,
  OP_vmlsl_s8,
  OP_vmlsl_u16,
  OP_vmlsl_u32,
  OP_vmlsl_u8,
  OP_vmov,
  OP_vmov_16,
  OP_vmov_32,
  OP_vmov_8,
  OP_vmov_f32,
  OP_vmov_f64,
  OP_vmov_i16,
  OP_vmov_i32,
  OP_vmov_i64,
  OP_vmov_i8,
  OP_vmov_s16,
  OP_vmov_s8,
  OP_vmov_u16,
  OP_vmov_u8,
  OP_vmovl_s16,
  OP_vmovl_s32,
  OP_vmovl_s8,
  OP_vmovl_u16,
  OP_vmovl_u32,
  OP_vmovl_u8,
  OP_vmovn_i16,
  OP_vmovn_i32,
  OP_vmovn_i64,
  OP_vmrs,
  OP_vmsr,
  OP_vmul_f32,
  OP_vmul_f64,
  OP_vmul_i16,
  OP_vmul_i32,
  OP_vmul_i8,
  OP_vmul_p32,
  OP_vmul_p8,
  OP_vmull_p32,
  OP_vmull_p8,
  OP_vmull_s16,
  OP_vmull_s32,
  OP_vmull_s8,
  OP_vmull_u16,
  OP_vmull_u32,
  OP_vmull_u8,
  OP_vmvn,
  OP_vmvn_i16,
  OP_vmvn_i32,
  OP_vneg_f32,
  OP_vneg_f64,
  OP_vneg_s16,
  OP_vneg_s32,
  OP_vneg_s8,
  OP_vnmla_f32,
  OP_vnmla_f64,
  OP_vnmls_f32,
  OP_vnmls_f64,
  OP_vnmul_f32,
  OP_vnmul_f64,
  OP_vorn,
  OP_vorr,
  OP_vorr_i16,
  OP_vorr_i32,
  OP_vpadal_s16,
  OP_vpadal_s32,
  OP_vpadal_s8,
  OP_vpadal_u16,
  OP_vpadal_u32,
  OP_vpadal_u8,
  OP_vpadd_f32,
  OP_vpadd_i16,
  OP_vpadd_i32,
  OP_vpadd_i8,
  OP_vpaddl_s16,
  OP_vpaddl_s32,
  OP_vpaddl_s8,
  OP_vpaddl_u16,
  OP_vpaddl_u32,
  OP_vpaddl_u8,
  OP_vpmax_f32,
  OP_vpmax_s16,
  OP_vpmax_s32,
  OP_vpmax_s8,
  OP_vpmax_u16,
  OP_vpmax_u32,
  OP_vpmax_u8,
  OP_vpmin_f32,
  OP_vpmin_s16,
  OP_vpmin_s32,
  OP_vpmin_s8,
  OP_vpmin_u16,
  OP_vpmin_u32,
  OP_vpmin_u8,
  OP_vqabs_s16,
  OP_vqabs_s32,
  OP_vqabs_s8,
  OP_vqadd_s16,
  OP_vqadd_s32,
  OP_vqadd_s64,
  OP_vqadd_s8,
  OP_vqadd_u16,
  OP_vqadd_u32,
  OP_vqadd_u64,
  OP_vqadd_u8,
  OP_vqdmlal_s16,
  OP_vqdmlal_s32,
  OP_vqdmlsl_s16,
  OP_vqdmlsl_s32,
  OP_vqdmulh_s16,
  OP_vqdmulh_s32,
  OP_vqdmull_s16,
  OP_vqdmull_s32,
  OP_vqmovn_s16,
  OP_vqmovn_s32,
  OP_vqmovn_s64,
  OP_vqmovn_u16,
  OP_vqmovn_u32,
  OP_vqmovn_u64,
  OP_vqmovun_s16,
  OP_vqmovun_s32,
  OP_vqmovun_s64,
  OP_vqneg_s16,
  OP_vqneg_s32,
  OP_vqneg_s8,
  OP_vqrdmulh_s16,
  OP_vqrdmulh_s32,
  OP_vqrshl_s16,
  OP_vqrshl_s32,
  OP_vqrshl_s64,
  OP_vqrshl_s8,
  OP_vqrshl_u16,
  OP_vqrshl_u32,
  OP_vqrshl_u64,
  OP_vqrshl_u8,
  OP_vqrshrn_s16,
  OP_vqrshrn_s32,
  OP_vqrshrn_s64,
  OP_vqrshrn_u16,
  OP_vqrshrn_u32,
  OP_vqrshrn_u64,
  OP_vqrshrun_s16,
  OP_vqrshrun_s32,
  OP_vqrshrun_s64,
  OP_vqshl_s16,
  OP_vqshl_s32,
  OP_vqshl_s64,
  OP_vqshl_s8,
  OP_vqshl_u16,
  OP_vqshl_u32,
  OP_vqshl_u64,
  OP_vqshl_u8,
  OP_vqshlu_s16,
  OP_vqshlu_s32,
  OP_vqshlu_s64,
  OP_vqshlu_s8,
  OP_vqshrn_s16,
  OP_vqshrn_s32,
  OP_vqshrn_s64,
  OP_vqshrn_u16,
  OP_vqshrn_u32,
  OP_vqshrn_u64,
  OP_vqshrun_s16,
  OP_vqshrun_s32,
  OP_vqshrun_s64,
  OP_vqsub_s16,
  OP_vqsub_s32,
  OP_vqsub_s64,
  OP_vqsub_s8,
  OP_vqsub_u16,
  OP_vqsub_u32,
  OP_vqsub_u64,
  OP_vqsub_u8,
  OP_vraddhn_i16,
  OP_vraddhn_i32,
  OP_vraddhn_i64,
  OP_vrecpe_f32,
  OP_vrecpe_u32,
  OP_vrecps_f32,
  OP_vrev16_16,
  OP_vrev16_8,
  OP_vrev32_16,
  OP_vrev32_32,
  OP_vrev32_8,
  OP_vrev64_16,
  OP_vrev64_32,
  OP_vrev64_8,
  OP_vrhadd_s16,
  OP_vrhadd_s32,
  OP_vrhadd_s8,
  OP_vrhadd_u16,
  OP_vrhadd_u32,
  OP_vrhadd_u8,
  OP_vrinta_f32_f32,
  OP_vrinta_f64_f64,
  OP_vrintm_f32_f32,
  OP_vrintm_f64_f64,
  OP_vrintn_f32_f32,
  OP_vrintn_f64_f64,
  OP_vrintp_f32_f32,
  OP_vrintp_f64_f64,
  OP_vrintr_f32,
  OP_vrintr_f64,
  OP_vrintx_f32,
  OP_vrintx_f32_f32,
  OP_vrintx_f64,
  OP_vrintz_f32,
  OP_vrintz_f32_f32,
  OP_vrintz_f64,
  OP_vrshl_s16,
  OP_vrshl_s32,
  OP_vrshl_s64,
  OP_vrshl_s8,
  OP_vrshl_u16,
  OP_vrshl_u32,
  OP_vrshl_u64,
  OP_vrshl_u8,
  OP_vrshr_s16,
  OP_vrshr_s32,
  OP_vrshr_s64,
  OP_vrshr_s8,
  OP_vrshr_u16,
  OP_vrshr_u32,
  OP_vrshr_u64,
  OP_vrshr_u8,
  OP_vrshrn_i16,
  OP_vrshrn_i32,
  OP_vrshrn_i64,
  OP_vrsqrte_f32,
  OP_vrsqrte_u32,
  OP_vrsqrts_f32,
  OP_vrsra_s16,
  OP_vrsra_s32,
  OP_vrsra_s64,
  OP_vrsra_s8,
  OP_vrsra_u16,
  OP_vrsra_u32,
  OP_vrsra_u64,
  OP_vrsra_u8,
  OP_vrsubhn_i16,
  OP_vrsubhn_i32,
  OP_vrsubhn_i64,
  OP_vsel_eq_f32,
  OP_vsel_eq_f64,
  OP_vsel_ge_f32,
  OP_vsel_ge_f64,
  OP_vsel_gt_f32,
  OP_vsel_gt_f64,
  OP_vsel_vs_f32,
  OP_vsel_vs_f64,
  OP_vshl_i16,
  OP_vshl_i32,
  OP_vshl_i64,
  OP_vshl_i8,
  OP_vshl_s16,
  OP_vshl_s32,
  OP_vshl_s64,
  OP_vshl_s8,
  OP_vshl_u16,
  OP_vshl_u32,
  OP_vshl_u64,
  OP_vshl_u8,
  OP_vshll_i16,
  OP_vshll_i32,
  OP_vshll_i8,
  OP_vshll_s16,
  OP_vshll_s32,
  OP_vshll_s8,
  OP_vshll_u16,
  OP_vshll_u32,
  OP_vshll_u8,
  OP_vshr_s16,
  OP_vshr_s32,
  OP_vshr_s64,
  OP_vshr_s8,
  OP_vshr_u16,
  OP_vshr_u32,
  OP_vshr_u64,
  OP_vshr_u8,
  OP_vshrn_i16,
  OP_vshrn_i32,
  OP_vshrn_i64,
  OP_vsli_16,
  OP_vsli_32,
  OP_vsli_64,
  OP_vsli_8,
  OP_vsqrt_f32,
  OP_vsqrt_f64,
  OP_vsra_s16,
  OP_vsra_s32,
  OP_vsra_s64,
  OP_vsra_s8,
  OP_vsra_u16,
  OP_vsra_u32,
  OP_vsra_u64,
  OP_vsra_u8,
  OP_vsri_16,
  OP_vsri_32,
  OP_vsri_64,
  OP_vsri_8,
  OP_vst1_16,
  OP_vst1_32,
  OP_vst1_64,
  OP_vst1_8,
  OP_vst1_lane_16,
  OP_vst1_lane_32,
  OP_vst1_lane_8,
  OP_vst2_16,
  OP_vst2_32,
  OP_vst2_8,
  OP_vst2_lane_16,
  OP_vst2_lane_32,
  OP_vst2_lane_8,
  OP_vst3_16,
  OP_vst3_32,
  OP_vst3_8,
  OP_vst3_lane_16,
  OP_vst3_lane_32,
  OP_vst3_lane_8,
  OP_vst4_16,
  OP_vst4_32,
  OP_vst4_8,
  OP_vst4_lane_16,
  OP_vst4_lane_32,
  OP_vst4_lane_8,
  OP_vstm,
  OP_vstmdb,
  OP_vstr,
  OP_vsub_f32,
  OP_vsub_f64,
  OP_vsub_i16,
  OP_vsub_i32,
  OP_vsub_i64,
  OP_vsub_i8,
  OP_vsubhn_i16,
  OP_vsubhn_i32,
  OP_vsubhn_i64,
  OP_vsubl_s16,
  OP_vsubl_s32,
  OP_vsubl_s8,
  OP_vsubl_u16,
  OP_vsubl_u32,
  OP_vsubl_u8,
  OP_vsubw_s16,
  OP_vsubw_s32,
  OP_vsubw_s8,
  OP_vsubw_u16,
  OP_vsubw_u32,
  OP_vsubw_u8,
  OP_vswp,
  OP_vtbl_8,
  OP_vtbx_8,
  OP_vtrn_16,
  OP_vtrn_32,
  OP_vtrn_8,
  OP_vtst_16,
  OP_vtst_32,
  OP_vtst_8,
  OP_vuzp_16,
  OP_vuzp_32,
  OP_vuzp_8,
  OP_vzip_16,
  OP_vzip_32,
  OP_vzip_8,
  OP_wfe,
  OP_wfi,
  OP_yield ,
  OP_FIRST = OP_adc,
  OP_LAST = OP_AFTER_LAST - 1 ,
  OP_UNDECODED,
  OP_CONTD,
  OP_LABEL,
  OP_add,
  OP_or,
  OP_adc,
  OP_sbb,
  OP_and,
  OP_daa,
  OP_sub,
  OP_das,
  OP_xor,
  OP_aaa,
  OP_cmp,
  OP_aas,
  OP_inc,
  OP_dec,
  OP_push,
  OP_push_imm,
  OP_pop,
  OP_pusha,
  OP_popa,
  OP_bound,
  OP_arpl,
  OP_imul,
  OP_jo_short,
  OP_jno_short,
  OP_jb_short,
  OP_jnb_short,
  OP_jz_short,
  OP_jnz_short,
  OP_jbe_short,
  OP_jnbe_short,
  OP_js_short,
  OP_jns_short,
  OP_jp_short,
  OP_jnp_short,
  OP_jl_short,
  OP_jnl_short,
  OP_jle_short,
  OP_jnle_short,
  OP_call,
  OP_call_ind,
  OP_call_far,
  OP_call_far_ind,
  OP_jmp,
  OP_jmp_short,
  OP_jmp_ind,
  OP_jmp_far,
  OP_jmp_far_ind,
  OP_loopne,
  OP_loope,
  OP_loop,
  OP_jecxz,
  OP_mov_ld,
  OP_mov_st,
  OP_mov_imm,
  OP_mov_seg,
  OP_mov_priv,
  OP_test,
  OP_lea,
  OP_xchg,
  OP_cwde,
  OP_cdq,
  OP_fwait,
  OP_pushf,
  OP_popf,
  OP_sahf,
  OP_lahf,
  OP_ret,
  OP_ret_far,
  OP_les,
  OP_lds,
  OP_enter,
  OP_leave,
  OP_int3,
  OP_int,
  OP_into,
  OP_iret,
  OP_aam,
  OP_aad,
  OP_xlat,
  OP_in,
  OP_out,
  OP_hlt,
  OP_cmc,
  OP_clc,
  OP_stc,
  OP_cli,
  OP_sti,
  OP_cld,
  OP_std,
  OP_lar,
  OP_lsl,
  OP_syscall,
  OP_clts,
  OP_sysret,
  OP_invd,
  OP_wbinvd,
  OP_ud2a,
  OP_nop_modrm,
  OP_movntps,
  OP_movntpd,
  OP_wrmsr,
  OP_rdtsc,
  OP_rdmsr,
  OP_rdpmc,
  OP_sysenter,
  OP_sysexit,
  OP_cmovo,
  OP_cmovno,
  OP_cmovb,
  OP_cmovnb,
  OP_cmovz,
  OP_cmovnz,
  OP_cmovbe,
  OP_cmovnbe,
  OP_cmovs,
  OP_cmovns,
  OP_cmovp,
  OP_cmovnp,
  OP_cmovl,
  OP_cmovnl,
  OP_cmovle,
  OP_cmovnle,
  OP_punpcklbw,
  OP_punpcklwd,
  OP_punpckldq,
  OP_packsswb,
  OP_pcmpgtb,
  OP_pcmpgtw,
  OP_pcmpgtd,
  OP_packuswb,
  OP_punpckhbw,
  OP_punpckhwd,
  OP_punpckhdq,
  OP_packssdw,
  OP_punpcklqdq,
  OP_punpckhqdq,
  OP_movd,
  OP_movq,
  OP_movdqu,
  OP_movdqa,
  OP_pshufw,
  OP_pshufd,
  OP_pshufhw,
  OP_pshuflw,
  OP_pcmpeqb,
  OP_pcmpeqw,
  OP_pcmpeqd,
  OP_emms,
  OP_jo,
  OP_jno,
  OP_jb,
  OP_jnb,
  OP_jz,
  OP_jnz,
  OP_jbe,
  OP_jnbe,
  OP_js,
  OP_jns,
  OP_jp,
  OP_jnp,
  OP_jl,
  OP_jnl,
  OP_jle,
  OP_jnle,
  OP_seto,
  OP_setno,
  OP_setb,
  OP_setnb,
  OP_setz,
  OP_setnz,
  OP_setbe,
  OP_setnbe,
  OP_sets,
  OP_setns,
  OP_setp,
  OP_setnp,
  OP_setl,
  OP_setnl,
  OP_setle,
  OP_setnle,
  OP_cpuid,
  OP_bt,
  OP_shld,
  OP_rsm,
  OP_bts,
  OP_shrd,
  OP_cmpxchg,
  OP_lss,
  OP_btr,
  OP_lfs,
  OP_lgs,
  OP_movzx,
  OP_ud2b,
  OP_btc,
  OP_bsf,
  OP_bsr,
  OP_movsx,
  OP_xadd,
  OP_movnti,
  OP_pinsrw,
  OP_pextrw,
  OP_bswap,
  OP_psrlw,
  OP_psrld,
  OP_psrlq,
  OP_paddq,
  OP_pmullw,
  OP_pmovmskb,
  OP_psubusb,
  OP_psubusw,
  OP_pminub,
  OP_pand,
  OP_paddusb,
  OP_paddusw,
  OP_pmaxub,
  OP_pandn,
  OP_pavgb,
  OP_psraw,
  OP_psrad,
  OP_pavgw,
  OP_pmulhuw,
  OP_pmulhw,
  OP_movntq,
  OP_movntdq,
  OP_psubsb,
  OP_psubsw,
  OP_pminsw,
  OP_por,
  OP_paddsb,
  OP_paddsw,
  OP_pmaxsw,
  OP_pxor,
  OP_psllw,
  OP_pslld,
  OP_psllq,
  OP_pmuludq,
  OP_pmaddwd,
  OP_psadbw,
  OP_maskmovq,
  OP_maskmovdqu,
  OP_psubb,
  OP_psubw,
  OP_psubd,
  OP_psubq,
  OP_paddb,
  OP_paddw,
  OP_paddd,
  OP_psrldq,
  OP_pslldq,
  OP_rol,
  OP_ror,
  OP_rcl,
  OP_rcr,
  OP_shl,
  OP_shr,
  OP_sar,
  OP_not,
  OP_neg,
  OP_mul,
  OP_div,
  OP_idiv,
  OP_sldt,
  OP_str,
  OP_lldt,
  OP_ltr,
  OP_verr,
  OP_verw,
  OP_sgdt,
  OP_sidt,
  OP_lgdt,
  OP_lidt,
  OP_smsw,
  OP_lmsw,
  OP_invlpg,
  OP_cmpxchg8b,
  OP_fxsave32,
  OP_fxrstor32,
  OP_ldmxcsr,
  OP_stmxcsr,
  OP_lfence,
  OP_mfence,
  OP_clflush,
  OP_sfence,
  OP_prefetchnta,
  OP_prefetcht0,
  OP_prefetcht1,
  OP_prefetcht2,
  OP_prefetch,
  OP_prefetchw,
  OP_movups,
  OP_movss,
  OP_movupd,
  OP_movsd,
  OP_movlps,
  OP_movlpd,
  OP_unpcklps,
  OP_unpcklpd,
  OP_unpckhps,
  OP_unpckhpd,
  OP_movhps,
  OP_movhpd,
  OP_movaps,
  OP_movapd,
  OP_cvtpi2ps,
  OP_cvtsi2ss,
  OP_cvtpi2pd,
  OP_cvtsi2sd,
  OP_cvttps2pi,
  OP_cvttss2si,
  OP_cvttpd2pi,
  OP_cvttsd2si,
  OP_cvtps2pi,
  OP_cvtss2si,
  OP_cvtpd2pi,
  OP_cvtsd2si,
  OP_ucomiss,
  OP_ucomisd,
  OP_comiss,
  OP_comisd,
  OP_movmskps,
  OP_movmskpd,
  OP_sqrtps,
  OP_sqrtss,
  OP_sqrtpd,
  OP_sqrtsd,
  OP_rsqrtps,
  OP_rsqrtss,
  OP_rcpps,
  OP_rcpss,
  OP_andps,
  OP_andpd,
  OP_andnps,
  OP_andnpd,
  OP_orps,
  OP_orpd,
  OP_xorps,
  OP_xorpd,
  OP_addps,
  OP_addss,
  OP_addpd,
  OP_addsd,
  OP_mulps,
  OP_mulss,
  OP_mulpd,
  OP_mulsd,
  OP_cvtps2pd,
  OP_cvtss2sd,
  OP_cvtpd2ps,
  OP_cvtsd2ss,
  OP_cvtdq2ps,
  OP_cvttps2dq,
  OP_cvtps2dq,
  OP_subps,
  OP_subss,
  OP_subpd,
  OP_subsd,
  OP_minps,
  OP_minss,
  OP_minpd,
  OP_minsd,
  OP_divps,
  OP_divss,
  OP_divpd,
  OP_divsd,
  OP_maxps,
  OP_maxss,
  OP_maxpd,
  OP_maxsd,
  OP_cmpps,
  OP_cmpss,
  OP_cmppd,
  OP_cmpsd,
  OP_shufps,
  OP_shufpd,
  OP_cvtdq2pd,
  OP_cvttpd2dq,
  OP_cvtpd2dq,
  OP_nop,
  OP_pause,
  OP_ins,
  OP_rep_ins,
  OP_outs,
  OP_rep_outs,
  OP_movs,
  OP_rep_movs,
  OP_stos,
  OP_rep_stos,
  OP_lods,
  OP_rep_lods,
  OP_cmps,
  OP_rep_cmps,
  OP_repne_cmps,
  OP_scas,
  OP_rep_scas,
  OP_repne_scas,
  OP_fadd,
  OP_fmul,
  OP_fcom,
  OP_fcomp,
  OP_fsub,
  OP_fsubr,
  OP_fdiv,
  OP_fdivr,
  OP_fld,
  OP_fst,
  OP_fstp,
  OP_fldenv,
  OP_fldcw,
  OP_fnstenv,
  OP_fnstcw,
  OP_fiadd,
  OP_fimul,
  OP_ficom,
  OP_ficomp,
  OP_fisub,
  OP_fisubr,
  OP_fidiv,
  OP_fidivr,
  OP_fild,
  OP_fist,
  OP_fistp,
  OP_frstor,
  OP_fnsave,
  OP_fnstsw,
  OP_fbld,
  OP_fbstp,
  OP_fxch,
  OP_fnop,
  OP_fchs,
  OP_fabs,
  OP_ftst,
  OP_fxam,
  OP_fld1,
  OP_fldl2t,
  OP_fldl2e,
  OP_fldpi,
  OP_fldlg2,
  OP_fldln2,
  OP_fldz,
  OP_f2xm1,
  OP_fyl2x,
  OP_fptan,
  OP_fpatan,
  OP_fxtract,
  OP_fprem1,
  OP_fdecstp,
  OP_fincstp,
  OP_fprem,
  OP_fyl2xp1,
  OP_fsqrt,
  OP_fsincos,
  OP_frndint,
  OP_fscale,
  OP_fsin,
  OP_fcos,
  OP_fcmovb,
  OP_fcmove,
  OP_fcmovbe,
  OP_fcmovu,
  OP_fucompp,
  OP_fcmovnb,
  OP_fcmovne,
  OP_fcmovnbe,
  OP_fcmovnu,
  OP_fnclex,
  OP_fninit,
  OP_fucomi,
  OP_fcomi,
  OP_ffree,
  OP_fucom,
  OP_fucomp,
  OP_faddp,
  OP_fmulp,
  OP_fcompp,
  OP_fsubrp,
  OP_fsubp,
  OP_fdivrp,
  OP_fdivp,
  OP_fucomip,
  OP_fcomip,
  OP_fisttp,
  OP_haddpd,
  OP_haddps,
  OP_hsubpd,
  OP_hsubps,
  OP_addsubpd,
  OP_addsubps,
  OP_lddqu,
  OP_monitor,
  OP_mwait,
  OP_movsldup,
  OP_movshdup,
  OP_movddup,
  OP_femms,
  OP_unknown_3dnow,
  OP_pavgusb,
  OP_pfadd,
  OP_pfacc,
  OP_pfcmpge,
  OP_pfcmpgt,
  OP_pfcmpeq,
  OP_pfmin,
  OP_pfmax,
  OP_pfmul,
  OP_pfrcp,
  OP_pfrcpit1,
  OP_pfrcpit2,
  OP_pfrsqrt,
  OP_pfrsqit1,
  OP_pmulhrw,
  OP_pfsub,
  OP_pfsubr,
  OP_pi2fd,
  OP_pf2id,
  OP_pi2fw,
  OP_pf2iw,
  OP_pfnacc,
  OP_pfpnacc,
  OP_pswapd,
  OP_pshufb,
  OP_phaddw,
  OP_phaddd,
  OP_phaddsw,
  OP_pmaddubsw,
  OP_phsubw,
  OP_phsubd,
  OP_phsubsw,
  OP_psignb,
  OP_psignw,
  OP_psignd,
  OP_pmulhrsw,
  OP_pabsb,
  OP_pabsw,
  OP_pabsd,
  OP_palignr,
  OP_popcnt,
  OP_movntss,
  OP_movntsd,
  OP_extrq,
  OP_insertq,
  OP_lzcnt,
  OP_pblendvb,
  OP_blendvps,
  OP_blendvpd,
  OP_ptest,
  OP_pmovsxbw,
  OP_pmovsxbd,
  OP_pmovsxbq,
  OP_pmovsxwd,
  OP_pmovsxwq,
  OP_pmovsxdq,
  OP_pmuldq,
  OP_pcmpeqq,
  OP_movntdqa,
  OP_packusdw,
  OP_pmovzxbw,
  OP_pmovzxbd,
  OP_pmovzxbq,
  OP_pmovzxwd,
  OP_pmovzxwq,
  OP_pmovzxdq,
  OP_pcmpgtq,
  OP_pminsb,
  OP_pminsd,
  OP_pminuw,
  OP_pminud,
  OP_pmaxsb,
  OP_pmaxsd,
  OP_pmaxuw,
  OP_pmaxud,
  OP_pmulld,
  OP_phminposuw,
  OP_crc32,
  OP_pextrb,
  OP_pextrd,
  OP_extractps,
  OP_roundps,
  OP_roundpd,
  OP_roundss,
  OP_roundsd,
  OP_blendps,
  OP_blendpd,
  OP_pblendw,
  OP_pinsrb,
  OP_insertps,
  OP_pinsrd,
  OP_dpps,
  OP_dppd,
  OP_mpsadbw,
  OP_pcmpestrm,
  OP_pcmpestri,
  OP_pcmpistrm,
  OP_pcmpistri,
  OP_movsxd,
  OP_swapgs,
  OP_vmcall,
  OP_vmlaunch,
  OP_vmresume,
  OP_vmxoff,
  OP_vmptrst,
  OP_vmptrld,
  OP_vmxon,
  OP_vmclear,
  OP_vmread,
  OP_vmwrite,
  OP_int1,
  OP_salc,
  OP_ffreep,
  OP_vmrun,
  OP_vmmcall,
  OP_vmload,
  OP_vmsave,
  OP_stgi,
  OP_clgi,
  OP_skinit,
  OP_invlpga,
  OP_rdtscp,
  OP_invept,
  OP_invvpid,
  OP_pclmulqdq,
  OP_aesimc,
  OP_aesenc,
  OP_aesenclast,
  OP_aesdec,
  OP_aesdeclast,
  OP_aeskeygenassist,
  OP_movbe,
  OP_xgetbv,
  OP_xsetbv,
  OP_xsave32,
  OP_xrstor32,
  OP_xsaveopt32,
  OP_vmovss,
  OP_vmovsd,
  OP_vmovups,
  OP_vmovupd,
  OP_vmovlps,
  OP_vmovsldup,
  OP_vmovlpd,
  OP_vmovddup,
  OP_vunpcklps,
  OP_vunpcklpd,
  OP_vunpckhps,
  OP_vunpckhpd,
  OP_vmovhps,
  OP_vmovshdup,
  OP_vmovhpd,
  OP_vmovaps,
  OP_vmovapd,
  OP_vcvtsi2ss,
  OP_vcvtsi2sd,
  OP_vmovntps,
  OP_vmovntpd,
  OP_vcvttss2si,
  OP_vcvttsd2si,
  OP_vcvtss2si,
  OP_vcvtsd2si,
  OP_vucomiss,
  OP_vucomisd,
  OP_vcomiss,
  OP_vcomisd,
  OP_vmovmskps,
  OP_vmovmskpd,
  OP_vsqrtps,
  OP_vsqrtss,
  OP_vsqrtpd,
  OP_vsqrtsd,
  OP_vrsqrtps,
  OP_vrsqrtss,
  OP_vrcpps,
  OP_vrcpss,
  OP_vandps,
  OP_vandpd,
  OP_vandnps,
  OP_vandnpd,
  OP_vorps,
  OP_vorpd,
  OP_vxorps,
  OP_vxorpd,
  OP_vaddps,
  OP_vaddss,
  OP_vaddpd,
  OP_vaddsd,
  OP_vmulps,
  OP_vmulss,
  OP_vmulpd,
  OP_vmulsd,
  OP_vcvtps2pd,
  OP_vcvtss2sd,
  OP_vcvtpd2ps,
  OP_vcvtsd2ss,
  OP_vcvtdq2ps,
  OP_vcvttps2dq,
  OP_vcvtps2dq,
  OP_vsubps,
  OP_vsubss,
  OP_vsubpd,
  OP_vsubsd,
  OP_vminps,
  OP_vminss,
  OP_vminpd,
  OP_vminsd,
  OP_vdivps,
  OP_vdivss,
  OP_vdivpd,
  OP_vdivsd,
  OP_vmaxps,
  OP_vmaxss,
  OP_vmaxpd,
  OP_vmaxsd,
  OP_vpunpcklbw,
  OP_vpunpcklwd,
  OP_vpunpckldq,
  OP_vpacksswb,
  OP_vpcmpgtb,
  OP_vpcmpgtw,
  OP_vpcmpgtd,
  OP_vpackuswb,
  OP_vpunpckhbw,
  OP_vpunpckhwd,
  OP_vpunpckhdq,
  OP_vpackssdw,
  OP_vpunpcklqdq,
  OP_vpunpckhqdq,
  OP_vmovd,
  OP_vpshufhw,
  OP_vpshufd,
  OP_vpshuflw,
  OP_vpcmpeqb,
  OP_vpcmpeqw,
  OP_vpcmpeqd,
  OP_vmovq,
  OP_vcmpps,
  OP_vcmpss,
  OP_vcmppd,
  OP_vcmpsd,
  OP_vpinsrw,
  OP_vpextrw,
  OP_vshufps,
  OP_vshufpd,
  OP_vpsrlw,
  OP_vpsrld,
  OP_vpsrlq,
  OP_vpaddq,
  OP_vpmullw,
  OP_vpmovmskb,
  OP_vpsubusb,
  OP_vpsubusw,
  OP_vpminub,
  OP_vpand,
  OP_vpaddusb,
  OP_vpaddusw,
  OP_vpmaxub,
  OP_vpandn,
  OP_vpavgb,
  OP_vpsraw,
  OP_vpsrad,
  OP_vpavgw,
  OP_vpmulhuw,
  OP_vpmulhw,
  OP_vcvtdq2pd,
  OP_vcvttpd2dq,
  OP_vcvtpd2dq,
  OP_vmovntdq,
  OP_vpsubsb,
  OP_vpsubsw,
  OP_vpminsw,
  OP_vpor,
  OP_vpaddsb,
  OP_vpaddsw,
  OP_vpmaxsw,
  OP_vpxor,
  OP_vpsllw,
  OP_vpslld,
  OP_vpsllq,
  OP_vpmuludq,
  OP_vpmaddwd,
  OP_vpsadbw,
  OP_vmaskmovdqu,
  OP_vpsubb,
  OP_vpsubw,
  OP_vpsubd,
  OP_vpsubq,
  OP_vpaddb,
  OP_vpaddw,
  OP_vpaddd,
  OP_vpsrldq,
  OP_vpslldq,
  OP_vmovdqu,
  OP_vmovdqa,
  OP_vhaddpd,
  OP_vhaddps,
  OP_vhsubpd,
  OP_vhsubps,
  OP_vaddsubpd,
  OP_vaddsubps,
  OP_vlddqu,
  OP_vpshufb,
  OP_vphaddw,
  OP_vphaddd,
  OP_vphaddsw,
  OP_vpmaddubsw,
  OP_vphsubw,
  OP_vphsubd,
  OP_vphsubsw,
  OP_vpsignb,
  OP_vpsignw,
  OP_vpsignd,
  OP_vpmulhrsw,
  OP_vpabsb,
  OP_vpabsw,
  OP_vpabsd,
  OP_vpalignr,
  OP_vpblendvb,
  OP_vblendvps,
  OP_vblendvpd,
  OP_vptest,
  OP_vpmovsxbw,
  OP_vpmovsxbd,
  OP_vpmovsxbq,
  OP_vpmovsxwd,
  OP_vpmovsxwq,
  OP_vpmovsxdq,
  OP_vpmuldq,
  OP_vpcmpeqq,
  OP_vmovntdqa,
  OP_vpackusdw,
  OP_vpmovzxbw,
  OP_vpmovzxbd,
  OP_vpmovzxbq,
  OP_vpmovzxwd,
  OP_vpmovzxwq,
  OP_vpmovzxdq,
  OP_vpcmpgtq,
  OP_vpminsb,
  OP_vpminsd,
  OP_vpminuw,
  OP_vpminud,
  OP_vpmaxsb,
  OP_vpmaxsd,
  OP_vpmaxuw,
  OP_vpmaxud,
  OP_vpmulld,
  OP_vphminposuw,
  OP_vaesimc,
  OP_vaesenc,
  OP_vaesenclast,
  OP_vaesdec,
  OP_vaesdeclast,
  OP_vpextrb,
  OP_vpextrd,
  OP_vextractps,
  OP_vroundps,
  OP_vroundpd,
  OP_vroundss,
  OP_vroundsd,
  OP_vblendps,
  OP_vblendpd,
  OP_vpblendw,
  OP_vpinsrb,
  OP_vinsertps,
  OP_vpinsrd,
  OP_vdpps,
  OP_vdppd,
  OP_vmpsadbw,
  OP_vpcmpestrm,
  OP_vpcmpestri,
  OP_vpcmpistrm,
  OP_vpcmpistri,
  OP_vpclmulqdq,
  OP_vaeskeygenassist,
  OP_vtestps,
  OP_vtestpd,
  OP_vzeroupper,
  OP_vzeroall,
  OP_vldmxcsr,
  OP_vstmxcsr,
  OP_vbroadcastss,
  OP_vbroadcastsd,
  OP_vbroadcastf128,
  OP_vmaskmovps,
  OP_vmaskmovpd,
  OP_vpermilps,
  OP_vpermilpd,
  OP_vperm2f128,
  OP_vinsertf128,
  OP_vextractf128,
  OP_vcvtph2ps,
  OP_vcvtps2ph,
  OP_vfmadd132ps,
  OP_vfmadd132pd,
  OP_vfmadd213ps,
  OP_vfmadd213pd,
  OP_vfmadd231ps,
  OP_vfmadd231pd,
  OP_vfmadd132ss,
  OP_vfmadd132sd,
  OP_vfmadd213ss,
  OP_vfmadd213sd,
  OP_vfmadd231ss,
  OP_vfmadd231sd,
  OP_vfmaddsub132ps,
  OP_vfmaddsub132pd,
  OP_vfmaddsub213ps,
  OP_vfmaddsub213pd,
  OP_vfmaddsub231ps,
  OP_vfmaddsub231pd,
  OP_vfmsubadd132ps,
  OP_vfmsubadd132pd,
  OP_vfmsubadd213ps,
  OP_vfmsubadd213pd,
  OP_vfmsubadd231ps,
  OP_vfmsubadd231pd,
  OP_vfmsub132ps,
  OP_vfmsub132pd,
  OP_vfmsub213ps,
  OP_vfmsub213pd,
  OP_vfmsub231ps,
  OP_vfmsub231pd,
  OP_vfmsub132ss,
  OP_vfmsub132sd,
  OP_vfmsub213ss,
  OP_vfmsub213sd,
  OP_vfmsub231ss,
  OP_vfmsub231sd,
  OP_vfnmadd132ps,
  OP_vfnmadd132pd,
  OP_vfnmadd213ps,
  OP_vfnmadd213pd,
  OP_vfnmadd231ps,
  OP_vfnmadd231pd,
  OP_vfnmadd132ss,
  OP_vfnmadd132sd,
  OP_vfnmadd213ss,
  OP_vfnmadd213sd,
  OP_vfnmadd231ss,
  OP_vfnmadd231sd,
  OP_vfnmsub132ps,
  OP_vfnmsub132pd,
  OP_vfnmsub213ps,
  OP_vfnmsub213pd,
  OP_vfnmsub231ps,
  OP_vfnmsub231pd,
  OP_vfnmsub132ss,
  OP_vfnmsub132sd,
  OP_vfnmsub213ss,
  OP_vfnmsub213sd,
  OP_vfnmsub231ss,
  OP_vfnmsub231sd,
  OP_movq2dq,
  OP_movdq2q,
  OP_fxsave64,
  OP_fxrstor64,
  OP_xsave64,
  OP_xrstor64,
  OP_xsaveopt64,
  OP_rdrand,
  OP_rdfsbase,
  OP_rdgsbase,
  OP_wrfsbase,
  OP_wrgsbase,
  OP_rdseed,
  OP_vfmaddsubps,
  OP_vfmaddsubpd,
  OP_vfmsubaddps,
  OP_vfmsubaddpd,
  OP_vfmaddps,
  OP_vfmaddpd,
  OP_vfmaddss,
  OP_vfmaddsd,
  OP_vfmsubps,
  OP_vfmsubpd,
  OP_vfmsubss,
  OP_vfmsubsd,
  OP_vfnmaddps,
  OP_vfnmaddpd,
  OP_vfnmaddss,
  OP_vfnmaddsd,
  OP_vfnmsubps,
  OP_vfnmsubpd,
  OP_vfnmsubss,
  OP_vfnmsubsd,
  OP_vfrczps,
  OP_vfrczpd,
  OP_vfrczss,
  OP_vfrczsd,
  OP_vpcmov,
  OP_vpcomb,
  OP_vpcomw,
  OP_vpcomd,
  OP_vpcomq,
  OP_vpcomub,
  OP_vpcomuw,
  OP_vpcomud,
  OP_vpcomuq,
  OP_vpermil2pd,
  OP_vpermil2ps,
  OP_vphaddbw,
  OP_vphaddbd,
  OP_vphaddbq,
  OP_vphaddwd,
  OP_vphaddwq,
  OP_vphadddq,
  OP_vphaddubw,
  OP_vphaddubd,
  OP_vphaddubq,
  OP_vphadduwd,
  OP_vphadduwq,
  OP_vphaddudq,
  OP_vphsubbw,
  OP_vphsubwd,
  OP_vphsubdq,
  OP_vpmacssww,
  OP_vpmacsswd,
  OP_vpmacssdql,
  OP_vpmacssdd,
  OP_vpmacssdqh,
  OP_vpmacsww,
  OP_vpmacswd,
  OP_vpmacsdql,
  OP_vpmacsdd,
  OP_vpmacsdqh,
  OP_vpmadcsswd,
  OP_vpmadcswd,
  OP_vpperm,
  OP_vprotb,
  OP_vprotw,
  OP_vprotd,
  OP_vprotq,
  OP_vpshlb,
  OP_vpshlw,
  OP_vpshld,
  OP_vpshlq,
  OP_vpshab,
  OP_vpshaw,
  OP_vpshad,
  OP_vpshaq,
  OP_bextr,
  OP_blcfill,
  OP_blci,
  OP_blcic,
  OP_blcmsk,
  OP_blcs,
  OP_blsfill,
  OP_blsic,
  OP_t1mskc,
  OP_tzmsk,
  OP_llwpcb,
  OP_slwpcb,
  OP_lwpins,
  OP_lwpval,
  OP_andn,
  OP_blsr,
  OP_blsmsk,
  OP_blsi,
  OP_tzcnt,
  OP_bzhi,
  OP_pext,
  OP_pdep,
  OP_sarx,
  OP_shlx,
  OP_shrx,
  OP_rorx,
  OP_mulx,
  OP_getsec,
  OP_vmfunc,
  OP_invpcid,
  OP_xabort,
  OP_xbegin,
  OP_xend,
  OP_xtest,
  OP_vpgatherdd,
  OP_vpgatherdq,
  OP_vpgatherqd,
  OP_vpgatherqq,
  OP_vgatherdps,
  OP_vgatherdpd,
  OP_vgatherqps,
  OP_vgatherqpd,
  OP_vbroadcasti128,
  OP_vinserti128,
  OP_vextracti128,
  OP_vpmaskmovd,
  OP_vpmaskmovq,
  OP_vperm2i128,
  OP_vpermd,
  OP_vpermps,
  OP_vpermq,
  OP_vpermpd,
  OP_vpblendd,
  OP_vpsllvd,
  OP_vpsllvq,
  OP_vpsravd,
  OP_vpsrlvd,
  OP_vpsrlvq,
  OP_vpbroadcastb,
  OP_vpbroadcastw,
  OP_vpbroadcastd,
  OP_vpbroadcastq,
  OP_xsavec32,
  OP_xsavec64,
  OP_adox,
  OP_adcx,
  OP_kmovw,
  OP_kmovb,
  OP_kmovq,
  OP_kmovd,
  OP_kandw,
  OP_kandb,
  OP_kandq,
  OP_kandd,
  OP_kandnw,
  OP_kandnb,
  OP_kandnq,
  OP_kandnd,
  OP_kunpckbw,
  OP_kunpckwd,
  OP_kunpckdq,
  OP_knotw,
  OP_knotb,
  OP_knotq,
  OP_knotd,
  OP_korw,
  OP_korb,
  OP_korq,
  OP_kord,
  OP_kxnorw,
  OP_kxnorb,
  OP_kxnorq,
  OP_kxnord,
  OP_kxorw,
  OP_kxorb,
  OP_kxorq,
  OP_kxord,
  OP_kaddw,
  OP_kaddb,
  OP_kaddq,
  OP_kaddd,
  OP_kortestw,
  OP_kortestb,
  OP_kortestq,
  OP_kortestd,
  OP_kshiftlw,
  OP_kshiftlb,
  OP_kshiftlq,
  OP_kshiftld,
  OP_kshiftrw,
  OP_kshiftrb,
  OP_kshiftrq,
  OP_kshiftrd,
  OP_ktestw,
  OP_ktestb,
  OP_ktestq,
  OP_ktestd,
  OP_valignd,
  OP_valignq,
  OP_vblendmpd,
  OP_vblendmps,
  OP_vbroadcastf32x2,
  OP_vbroadcastf32x4,
  OP_vbroadcastf32x8,
  OP_vbroadcastf64x2,
  OP_vbroadcastf64x4,
  OP_vbroadcasti32x2,
  OP_vbroadcasti32x4,
  OP_vbroadcasti32x8,
  OP_vbroadcasti64x2,
  OP_vbroadcasti64x4,
  OP_vcompresspd,
  OP_vcompressps,
  OP_vcvtpd2qq,
  OP_vcvtpd2udq,
  OP_vcvtpd2uqq,
  OP_vcvtps2qq,
  OP_vcvtps2udq,
  OP_vcvtps2uqq,
  OP_vcvtqq2pd,
  OP_vcvtqq2ps,
  OP_vcvtsd2usi,
  OP_vcvtss2usi,
  OP_vcvttpd2qq,
  OP_vcvttpd2udq,
  OP_vcvttpd2uqq,
  OP_vcvttps2qq,
  OP_vcvttps2udq,
  OP_vcvttps2uqq,
  OP_vcvttsd2usi,
  OP_vcvttss2usi,
  OP_vcvtudq2pd,
  OP_vcvtudq2ps,
  OP_vcvtuqq2pd,
  OP_vcvtuqq2ps,
  OP_vcvtusi2sd,
  OP_vcvtusi2ss,
  OP_vdbpsadbw,
  OP_vexp2pd,
  OP_vexp2ps,
  OP_vexpandpd,
  OP_vexpandps,
  OP_vextractf32x4,
  OP_vextractf32x8,
  OP_vextractf64x2,
  OP_vextractf64x4,
  OP_vextracti32x4,
  OP_vextracti32x8,
  OP_vextracti64x2,
  OP_vextracti64x4,
  OP_vfixupimmpd,
  OP_vfixupimmps,
  OP_vfixupimmsd,
  OP_vfixupimmss,
  OP_vfpclasspd,
  OP_vfpclassps,
  OP_vfpclasssd,
  OP_vfpclassss,
  OP_vgatherpf0dpd,
  OP_vgatherpf0dps,
  OP_vgatherpf0qpd,
  OP_vgatherpf0qps,
  OP_vgatherpf1dpd,
  OP_vgatherpf1dps,
  OP_vgatherpf1qpd,
  OP_vgatherpf1qps,
  OP_vgetexppd,
  OP_vgetexpps,
  OP_vgetexpsd,
  OP_vgetexpss,
  OP_vgetmantpd,
  OP_vgetmantps,
  OP_vgetmantsd,
  OP_vgetmantss,
  OP_vinsertf32x4,
  OP_vinsertf32x8,
  OP_vinsertf64x2,
  OP_vinsertf64x4,
  OP_vinserti32x4,
  OP_vinserti32x8,
  OP_vinserti64x2,
  OP_vinserti64x4,
  OP_vmovdqa32,
  OP_vmovdqa64,
  OP_vmovdqu16,
  OP_vmovdqu32,
  OP_vmovdqu64,
  OP_vmovdqu8,
  OP_vpabsq,
  OP_vpandd,
  OP_vpandnd,
  OP_vpandnq,
  OP_vpandq,
  OP_vpblendmb,
  OP_vpblendmd,
  OP_vpblendmq,
  OP_vpblendmw,
  OP_vpbroadcastmb2q,
  OP_vpbroadcastmw2d,
  OP_vpcmpb,
  OP_vpcmpd,
  OP_vpcmpq,
  OP_vpcmpub,
  OP_vpcmpud,
  OP_vpcmpuq,
  OP_vpcmpuw,
  OP_vpcmpw,
  OP_vpcompressd,
  OP_vpcompressq,
  OP_vpconflictd,
  OP_vpconflictq,
  OP_vpermb,
  OP_vpermi2b,
  OP_vpermi2d,
  OP_vpermi2pd,
  OP_vpermi2ps,
  OP_vpermi2q,
  OP_vpermi2w,
  OP_vpermt2b,
  OP_vpermt2d,
  OP_vpermt2pd,
  OP_vpermt2ps,
  OP_vpermt2q,
  OP_vpermt2w,
  OP_vpermw,
  OP_vpexpandd,
  OP_vpexpandq,
  OP_vpextrq,
  OP_vpinsrq,
  OP_vplzcntd,
  OP_vplzcntq,
  OP_vpmadd52huq,
  OP_vpmadd52luq,
  OP_vpmaxsq,
  OP_vpmaxuq,
  OP_vpminsq,
  OP_vpminuq,
  OP_vpmovb2m,
  OP_vpmovd2m,
  OP_vpmovdb,
  OP_vpmovdw,
  OP_vpmovm2b,
  OP_vpmovm2d,
  OP_vpmovm2q,
  OP_vpmovm2w,
  OP_vpmovq2m,
  OP_vpmovqb,
  OP_vpmovqd,
  OP_vpmovqw,
  OP_vpmovsdb,
  OP_vpmovsdw,
  OP_vpmovsqb,
  OP_vpmovsqd,
  OP_vpmovsqw,
  OP_vpmovswb,
  OP_vpmovusdb,
  OP_vpmovusdw,
  OP_vpmovusqb,
  OP_vpmovusqd,
  OP_vpmovusqw,
  OP_vpmovuswb,
  OP_vpmovw2m,
  OP_vpmovwb,
  OP_vpmullq,
  OP_vpord,
  OP_vporq,
  OP_vprold,
  OP_vprolq,
  OP_vprolvd,
  OP_vprolvq,
  OP_vprord,
  OP_vprorq,
  OP_vprorvd,
  OP_vprorvq,
  OP_vpscatterdd,
  OP_vpscatterdq,
  OP_vpscatterqd,
  OP_vpscatterqq,
  OP_vpsllvw,
  OP_vpsraq,
  OP_vpsravq,
  OP_vpsravw,
  OP_vpsrlvw,
  OP_vpternlogd,
  OP_vpternlogq,
  OP_vptestmb,
  OP_vptestmd,
  OP_vptestmq,
  OP_vptestmw,
  OP_vptestnmb,
  OP_vptestnmd,
  OP_vptestnmq,
  OP_vptestnmw,
  OP_vpxord,
  OP_vpxorq,
  OP_vrangepd,
  OP_vrangeps,
  OP_vrangesd,
  OP_vrangess,
  OP_vrcp14pd,
  OP_vrcp14ps,
  OP_vrcp14sd,
  OP_vrcp14ss,
  OP_vrcp28pd,
  OP_vrcp28ps,
  OP_vrcp28sd,
  OP_vrcp28ss,
  OP_vreducepd,
  OP_vreduceps,
  OP_vreducesd,
  OP_vreducess,
  OP_vrndscalepd,
  OP_vrndscaleps,
  OP_vrndscalesd,
  OP_vrndscaless,
  OP_vrsqrt14pd,
  OP_vrsqrt14ps,
  OP_vrsqrt14sd,
  OP_vrsqrt14ss,
  OP_vrsqrt28pd,
  OP_vrsqrt28ps,
  OP_vrsqrt28sd,
  OP_vrsqrt28ss,
  OP_vscalefpd,
  OP_vscalefps,
  OP_vscalefsd,
  OP_vscalefss,
  OP_vscatterdpd,
  OP_vscatterdps,
  OP_vscatterqpd,
  OP_vscatterqps,
  OP_vscatterpf0dpd,
  OP_vscatterpf0dps,
  OP_vscatterpf0qpd,
  OP_vscatterpf0qps,
  OP_vscatterpf1dpd,
  OP_vscatterpf1dps,
  OP_vscatterpf1qpd,
  OP_vscatterpf1qps,
  OP_vshuff32x4,
  OP_vshuff64x2,
  OP_vshufi32x4,
  OP_vshufi64x2,
  OP_sha1msg1,
  OP_sha1msg2,
  OP_sha1nexte,
  OP_sha1rnds4,
  OP_sha256msg1,
  OP_sha256msg2,
  OP_sha256rnds2,
  OP_bndcl,
  OP_bndcn,
  OP_bndcu,
  OP_bndldx,
  OP_bndmk,
  OP_bndmov,
  OP_bndstx,
  OP_ptwrite,
  OP_monitorx,
  OP_mwaitx,
  OP_rdpkru,
  OP_wrpkru,
  OP_encls,
  OP_enclu,
  OP_enclv,
  OP_vpdpbusd,
  OP_vpdpbusds,
  OP_vpdpwssd,
  OP_vpdpwssds,
  OP_vcvtne2ps2bf16,
  OP_vcvtneps2bf16,
  OP_vdpbf16ps ,
  OP_FIRST = OP_add,
  OP_LAST = OP_AFTER_LAST - 1,
  OPSZ_NA = 0 ,
  OPSZ_0,
  OPSZ_1,
  OPSZ_2,
  OPSZ_4,
  OPSZ_6,
  OPSZ_8,
  OPSZ_10,
  OPSZ_16,
  OPSZ_14,
  OPSZ_28,
  OPSZ_94,
  OPSZ_108,
  OPSZ_512,
  OPSZ_2_short1,
  OPSZ_4_short2,
  OPSZ_4_rex8_short2,
  OPSZ_4_rex8,
  OPSZ_6_irex10_short4,
  OPSZ_8_short2,
  OPSZ_8_short4,
  OPSZ_28_short14,
  OPSZ_108_short94,
  OPSZ_4x8,
  OPSZ_6x10,
  OPSZ_4x8_short2,
  OPSZ_4x8_short2xi8,
  OPSZ_4_short2xi4,
  OPSZ_1_reg4,
  OPSZ_2_reg4,
  OPSZ_4_reg16,
  OPSZ_xsave,
  OPSZ_12,
  OPSZ_32,
  OPSZ_40,
  OPSZ_32_short16,
  OPSZ_8_rex16,
  OPSZ_8_rex16_short4,
  OPSZ_12_rex40_short6,
  OPSZ_16_vex32,
  OPSZ_15,
  OPSZ_3,
  OPSZ_1b,
  OPSZ_2b,
  OPSZ_3b,
  OPSZ_4b,
  OPSZ_5b,
  OPSZ_6b,
  OPSZ_7b,
  OPSZ_9b,
  OPSZ_10b,
  OPSZ_11b,
  OPSZ_12b,
  OPSZ_20b,
  OPSZ_25b,
  OPSZ_VAR_REGLIST,
  OPSZ_20,
  OPSZ_24,
  OPSZ_36,
  OPSZ_44,
  OPSZ_48,
  OPSZ_52,
  OPSZ_56,
  OPSZ_60,
  OPSZ_64,
  OPSZ_68,
  OPSZ_72,
  OPSZ_76,
  OPSZ_80,
  OPSZ_84,
  OPSZ_88,
  OPSZ_92,
  OPSZ_96,
  OPSZ_100,
  OPSZ_104,
  OPSZ_112,
  OPSZ_116,
  OPSZ_120,
  OPSZ_124,
  OPSZ_128,
  OPSZ_SCALABLE,
  OPSZ_SCALABLE_PRED,
  OPSZ_16_vex32_evex64,
  OPSZ_vex32_evex64,
  OPSZ_16_of_32_evex64,
  OPSZ_32_of_64,
  OPSZ_4_of_32_evex64,
  OPSZ_8_of_32_evex64,
  OPSZ_8x16 ,
  VENDOR_INTEL,
  VENDOR_AMD,
  VENDOR_ARM,
  VENDOR_UNKNOWN,
  DR_MAP_PRIVATE = 0x0001,
  DR_MAP_FIXED = 0x0002,
  DR_MAP_IMAGE = 0x0004,
  DR_MAP_CACHE_REACHABLE = 0x0008,
  DRMGR_PRIORITY_APP2APP_DRBBDUP = 6500,
  DRMGR_PRIORITY_INSERT_DRBBDUP = -6500 ,
  DRMGR_PRIORITY_INSERT_DRREG_HIGH = -7500,
  DRMGR_PRIORITY_INSERT_DRREG_LOW = 7500,
  DRMGR_PRIORITY_FAULT_DRREG = -7500 ,
  DRSYM_TYPE_OTHER,
  DRSYM_TYPE_INT,
  DRSYM_TYPE_PTR,
  DRSYM_TYPE_FUNC,
  DRSYM_TYPE_VOID,
  DRSYM_TYPE_COMPOUND ,
  DRMGR_PRIORITY_APP2APP_DRWRAP = -500,
  DRMGR_PRIORITY_INSERT_DRWRAP = 500,
  DRMGR_PRIORITY_FAULT_DRWRAP = 500,
  DRMGR_PRIORITY_FAULT_DRX = -7500
}
 

Detailed Description

ARM-specific instruction creation convenience macros.

Macro Definition Documentation

◆ dr_ir_macros_arm_hlt

#define dr_ir_macros_arm_hlt (   dc,
  imm 
)    instr_create_0dst_1src((dc), OP_hlt, (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.

◆ dr_ir_macros_arm_hvc

#define dr_ir_macros_arm_hvc (   dc,
  imm 
)    instr_create_0dst_1src((dc), OP_hvc, (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_adc

#define INSTR_CREATE_adc (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_adc_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_adc, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_adc_shimm

#define INSTR_CREATE_adc_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_adc, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_adc_shreg

#define INSTR_CREATE_adc_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_adc, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_adcs

#define INSTR_CREATE_adcs (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_adcs_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_adcs, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_adcs_shimm

#define INSTR_CREATE_adcs_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_adcs, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_adcs_shreg

#define INSTR_CREATE_adcs_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_adcs, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_add

#define INSTR_CREATE_add (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_add_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_add, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_add_shimm

#define INSTR_CREATE_add_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_add, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_add_shreg

#define INSTR_CREATE_add_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_add, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_adds

#define INSTR_CREATE_adds (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_adds_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_adds, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_adds_shimm

#define INSTR_CREATE_adds_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_adds, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_adds_shreg

#define INSTR_CREATE_adds_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_adds, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_addw

#define INSTR_CREATE_addw (   dc,
  Rd,
  Rn,
  imm 
)     instr_create_1dst_2src((dc), OP_addw, (Rd), (Rn), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_aesd_8

#define INSTR_CREATE_aesd_8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_aesd_8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_aese_8

#define INSTR_CREATE_aese_8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_aese_8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_aesimc_8

#define INSTR_CREATE_aesimc_8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_aesimc_8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_aesmc_8

#define INSTR_CREATE_aesmc_8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_aesmc_8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_and

#define INSTR_CREATE_and (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_and_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_and, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_and_shimm

#define INSTR_CREATE_and_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_and, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_and_shreg

#define INSTR_CREATE_and_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_and, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_ands

#define INSTR_CREATE_ands (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_ands_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_ands, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_ands_shimm

#define INSTR_CREATE_ands_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_ands, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ands_shreg

#define INSTR_CREATE_ands_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_ands, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_asr

#define INSTR_CREATE_asr (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)     instr_create_1dst_2src((dc), OP_asr, (Rd), (Rn), (Rm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_asrs

#define INSTR_CREATE_asrs (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)     instr_create_1dst_2src((dc), OP_asrs, (Rd), (Rn), (Rm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_b

#define INSTR_CREATE_b (   dc,
  pc 
)    instr_create_0dst_1src((dc), OP_b, (pc))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
pcThe program counter constant opnd_t operand.

◆ INSTR_CREATE_b_short [1/2]

#define INSTR_CREATE_b_short (   dc,
  pc 
)    instr_create_0dst_1src((dc), OP_b_short, (pc))

This macro creats an instr_t for a jump instruction with a short reach, automatically supplying any implicit operands.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
pcThe program counter constant opnd_t operand.

◆ INSTR_CREATE_b_short [2/2]

#define INSTR_CREATE_b_short (   dc,
  pc 
)    instr_create_0dst_1src((dc), OP_b_short, (pc))

This macro creats an instr_t for a jump instruction with a short reach, automatically supplying any implicit operands.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
pcThe program counter constant opnd_t operand.

◆ INSTR_CREATE_bfc

#define INSTR_CREATE_bfc (   dc,
  Rd,
  imm,
  imm2 
)     instr_create_1dst_3src((dc), OP_bfc, (Rd), (imm), (imm2), (Rd))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_bfi

#define INSTR_CREATE_bfi (   dc,
  Rd,
  Rm,
  imm,
  imm2 
)     instr_create_1dst_4src((dc), OP_bfi, (Rd), (Rm), (imm), (imm2), (Rd))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_bic

#define INSTR_CREATE_bic (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_bic_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_bic, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_bic_shimm

#define INSTR_CREATE_bic_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_bic, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_bic_shreg

#define INSTR_CREATE_bic_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_bic, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_bics

#define INSTR_CREATE_bics (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_bics_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_bics, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_bics_shimm

#define INSTR_CREATE_bics_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_bics, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_bics_shreg

#define INSTR_CREATE_bics_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_bics, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_bkpt

#define INSTR_CREATE_bkpt (   dc,
  imm 
)    instr_create_0dst_1src((dc), OP_bkpt, (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_bl

#define INSTR_CREATE_bl (   dc,
  pc 
)     instr_create_1dst_1src((dc), OP_bl, opnd_create_reg(DR_REG_LR), (pc))

This macro creats an instr_t for a jump instruction with a short reach, automatically supplying any implicit operands.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
pcThe program counter constant opnd_t operand.

◆ INSTR_CREATE_blx

#define INSTR_CREATE_blx (   dc,
  pc 
)     instr_create_1dst_1src((dc), OP_blx, opnd_create_reg(DR_REG_LR), (pc))

This macro creats an instr_t for a jump instruction with a short reach, automatically supplying any implicit operands.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
pcThe program counter constant opnd_t operand.

◆ INSTR_CREATE_blx_ind

#define INSTR_CREATE_blx_ind (   dc,
  Rm 
)     instr_create_1dst_1src((dc), OP_blx_ind, opnd_create_reg(DR_REG_LR), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_bx

#define INSTR_CREATE_bx (   dc,
  Rm 
)    instr_create_0dst_1src((dc), OP_bx, (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_bxj

#define INSTR_CREATE_bxj (   dc,
  Rm 
)    instr_create_0dst_1src((dc), OP_bxj, (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_cbnz

#define INSTR_CREATE_cbnz (   dc,
  pc,
  Rn 
)    instr_create_0dst_2src((dc), OP_cbnz, (pc), (Rn))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
pcThe program counter constant opnd_t operand.
RnThe source register opnd_t operand.

◆ INSTR_CREATE_cbz

#define INSTR_CREATE_cbz (   dc,
  pc,
  Rn 
)    instr_create_0dst_2src((dc), OP_cbz, (pc), (Rn))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
pcThe program counter constant opnd_t operand.
RnThe source register opnd_t operand.

◆ INSTR_CREATE_cdp

#define INSTR_CREATE_cdp (   dc,
  cpreg,
  imm,
  imm2,
  cpreg2,
  cpreg3,
  imm3 
)
Value:
instr_create_1dst_5src((dc), OP_cdp, (cpreg), (imm), (imm2), (cpreg2), (cpreg3), \
(imm3))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
cpreg2The second coprocessor register opnd_t operand.
cpreg3The third coprocessor register opnd_t operand.
imm3The third integer constant opnd_t operand.

◆ INSTR_CREATE_cdp2

#define INSTR_CREATE_cdp2 (   dc,
  cpreg,
  imm,
  imm2,
  cpreg2,
  cpreg3 
)     instr_create_1dst_4src((dc), OP_cdp2, (cpreg), (imm), (imm2), (cpreg2), (cpreg3))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
cpreg2The second coprocessor register opnd_t operand.
cpreg3The third coprocessor register opnd_t operand.

◆ INSTR_CREATE_clrex

#define INSTR_CREATE_clrex (   dc)    instr_create_0dst_0src((dc), OP_clrex)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ INSTR_CREATE_clz

#define INSTR_CREATE_clz (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src((dc), OP_clz, (Rd), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_cmn

#define INSTR_CREATE_cmn (   dc,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_cmn_shimm((dc), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_0dst_2src((dc), OP_cmn, (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_cmn_shimm

#define INSTR_CREATE_cmn_shimm (   dc,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_0dst_4src((dc), OP_cmn, (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_cmn_shreg

#define INSTR_CREATE_cmn_shreg (   dc,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_0dst_4src((dc), OP_cmn, (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_cmp

#define INSTR_CREATE_cmp (   dc,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_cmp_shimm((dc), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_0dst_2src((dc), OP_cmp, (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_cmp_shimm

#define INSTR_CREATE_cmp_shimm (   dc,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_0dst_4src((dc), OP_cmp, (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_cmp_shreg

#define INSTR_CREATE_cmp_shreg (   dc,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_0dst_4src((dc), OP_cmp, (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_cps

#define INSTR_CREATE_cps (   dc,
  imm 
)    instr_create_0dst_1src((dc), OP_cps, (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_cpsid

#define INSTR_CREATE_cpsid (   dc,
  imm 
)    instr_create_0dst_1src((dc), OP_cpsid, (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_cpsid_noflags

#define INSTR_CREATE_cpsid_noflags (   dc,
  imm,
  imm2 
)     instr_create_0dst_2src((dc), OP_cpsid, (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_cpsie

#define INSTR_CREATE_cpsie (   dc,
  imm 
)    instr_create_0dst_1src((dc), OP_cpsie, (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_cpsie_noflags

#define INSTR_CREATE_cpsie_noflags (   dc,
  imm,
  imm2 
)     instr_create_0dst_2src((dc), OP_cpsie, (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_crc32b

#define INSTR_CREATE_crc32b (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_crc32b, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_crc32cb

#define INSTR_CREATE_crc32cb (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_crc32cb, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_crc32ch

#define INSTR_CREATE_crc32ch (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_crc32ch, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_crc32cw

#define INSTR_CREATE_crc32cw (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_crc32cw, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_crc32h

#define INSTR_CREATE_crc32h (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_crc32h, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_crc32w

#define INSTR_CREATE_crc32w (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_crc32w, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_dbg

#define INSTR_CREATE_dbg (   dc,
  imm 
)    instr_create_0dst_1src((dc), OP_dbg, (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_dcps1

#define INSTR_CREATE_dcps1 (   dc)    instr_create_0dst_0src((dc), OP_dcps1)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ INSTR_CREATE_dcps2

#define INSTR_CREATE_dcps2 (   dc)    instr_create_0dst_0src((dc), OP_dcps2)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ INSTR_CREATE_dcps3

#define INSTR_CREATE_dcps3 (   dc)    instr_create_0dst_0src((dc), OP_dcps3)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ INSTR_CREATE_dmb

#define INSTR_CREATE_dmb (   dc,
  imm 
)    instr_create_0dst_1src((dc), OP_dmb, (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_dsb

#define INSTR_CREATE_dsb (   dc,
  imm 
)    instr_create_0dst_1src((dc), OP_dsb, (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_enterx

#define INSTR_CREATE_enterx (   dc)    instr_create_0dst_0src((dc), OP_enterx)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ INSTR_CREATE_eor

#define INSTR_CREATE_eor (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_eor_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_eor, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_eor_shimm

#define INSTR_CREATE_eor_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_eor, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_eor_shreg

#define INSTR_CREATE_eor_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_eor, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_eors

#define INSTR_CREATE_eors (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_eors_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_eors, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_eors_shimm

#define INSTR_CREATE_eors_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_eors, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_eors_shreg

#define INSTR_CREATE_eors_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_eors, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_eret

#define INSTR_CREATE_eret (   dc)     instr_create_0dst_1src((dc), OP_eret, opnd_create_reg(DR_REG_LR))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ INSTR_CREATE_eret_imm

#define INSTR_CREATE_eret_imm (   dc,
  imm 
)     instr_create_0dst_2src((dc), OP_eret, opnd_create_reg(DR_REG_LR), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_isb

#define INSTR_CREATE_isb (   dc,
  imm 
)    instr_create_0dst_1src((dc), OP_isb, (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_it

#define INSTR_CREATE_it (   dc,
  imm,
  imm2 
)    instr_create_0dst_2src((dc), OP_it, (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_lda

#define INSTR_CREATE_lda (   dc,
  Rd,
  mem 
)    instr_create_1dst_1src((dc), OP_lda, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldab

#define INSTR_CREATE_ldab (   dc,
  Rd,
  mem 
)    instr_create_1dst_1src((dc), OP_ldab, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldaex

#define INSTR_CREATE_ldaex (   dc,
  Rd,
  mem 
)     instr_create_1dst_1src((dc), OP_ldaex, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldaexb

#define INSTR_CREATE_ldaexb (   dc,
  Rd,
  mem 
)     instr_create_1dst_1src((dc), OP_ldaexb, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldaexd

#define INSTR_CREATE_ldaexd (   dc,
  Rd,
  Rd2,
  mem 
)     instr_create_2dst_1src((dc), OP_ldaexd, (Rd), (Rd2), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldaexh

#define INSTR_CREATE_ldaexh (   dc,
  Rd,
  mem 
)     instr_create_1dst_1src((dc), OP_ldaexh, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldah

#define INSTR_CREATE_ldah (   dc,
  Rd,
  mem 
)    instr_create_1dst_1src((dc), OP_ldah, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldc

#define INSTR_CREATE_ldc (   dc,
  cpreg,
  mem,
  imm 
)     instr_create_1dst_2src((dc), OP_ldc, (cpreg), (mem), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldc2_option

#define INSTR_CREATE_ldc2_option (   dc,
  cpreg,
  mem,
  imm,
  imm2 
)     instr_create_1dst_3src((dc), OP_ldc2, (cpreg), (mem), (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_ldc2_wbimm

#define INSTR_CREATE_ldc2_wbimm (   dc,
  cpreg,
  mem,
  imm,
  imm2 
)
Value:
instr_create_2dst_4src((dc), OP_ldc2, (cpreg), opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_ldc2l_option

#define INSTR_CREATE_ldc2l_option (   dc,
  cpreg,
  mem,
  imm,
  imm2 
)     instr_create_1dst_3src((dc), OP_ldc2l, (cpreg), (mem), (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_ldc2l_wbimm

#define INSTR_CREATE_ldc2l_wbimm (   dc,
  cpreg,
  mem,
  imm,
  imm2 
)
Value:
instr_create_2dst_4src((dc), OP_ldc2l, (cpreg), opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_ldc_option

#define INSTR_CREATE_ldc_option (   dc,
  cpreg,
  mem,
  imm,
  imm2 
)     instr_create_1dst_3src((dc), OP_ldc, (cpreg), (mem), (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_ldc_wbimm

#define INSTR_CREATE_ldc_wbimm (   dc,
  cpreg,
  mem,
  imm,
  imm2 
)
Value:
instr_create_2dst_4src((dc), OP_ldc, (cpreg), opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_ldcl

#define INSTR_CREATE_ldcl (   dc,
  cpreg,
  mem,
  imm 
)     instr_create_1dst_2src((dc), OP_ldcl, (cpreg), (mem), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldcl_option

#define INSTR_CREATE_ldcl_option (   dc,
  cpreg,
  mem,
  imm,
  imm2 
)     instr_create_1dst_3src((dc), OP_ldcl, (cpreg), (mem), (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_ldcl_wbimm

#define INSTR_CREATE_ldcl_wbimm (   dc,
  cpreg,
  mem,
  imm,
  imm2 
)
Value:
instr_create_2dst_4src((dc), OP_ldcl, (cpreg), opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_ldm

#define INSTR_CREATE_ldm (   dc,
  mem,
  list_len,
  ... 
)     instr_create_Ndst_Msrc_vardst((dc), OP_ldm, 0, 1, list_len, 0, (mem), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_ldm_priv

#define INSTR_CREATE_ldm_priv (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_ldm_priv, 0, 1, list_len, 0, (mem), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_ldm_priv_wb

#define INSTR_CREATE_ldm_priv_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_ldm_priv, 1, 2, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_ldm_wb

#define INSTR_CREATE_ldm_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_ldm, 1, 2, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_ldmda

#define INSTR_CREATE_ldmda (   dc,
  mem,
  list_len,
  ... 
)     instr_create_Ndst_Msrc_vardst((dc), OP_ldmda, 0, 1, list_len, 0, (mem), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_ldmda_priv

#define INSTR_CREATE_ldmda_priv (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_ldmda_priv, 0, 1, list_len, 0, (mem), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_ldmda_priv_wb

#define INSTR_CREATE_ldmda_priv_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_ldmda_priv, 1, 2, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_ldmda_wb

#define INSTR_CREATE_ldmda_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_ldmda, 1, 2, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_ldmdb

#define INSTR_CREATE_ldmdb (   dc,
  mem,
  list_len,
  ... 
)     instr_create_Ndst_Msrc_vardst((dc), OP_ldmdb, 0, 1, list_len, 0, (mem), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_ldmdb_priv

#define INSTR_CREATE_ldmdb_priv (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_ldmdb_priv, 0, 1, list_len, 0, (mem), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_ldmdb_priv_wb

#define INSTR_CREATE_ldmdb_priv_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_ldmdb_priv, 1, 2, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_ldmdb_wb

#define INSTR_CREATE_ldmdb_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_ldmdb, 1, 2, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_ldmib

#define INSTR_CREATE_ldmib (   dc,
  mem,
  list_len,
  ... 
)     instr_create_Ndst_Msrc_vardst((dc), OP_ldmib, 0, 1, list_len, 0, (mem), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_ldmib_priv

#define INSTR_CREATE_ldmib_priv (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_ldmib_priv, 0, 1, list_len, 0, (mem), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_ldmib_wb

#define INSTR_CREATE_ldmib_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_ldmib, 1, 2, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_ldr

#define INSTR_CREATE_ldr (   dc,
  Rd,
  mem 
)    instr_create_1dst_1src((dc), OP_ldr, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldr_wbimm

#define INSTR_CREATE_ldr_wbimm (   dc,
  Rd,
  mem,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_ldr, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldr_wbreg

#define INSTR_CREATE_ldr_wbreg (   dc,
  Rd,
  mem,
  Rm,
  shift,
  imm 
)
Value:
instr_create_2dst_5src((dc), OP_ldr, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldrb

#define INSTR_CREATE_ldrb (   dc,
  Rd,
  mem 
)    instr_create_1dst_1src((dc), OP_ldrb, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldrb_wbimm

#define INSTR_CREATE_ldrb_wbimm (   dc,
  Rd,
  mem,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_ldrb, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldrb_wbreg

#define INSTR_CREATE_ldrb_wbreg (   dc,
  Rd,
  mem,
  Rm,
  shift,
  imm 
)
Value:
instr_create_2dst_5src((dc), OP_ldrb, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldrbt

#define INSTR_CREATE_ldrbt (   dc,
  Rd,
  mem 
)     instr_create_1dst_1src((dc), OP_ldrbt, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldrbt_wbimm

#define INSTR_CREATE_ldrbt_wbimm (   dc,
  Rd,
  mem,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_ldrbt, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldrbt_wbreg

#define INSTR_CREATE_ldrbt_wbreg (   dc,
  Rd,
  mem,
  Rm,
  shift,
  imm 
)
Value:
instr_create_2dst_5src((dc), OP_ldrbt, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldrd

#define INSTR_CREATE_ldrd (   dc,
  Rd,
  Rd2,
  mem 
)     instr_create_2dst_1src((dc), OP_ldrd, (Rd), (Rd2), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldrd_wbimm

#define INSTR_CREATE_ldrd_wbimm (   dc,
  Rd,
  Rd2,
  mem,
  imm 
)
Value:
instr_create_3dst_3src((dc), OP_ldrd, (Rd), (Rd2), \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldrd_wbreg

#define INSTR_CREATE_ldrd_wbreg (   dc,
  Rd,
  Rd2,
  mem,
  Rm 
)
Value:
instr_create_3dst_3src((dc), OP_ldrd, (Rd), (Rd2), \
opnd_create_reg(opnd_get_base(mem)), (mem), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_ldrex

#define INSTR_CREATE_ldrex (   dc,
  Rd,
  mem 
)     instr_create_1dst_1src((dc), OP_ldrex, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldrexb

#define INSTR_CREATE_ldrexb (   dc,
  Rd,
  mem 
)     instr_create_1dst_1src((dc), OP_ldrexb, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldrexd

#define INSTR_CREATE_ldrexd (   dc,
  Rd,
  Rd2,
  mem 
)     instr_create_2dst_1src((dc), OP_ldrexd, (Rd), (Rd2), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldrexh

#define INSTR_CREATE_ldrexh (   dc,
  Rd,
  mem 
)     instr_create_1dst_1src((dc), OP_ldrexh, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldrh

#define INSTR_CREATE_ldrh (   dc,
  Rd,
  mem 
)    instr_create_1dst_1src((dc), OP_ldrh, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldrh_wbimm

#define INSTR_CREATE_ldrh_wbimm (   dc,
  Rd,
  mem,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_ldrh, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldrh_wbreg

#define INSTR_CREATE_ldrh_wbreg (   dc,
  Rd,
  mem,
  Rm 
)
Value:
instr_create_2dst_3src((dc), OP_ldrh, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_ldrht

#define INSTR_CREATE_ldrht (   dc,
  Rd,
  mem 
)     instr_create_1dst_1src((dc), OP_ldrht, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldrht_wbimm

#define INSTR_CREATE_ldrht_wbimm (   dc,
  Rd,
  mem,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_ldrht, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldrht_wbreg

#define INSTR_CREATE_ldrht_wbreg (   dc,
  Rd,
  mem,
  Rm 
)
Value:
instr_create_2dst_3src((dc), OP_ldrht, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_ldrsb

#define INSTR_CREATE_ldrsb (   dc,
  Rd,
  mem 
)     instr_create_1dst_1src((dc), OP_ldrsb, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldrsb_wbimm

#define INSTR_CREATE_ldrsb_wbimm (   dc,
  Rd,
  mem,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_ldrsb, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldrsb_wbreg

#define INSTR_CREATE_ldrsb_wbreg (   dc,
  Rd,
  mem,
  Rm 
)
Value:
instr_create_2dst_3src((dc), OP_ldrsb, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_ldrsbt

#define INSTR_CREATE_ldrsbt (   dc,
  Rd,
  mem 
)     instr_create_1dst_1src((dc), OP_ldrsbt, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldrsbt_wbimm

#define INSTR_CREATE_ldrsbt_wbimm (   dc,
  Rd,
  mem,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_ldrsbt, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldrsbt_wbreg

#define INSTR_CREATE_ldrsbt_wbreg (   dc,
  Rd,
  mem,
  Rm 
)
Value:
instr_create_2dst_3src((dc), OP_ldrsbt, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_ldrsh

#define INSTR_CREATE_ldrsh (   dc,
  Rd,
  mem 
)     instr_create_1dst_1src((dc), OP_ldrsh, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldrsh_wbimm

#define INSTR_CREATE_ldrsh_wbimm (   dc,
  Rd,
  mem,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_ldrsh, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldrsh_wbreg

#define INSTR_CREATE_ldrsh_wbreg (   dc,
  Rd,
  mem,
  Rm 
)
Value:
instr_create_2dst_3src((dc), OP_ldrsh, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_ldrsht

#define INSTR_CREATE_ldrsht (   dc,
  Rd,
  mem 
)     instr_create_1dst_1src((dc), OP_ldrsht, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldrsht_wbimm

#define INSTR_CREATE_ldrsht_wbimm (   dc,
  Rd,
  mem,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_ldrsht, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldrsht_wbreg

#define INSTR_CREATE_ldrsht_wbreg (   dc,
  Rd,
  mem,
  Rm 
)
Value:
instr_create_2dst_3src((dc), OP_ldrsht, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_ldrt

#define INSTR_CREATE_ldrt (   dc,
  Rd,
  mem 
)    instr_create_1dst_1src((dc), OP_ldrt, (Rd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ldrt_wbimm

#define INSTR_CREATE_ldrt_wbimm (   dc,
  Rd,
  mem,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_ldrt, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_ldrt_wbreg

#define INSTR_CREATE_ldrt_wbreg (   dc,
  Rd,
  mem,
  Rm,
  shift,
  imm 
)
Value:
instr_create_2dst_5src((dc), OP_ldrt, (Rd), opnd_create_reg(opnd_get_base(mem)), \
(mem), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_leavex

#define INSTR_CREATE_leavex (   dc)    instr_create_0dst_0src((dc), OP_leavex)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ INSTR_CREATE_lsl

#define INSTR_CREATE_lsl (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)     instr_create_1dst_2src((dc), OP_lsl, (Rd), (Rn), (Rm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_lsls

#define INSTR_CREATE_lsls (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)     instr_create_1dst_2src((dc), OP_lsls, (Rd), (Rn), (Rm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_lsr

#define INSTR_CREATE_lsr (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)     instr_create_1dst_2src((dc), OP_lsr, (Rd), (Rn), (Rm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_lsrs

#define INSTR_CREATE_lsrs (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)     instr_create_1dst_2src((dc), OP_lsrs, (Rd), (Rn), (Rm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_mcr

#define INSTR_CREATE_mcr (   dc,
  cpreg,
  cpreg2,
  imm,
  imm2,
  Rt,
  imm3 
)     instr_create_2dst_4src((dc), OP_mcr, (cpreg), (cpreg2), (imm), (imm2), (Rt), (imm3))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
cpreg2The second coprocessor register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RtThe source register opnd_t operand.
imm3The third integer constant opnd_t operand.

◆ INSTR_CREATE_mcr2

#define INSTR_CREATE_mcr2 (   dc,
  cpreg,
  cpreg2,
  imm,
  imm2,
  Rt 
)     instr_create_2dst_3src((dc), OP_mcr2, (cpreg), (cpreg2), (imm), (imm2), (Rt))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
cpreg2The second coprocessor register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RtThe source register opnd_t operand.

◆ INSTR_CREATE_mcrr

#define INSTR_CREATE_mcrr (   dc,
  cpreg,
  Rn,
  Rt,
  imm,
  imm2 
)     instr_create_1dst_4src((dc), OP_mcrr, (cpreg), (Rn), (Rt), (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
RnThe source register opnd_t operand.
RtThe source register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_mcrr2

#define INSTR_CREATE_mcrr2 (   dc,
  cpreg,
  Rn,
  Rt,
  imm,
  imm2 
)     instr_create_1dst_4src((dc), OP_mcrr2, (cpreg), (Rn), (Rt), (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
cpregThe coprocessor register opnd_t operand.
RnThe source register opnd_t operand.
RtThe source register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_mla

#define INSTR_CREATE_mla (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_mla, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_mlas

#define INSTR_CREATE_mlas (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_mlas, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_mls

#define INSTR_CREATE_mls (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_mls, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_mov

#define INSTR_CREATE_mov (   dc,
  Rd,
  Rm_or_imm 
)     instr_create_1dst_1src((dc), OP_mov, (Rd), (Rm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rm_or_immThe source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_movs

#define INSTR_CREATE_movs (   dc,
  Rd,
  Rm_or_imm 
)     instr_create_1dst_1src((dc), OP_movs, (Rd), (Rm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rm_or_immThe source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_movt

#define INSTR_CREATE_movt (   dc,
  Rd,
  imm 
)    instr_create_1dst_1src((dc), OP_movt, (Rd), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_movw

#define INSTR_CREATE_movw (   dc,
  Rd,
  imm 
)    instr_create_1dst_1src((dc), OP_movw, (Rd), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_mrc

#define INSTR_CREATE_mrc (   dc,
  Rd,
  imm,
  imm2,
  cpreg,
  cpreg2,
  imm3 
)     instr_create_1dst_5src((dc), OP_mrc, (Rd), (imm), (imm2), (cpreg), (cpreg2), (imm3))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
cpregThe coprocessor register opnd_t operand.
cpreg2The second coprocessor register opnd_t operand.
imm3The third integer constant opnd_t operand.

◆ INSTR_CREATE_mrc2

#define INSTR_CREATE_mrc2 (   dc,
  Rd,
  imm,
  imm2,
  cpreg,
  cpreg2,
  imm3 
)     instr_create_1dst_5src((dc), OP_mrc2, (Rd), (imm), (imm2), (cpreg), (cpreg2), (imm3))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
cpregThe coprocessor register opnd_t operand.
cpreg2The second coprocessor register opnd_t operand.
imm3The third integer constant opnd_t operand.

◆ INSTR_CREATE_mrrc

#define INSTR_CREATE_mrrc (   dc,
  Ra,
  Rd,
  imm,
  imm2,
  cpreg 
)     instr_create_2dst_3src((dc), OP_mrrc, (Ra), (Rd), (imm), (imm2), (cpreg))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RaThe third source register opnd_t operand.
RdThe destination register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
cpregThe coprocessor register opnd_t operand.

◆ INSTR_CREATE_mrrc2

#define INSTR_CREATE_mrrc2 (   dc,
  Ra,
  Rd,
  imm,
  imm2,
  cpreg 
)     instr_create_2dst_3src((dc), OP_mrrc2, (Ra), (Rd), (imm), (imm2), (cpreg))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RaThe third source register opnd_t operand.
RdThe destination register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
cpregThe coprocessor register opnd_t operand.

◆ INSTR_CREATE_mrs

#define INSTR_CREATE_mrs (   dc,
  Rd,
  statreg 
)     instr_create_1dst_1src((dc), OP_mrs, (Rd), (statreg))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.

◆ INSTR_CREATE_mrs_priv

#define INSTR_CREATE_mrs_priv (   dc,
  Rd,
  imm 
)     instr_create_1dst_1src((dc), OP_mrs_priv, (Rd), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_mrs_priv_spsr

#define INSTR_CREATE_mrs_priv_spsr (   dc,
  Rd,
  statreg,
  imm 
)     instr_create_1dst_2src((dc), OP_mrs_priv, (Rd), (statreg), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_msr

#define INSTR_CREATE_msr (   dc,
  statreg,
  imm_msr,
  Rm 
)     instr_create_1dst_2src((dc), OP_msr, (statreg), (imm_msr), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.
imm_msrThe integer constant (typically from OPND_CREATE_INT_MSR*) opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_msr_imm

#define INSTR_CREATE_msr_imm (   dc,
  statreg,
  imm,
  imm2 
)     instr_create_1dst_2src((dc), OP_msr, (statreg), (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_msr_priv

#define INSTR_CREATE_msr_priv (   dc,
  imm,
  Rm 
)     instr_create_0dst_2src((dc), OP_msr_priv, (imm), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_msr_priv_spsr

#define INSTR_CREATE_msr_priv_spsr (   dc,
  statreg,
  imm,
  Rm 
)     instr_create_1dst_2src((dc), OP_msr_priv, (statreg), (imm), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_mul

#define INSTR_CREATE_mul (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_mul, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_muls

#define INSTR_CREATE_muls (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_muls, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_mvn

#define INSTR_CREATE_mvn (   dc,
  Rd,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_mvn_shimm((dc), (Rd), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_1src((dc), OP_mvn, (Rd), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rm_or_immThe source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_mvn_shimm

#define INSTR_CREATE_mvn_shimm (   dc,
  Rd,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_3src((dc), OP_mvn, (Rd), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_mvn_shreg

#define INSTR_CREATE_mvn_shreg (   dc,
  Rd,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_3src((dc), OP_mvn, (Rd), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_mvns

#define INSTR_CREATE_mvns (   dc,
  Rd,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_mvns_shimm((dc), (Rd), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_1src((dc), OP_mvns, (Rd), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rm_or_immThe source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_mvns_shimm

#define INSTR_CREATE_mvns_shimm (   dc,
  Rd,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_3src((dc), OP_mvns, (Rd), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_mvns_shreg

#define INSTR_CREATE_mvns_shreg (   dc,
  Rd,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_3src((dc), OP_mvns, (Rd), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_neg

#define INSTR_CREATE_neg (   dc,
  Rd,
  Rn 
)     INSTR_CREATE_rsb((dc), (Rd), (Rn), OPND_CREATE_INT16(0))

This macro creates an instr_t for a negate instruction, automatically supplying any implicit operands.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.

◆ INSTR_CREATE_nop

#define INSTR_CREATE_nop (   dc)    instr_create_0dst_0src((dc), OP_nop)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ INSTR_CREATE_orn

#define INSTR_CREATE_orn (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_orn_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_orn, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_orn_shimm

#define INSTR_CREATE_orn_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_orn, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_orns

#define INSTR_CREATE_orns (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_orns_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_orns, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_orns_shimm

#define INSTR_CREATE_orns_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_orns, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_orr

#define INSTR_CREATE_orr (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_orr_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_orr, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_orr_shimm

#define INSTR_CREATE_orr_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_orr, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_orr_shreg

#define INSTR_CREATE_orr_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_orr, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_orrs

#define INSTR_CREATE_orrs (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_orrs_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_orrs, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_orrs_shimm

#define INSTR_CREATE_orrs_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_orrs, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_orrs_shreg

#define INSTR_CREATE_orrs_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_orrs, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_pkhbt_shimm

#define INSTR_CREATE_pkhbt_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_pkhbt, (Rd), (Rn), (Rm), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_pkhtb_shimm

#define INSTR_CREATE_pkhtb_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_pkhtb, (Rd), (Rn), (Rm), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_pld

#define INSTR_CREATE_pld (   dc,
  mem 
)    instr_create_0dst_1src((dc), OP_pld, (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.

◆ INSTR_CREATE_pldw

#define INSTR_CREATE_pldw (   dc,
  mem 
)    instr_create_0dst_1src((dc), OP_pldw, (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.

◆ INSTR_CREATE_pli

#define INSTR_CREATE_pli (   dc,
  mem 
)    instr_create_0dst_1src((dc), OP_pli, (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.

◆ INSTR_CREATE_pop

#define INSTR_CREATE_pop (   dc,
  Rd 
)
Value:
INSTR_CREATE_ldr_wbimm((dc), (Rd), OPND_CREATE_MEMPTR(DR_REG_XSP, 0), \
OPND_CREATE_INT16(sizeof(void *)))

This macro creates an instr_t for a pop instruction into a single register, automatically supplying any implicit operands.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.

◆ INSTR_CREATE_pop_list

#define INSTR_CREATE_pop_list (   dc,
  list_len,
  ... 
)     INSTR_CREATE_ldm_wb((dc), OPND_CREATE_MEMLIST(DR_REG_XSP), list_len, __VA_ARGS__)

This macro creates an instr_t for a pop instruction into a list of registers, automatically supplying any implicit operands.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments.

◆ INSTR_CREATE_push

#define INSTR_CREATE_push (   dc,
  Rt 
)
Value:
INSTR_CREATE_str_wbimm((dc), OPND_CREATE_MEMPTR(DR_REG_XSP, -sizeof(void *)), (Rt), \
OPND_CREATE_INT16(-sizeof(void *)))

This macro creates an instr_t for a push instruction of a single register, automatically supplying any implicit operands.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RtThe destination register opnd_t operand.

◆ INSTR_CREATE_push_list

#define INSTR_CREATE_push_list (   dc,
  list_len,
  ... 
)     INSTR_CREATE_stmdb_wb((dc), OPND_CREATE_MEMLIST(DR_REG_XSP), list_len, __VA_ARGS__)

This macro creates an instr_t for a push instruction of a list of registers, automatically supplying any implicit operands.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments.

◆ INSTR_CREATE_qadd

#define INSTR_CREATE_qadd (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_qadd, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_qadd16

#define INSTR_CREATE_qadd16 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_qadd16, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_qadd8

#define INSTR_CREATE_qadd8 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_qadd8, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_qasx

#define INSTR_CREATE_qasx (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_qasx, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_qdadd

#define INSTR_CREATE_qdadd (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_qdadd, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_qdsub

#define INSTR_CREATE_qdsub (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_qdsub, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_qsax

#define INSTR_CREATE_qsax (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_qsax, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_qsub

#define INSTR_CREATE_qsub (   dc,
  Rd,
  Rm,
  Rn 
)     instr_create_1dst_2src((dc), OP_qsub, (Rd), (Rm), (Rn))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.
RnThe source register opnd_t operand.

◆ INSTR_CREATE_qsub16

#define INSTR_CREATE_qsub16 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_qsub16, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_qsub8

#define INSTR_CREATE_qsub8 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_qsub8, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_rbit

#define INSTR_CREATE_rbit (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src((dc), OP_rbit, (Rd), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_rev

#define INSTR_CREATE_rev (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src((dc), OP_rev, (Rd), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_rev16

#define INSTR_CREATE_rev16 (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src((dc), OP_rev16, (Rd), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_revsh

#define INSTR_CREATE_revsh (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src((dc), OP_revsh, (Rd), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_rfe

#define INSTR_CREATE_rfe (   dc,
  statreg,
  mem 
)     instr_create_1dst_1src((dc), OP_rfe, (statreg), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_rfe_wb

#define INSTR_CREATE_rfe_wb (   dc,
  statreg,
  mem 
)
Value:
instr_create_2dst_2src((dc), OP_rfe, opnd_create_reg(opnd_get_base(mem)), (statreg), \
(mem), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_rfeda

#define INSTR_CREATE_rfeda (   dc,
  statreg,
  mem 
)     instr_create_1dst_1src((dc), OP_rfeda, (statreg), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_rfeda_wb

#define INSTR_CREATE_rfeda_wb (   dc,
  statreg,
  mem 
)
Value:
instr_create_2dst_2src((dc), OP_rfeda, opnd_create_reg(opnd_get_base(mem)), \
(statreg), (mem), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_rfedb

#define INSTR_CREATE_rfedb (   dc,
  statreg,
  mem 
)     instr_create_1dst_1src((dc), OP_rfedb, (statreg), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_rfedb_wb

#define INSTR_CREATE_rfedb_wb (   dc,
  statreg,
  mem 
)
Value:
instr_create_2dst_2src((dc), OP_rfedb, opnd_create_reg(opnd_get_base(mem)), \
(statreg), (mem), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_rfeib

#define INSTR_CREATE_rfeib (   dc,
  statreg,
  mem 
)     instr_create_1dst_1src((dc), OP_rfeib, (statreg), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_rfeib_wb

#define INSTR_CREATE_rfeib_wb (   dc,
  statreg,
  mem 
)
Value:
instr_create_2dst_2src((dc), OP_rfeib, opnd_create_reg(opnd_get_base(mem)), \
(statreg), (mem), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_ror

#define INSTR_CREATE_ror (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)     instr_create_1dst_2src((dc), OP_ror, (Rd), (Rn), (Rm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_rors

#define INSTR_CREATE_rors (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)     instr_create_1dst_2src((dc), OP_rors, (Rd), (Rn), (Rm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_rrx

#define INSTR_CREATE_rrx (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src((dc), OP_rrx, (Rd), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_rrxs

#define INSTR_CREATE_rrxs (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src((dc), OP_rrxs, (Rd), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_rsb

#define INSTR_CREATE_rsb (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_rsb_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_rsb, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_rsb_shimm

#define INSTR_CREATE_rsb_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_rsb, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_rsb_shreg

#define INSTR_CREATE_rsb_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_rsb, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_rsbs

#define INSTR_CREATE_rsbs (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_rsbs_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_rsbs, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_rsbs_shimm

#define INSTR_CREATE_rsbs_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_rsbs, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_rsbs_shreg

#define INSTR_CREATE_rsbs_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_rsbs, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_rsc

#define INSTR_CREATE_rsc (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_rsc_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_rsc, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_rsc_shimm

#define INSTR_CREATE_rsc_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_rsc, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_rsc_shreg

#define INSTR_CREATE_rsc_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_rsc, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_rscs

#define INSTR_CREATE_rscs (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_rscs_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_rscs, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_rscs_shimm

#define INSTR_CREATE_rscs_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_rscs, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_rscs_shreg

#define INSTR_CREATE_rscs_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_rscs, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_sadd16

#define INSTR_CREATE_sadd16 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_sadd16, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_sadd8

#define INSTR_CREATE_sadd8 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_sadd8, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_sasx

#define INSTR_CREATE_sasx (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_sasx, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_sbc

#define INSTR_CREATE_sbc (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_sbc_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_sbc, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_sbc_shimm

#define INSTR_CREATE_sbc_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_sbc, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_sbc_shreg

#define INSTR_CREATE_sbc_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_sbc, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_sbcs

#define INSTR_CREATE_sbcs (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_sbcs_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_sbcs, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_sbcs_shimm

#define INSTR_CREATE_sbcs_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_sbcs, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_sbcs_shreg

#define INSTR_CREATE_sbcs_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_sbcs, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_sbfx

#define INSTR_CREATE_sbfx (   dc,
  Rd,
  Rm,
  imm,
  imm2 
)     instr_create_1dst_3src((dc), OP_sbfx, (Rd), (Rm), (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_sdiv

#define INSTR_CREATE_sdiv (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_sdiv, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_sel

#define INSTR_CREATE_sel (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_sel, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_setend

#define INSTR_CREATE_setend (   dc,
  imm 
)    instr_create_0dst_1src((dc), OP_setend, (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_sev

#define INSTR_CREATE_sev (   dc)    instr_create_0dst_0src((dc), OP_sev)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ INSTR_CREATE_sevl

#define INSTR_CREATE_sevl (   dc)    instr_create_0dst_0src((dc), OP_sevl)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ INSTR_CREATE_sha1c_32

#define INSTR_CREATE_sha1c_32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_sha1c_32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_sha1h_32

#define INSTR_CREATE_sha1h_32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_sha1h_32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_sha1m_32

#define INSTR_CREATE_sha1m_32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_sha1m_32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_sha1p_32

#define INSTR_CREATE_sha1p_32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_sha1p_32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_sha1su0_32

#define INSTR_CREATE_sha1su0_32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_sha1su0_32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_sha1su1_32

#define INSTR_CREATE_sha1su1_32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_sha1su1_32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_sha256h2_32

#define INSTR_CREATE_sha256h2_32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_sha256h2_32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_sha256h_32

#define INSTR_CREATE_sha256h_32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_sha256h_32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_sha256su0_32

#define INSTR_CREATE_sha256su0_32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_sha256su0_32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_sha256su1_32

#define INSTR_CREATE_sha256su1_32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_sha256su1_32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_shadd16

#define INSTR_CREATE_shadd16 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_shadd16, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_shadd8

#define INSTR_CREATE_shadd8 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_shadd8, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_shasx

#define INSTR_CREATE_shasx (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_shasx, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_shsax

#define INSTR_CREATE_shsax (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_shsax, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_shsub16

#define INSTR_CREATE_shsub16 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_shsub16, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_shsub8

#define INSTR_CREATE_shsub8 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_shsub8, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smc

#define INSTR_CREATE_smc (   dc,
  imm 
)    instr_create_0dst_1src((dc), OP_smc, (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_smlabb

#define INSTR_CREATE_smlabb (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_smlabb, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_smlabt

#define INSTR_CREATE_smlabt (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_smlabt, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_smlad

#define INSTR_CREATE_smlad (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_smlad, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_smladx

#define INSTR_CREATE_smladx (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_smladx, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_smlal

#define INSTR_CREATE_smlal (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_4src((dc), OP_smlal, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smlalbb

#define INSTR_CREATE_smlalbb (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_4src((dc), OP_smlalbb, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smlalbt

#define INSTR_CREATE_smlalbt (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_4src((dc), OP_smlalbt, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smlald

#define INSTR_CREATE_smlald (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_4src((dc), OP_smlald, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smlaldx

#define INSTR_CREATE_smlaldx (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_4src((dc), OP_smlaldx, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smlals

#define INSTR_CREATE_smlals (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_4src((dc), OP_smlals, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smlaltb

#define INSTR_CREATE_smlaltb (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_4src((dc), OP_smlaltb, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smlaltt

#define INSTR_CREATE_smlaltt (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_4src((dc), OP_smlaltt, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smlatb

#define INSTR_CREATE_smlatb (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_smlatb, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_smlatt

#define INSTR_CREATE_smlatt (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_smlatt, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_smlawb

#define INSTR_CREATE_smlawb (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_smlawb, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_smlawt

#define INSTR_CREATE_smlawt (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_smlawt, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_smlsd

#define INSTR_CREATE_smlsd (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_smlsd, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_smlsdx

#define INSTR_CREATE_smlsdx (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_smlsdx, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_smlsld

#define INSTR_CREATE_smlsld (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_4src((dc), OP_smlsld, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smlsldx

#define INSTR_CREATE_smlsldx (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_4src((dc), OP_smlsldx, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smmla

#define INSTR_CREATE_smmla (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_smmla, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_smmlar

#define INSTR_CREATE_smmlar (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_smmlar, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_smmls

#define INSTR_CREATE_smmls (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_smmls, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_smmlsr

#define INSTR_CREATE_smmlsr (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_smmlsr, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_smmul

#define INSTR_CREATE_smmul (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_smmul, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smmulr

#define INSTR_CREATE_smmulr (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_smmulr, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smuad

#define INSTR_CREATE_smuad (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_smuad, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smuadx

#define INSTR_CREATE_smuadx (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_smuadx, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smulbb

#define INSTR_CREATE_smulbb (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_smulbb, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smulbt

#define INSTR_CREATE_smulbt (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_smulbt, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smull

#define INSTR_CREATE_smull (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_2src((dc), OP_smull, (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smulls

#define INSTR_CREATE_smulls (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_2src((dc), OP_smulls, (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smultb

#define INSTR_CREATE_smultb (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_smultb, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smultt

#define INSTR_CREATE_smultt (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_smultt, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smulwb

#define INSTR_CREATE_smulwb (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_smulwb, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smulwt

#define INSTR_CREATE_smulwt (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_smulwt, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smusd

#define INSTR_CREATE_smusd (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_smusd, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_smusdx

#define INSTR_CREATE_smusdx (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_smusdx, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_srs

#define INSTR_CREATE_srs (   dc,
  mem,
  imm,
  statreg 
)
Value:
instr_create_1dst_3src((dc), OP_srs, (mem), (imm), opnd_create_reg(DR_REG_LR), \
(statreg))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.

◆ INSTR_CREATE_srs_wbimm

#define INSTR_CREATE_srs_wbimm (   dc,
  mem,
  imm,
  statreg 
)
Value:
instr_create_2dst_4src((dc), OP_srs, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg(opnd_get_base(mem)), \
opnd_create_reg(DR_REG_LR), (statreg))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.

◆ INSTR_CREATE_srsda

#define INSTR_CREATE_srsda (   dc,
  mem,
  imm,
  statreg 
)
Value:
instr_create_1dst_3src((dc), OP_srsda, (mem), (imm), opnd_create_reg(DR_REG_LR), \
(statreg))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.

◆ INSTR_CREATE_srsda_wbimm

#define INSTR_CREATE_srsda_wbimm (   dc,
  mem,
  imm,
  statreg 
)
Value:
instr_create_2dst_4src((dc), OP_srsda, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg(opnd_get_base(mem)), \
opnd_create_reg(DR_REG_LR), (statreg))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.

◆ INSTR_CREATE_srsdb

#define INSTR_CREATE_srsdb (   dc,
  mem,
  imm,
  statreg 
)
Value:
instr_create_1dst_3src((dc), OP_srsdb, (mem), (imm), opnd_create_reg(DR_REG_LR), \
(statreg))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.

◆ INSTR_CREATE_srsdb_wbimm

#define INSTR_CREATE_srsdb_wbimm (   dc,
  mem,
  imm,
  statreg 
)
Value:
instr_create_2dst_4src((dc), OP_srsdb, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg(opnd_get_base(mem)), \
opnd_create_reg(DR_REG_LR), (statreg))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.

◆ INSTR_CREATE_srsib

#define INSTR_CREATE_srsib (   dc,
  mem,
  imm,
  statreg 
)
Value:
instr_create_1dst_3src((dc), OP_srsib, (mem), (imm), opnd_create_reg(DR_REG_LR), \
(statreg))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.

◆ INSTR_CREATE_srsib_wbimm

#define INSTR_CREATE_srsib_wbimm (   dc,
  mem,
  imm,
  statreg 
)
Value:
instr_create_2dst_4src((dc), OP_srsib, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg(opnd_get_base(mem)), \
opnd_create_reg(DR_REG_LR), (statreg))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
statregThe status register (usually DR_REG_CPSR) opnd_t operand.

◆ INSTR_CREATE_ssat16

#define INSTR_CREATE_ssat16 (   dc,
  Rd,
  imm,
  Rm 
)     instr_create_1dst_2src((dc), OP_ssat16, (Rd), (imm), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_ssat_shimm

#define INSTR_CREATE_ssat_shimm (   dc,
  Rd,
  imm,
  Rm,
  shift,
  imm2 
)
Value:
instr_create_1dst_4src((dc), OP_ssat, (Rd), (imm), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_ssax

#define INSTR_CREATE_ssax (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_ssax, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_ssub16

#define INSTR_CREATE_ssub16 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_ssub16, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_ssub8

#define INSTR_CREATE_ssub8 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_ssub8, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_stc

#define INSTR_CREATE_stc (   dc,
  mem,
  imm,
  cpreg,
  imm2 
)     instr_create_1dst_3src((dc), OP_stc, (mem), (imm), (cpreg), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
cpregThe coprocessor register opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_stc2

#define INSTR_CREATE_stc2 (   dc,
  mem,
  imm,
  cpreg,
  imm2 
)     instr_create_1dst_3src((dc), OP_stc2, (mem), (imm), (cpreg), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
cpregThe coprocessor register opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_stc2_wbimm

#define INSTR_CREATE_stc2_wbimm (   dc,
  mem,
  imm,
  cpreg,
  imm2 
)
Value:
instr_create_2dst_4src((dc), OP_stc2, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), (cpreg), (imm2), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
cpregThe coprocessor register opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_stc2l

#define INSTR_CREATE_stc2l (   dc,
  mem,
  imm,
  cpreg,
  imm2 
)     instr_create_1dst_3src((dc), OP_stc2l, (mem), (imm), (cpreg), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
cpregThe coprocessor register opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_stc2l_wbimm

#define INSTR_CREATE_stc2l_wbimm (   dc,
  mem,
  imm,
  cpreg,
  imm2 
)
Value:
instr_create_2dst_4src((dc), OP_stc2l, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), (cpreg), (imm2), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
cpregThe coprocessor register opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_stc_wbimm

#define INSTR_CREATE_stc_wbimm (   dc,
  mem,
  imm,
  cpreg,
  imm2 
)
Value:
instr_create_2dst_4src((dc), OP_stc, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), (cpreg), (imm2), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
cpregThe coprocessor register opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_stcl

#define INSTR_CREATE_stcl (   dc,
  mem,
  imm,
  cpreg,
  imm2 
)     instr_create_1dst_3src((dc), OP_stcl, (mem), (imm), (cpreg), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
cpregThe coprocessor register opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_stcl_wbimm

#define INSTR_CREATE_stcl_wbimm (   dc,
  mem,
  imm,
  cpreg,
  imm2 
)
Value:
instr_create_2dst_4src((dc), OP_stcl, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), (cpreg), (imm2), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
cpregThe coprocessor register opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_stl

#define INSTR_CREATE_stl (   dc,
  mem,
  Rm 
)    instr_create_1dst_1src((dc), OP_stl, (mem), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_stlb

#define INSTR_CREATE_stlb (   dc,
  mem,
  Rm 
)    instr_create_1dst_1src((dc), OP_stlb, (mem), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_stlex

#define INSTR_CREATE_stlex (   dc,
  mem,
  Rd,
  Rm 
)     instr_create_2dst_1src((dc), OP_stlex, (mem), (Rd), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_stlexb

#define INSTR_CREATE_stlexb (   dc,
  mem,
  Rd,
  Rm 
)     instr_create_2dst_1src((dc), OP_stlexb, (mem), (Rd), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_stlexd

#define INSTR_CREATE_stlexd (   dc,
  mem,
  Rd,
  Rt,
  Rt2 
)     instr_create_2dst_2src((dc), OP_stlexd, (mem), (Rd), (Rt), (Rt2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RdThe destination register opnd_t operand.
RtThe source register opnd_t operand.
Rt2The second source register opnd_t operand.

◆ INSTR_CREATE_stlexh

#define INSTR_CREATE_stlexh (   dc,
  mem,
  Rd,
  Rm 
)     instr_create_2dst_1src((dc), OP_stlexh, (mem), (Rd), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_stlh

#define INSTR_CREATE_stlh (   dc,
  mem,
  Rm 
)    instr_create_1dst_1src((dc), OP_stlh, (mem), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_stm

#define INSTR_CREATE_stm (   dc,
  mem,
  list_len,
  ... 
)     instr_create_Ndst_Msrc_varsrc((dc), OP_stm, 1, 0, list_len, 0, (mem), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_stm_priv

#define INSTR_CREATE_stm_priv (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_stm_priv, 1, 0, list_len, 0, (mem), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_stm_wb

#define INSTR_CREATE_stm_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_stm, 2, 1, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_stmda

#define INSTR_CREATE_stmda (   dc,
  mem,
  list_len,
  ... 
)     instr_create_Ndst_Msrc_varsrc((dc), OP_stmda, 1, 0, list_len, 0, (mem), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_stmda_priv

#define INSTR_CREATE_stmda_priv (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_stmda_priv, 1, 0, list_len, 0, (mem), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_stmda_wb

#define INSTR_CREATE_stmda_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_stmda, 2, 1, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_stmdb

#define INSTR_CREATE_stmdb (   dc,
  mem,
  list_len,
  ... 
)     instr_create_Ndst_Msrc_varsrc((dc), OP_stmdb, 1, 0, list_len, 0, (mem), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_stmdb_priv

#define INSTR_CREATE_stmdb_priv (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_stmdb_priv, 1, 0, list_len, 0, (mem), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_stmdb_wb

#define INSTR_CREATE_stmdb_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_stmdb, 2, 1, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_stmib

#define INSTR_CREATE_stmib (   dc,
  mem,
  list_len,
  ... 
)     instr_create_Ndst_Msrc_varsrc((dc), OP_stmib, 1, 0, list_len, 0, (mem), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_stmib_priv

#define INSTR_CREATE_stmib_priv (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_stmib_priv, 1, 0, list_len, 0, (mem), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_stmib_wb

#define INSTR_CREATE_stmib_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_stmib, 2, 1, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_str

#define INSTR_CREATE_str (   dc,
  mem,
  Rt 
)    instr_create_1dst_1src((dc), OP_str, (mem), (Rt))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.

◆ INSTR_CREATE_str_wbimm

#define INSTR_CREATE_str_wbimm (   dc,
  mem,
  Rt,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_str, (mem), opnd_create_reg(opnd_get_base(mem)), \
(Rt), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_str_wbreg

#define INSTR_CREATE_str_wbreg (   dc,
  mem,
  Rt,
  Rm,
  shift,
  imm 
)
Value:
instr_create_2dst_5src((dc), OP_str, (mem), opnd_create_reg(opnd_get_base(mem)), \
(Rt), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.
RmThe source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_strb

#define INSTR_CREATE_strb (   dc,
  mem,
  Rt 
)    instr_create_1dst_1src((dc), OP_strb, (mem), (Rt))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.

◆ INSTR_CREATE_strb_wbimm

#define INSTR_CREATE_strb_wbimm (   dc,
  mem,
  Rt,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_strb, (mem), opnd_create_reg(opnd_get_base(mem)), \
(Rt), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_strb_wbreg

#define INSTR_CREATE_strb_wbreg (   dc,
  mem,
  Rt,
  Rm,
  shift,
  imm 
)
Value:
instr_create_2dst_5src((dc), OP_strb, (mem), opnd_create_reg(opnd_get_base(mem)), \
(Rt), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.
RmThe source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_strbt

#define INSTR_CREATE_strbt (   dc,
  mem,
  Rt 
)     instr_create_1dst_1src((dc), OP_strbt, (mem), (Rt))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.

◆ INSTR_CREATE_strbt_wbimm

#define INSTR_CREATE_strbt_wbimm (   dc,
  mem,
  Rt,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_strbt, (mem), opnd_create_reg(opnd_get_base(mem)), \
(Rt), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_strbt_wbreg

#define INSTR_CREATE_strbt_wbreg (   dc,
  mem,
  Rt,
  Rm,
  shift,
  imm 
)
Value:
instr_create_2dst_5src((dc), OP_strbt, (mem), opnd_create_reg(opnd_get_base(mem)), \
(Rt), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.
RmThe source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_strd

#define INSTR_CREATE_strd (   dc,
  mem,
  Rt,
  Rt2 
)     instr_create_1dst_2src((dc), OP_strd, (mem), (Rt), (Rt2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.
Rt2The second source register opnd_t operand.

◆ INSTR_CREATE_strd_wbimm

#define INSTR_CREATE_strd_wbimm (   dc,
  mem,
  Rt,
  Rt2,
  imm 
)
Value:
instr_create_2dst_4src((dc), OP_strd, (mem), opnd_create_reg(opnd_get_base(mem)), \
(Rt), (Rt2), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.
Rt2The second source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_strd_wbreg

#define INSTR_CREATE_strd_wbreg (   dc,
  mem,
  Rt,
  Rt2,
  Rm 
)
Value:
instr_create_2dst_4src((dc), OP_strd, (mem), opnd_create_reg(opnd_get_base(mem)), \
(Rt), (Rt2), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.
Rt2The second source register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_strex

#define INSTR_CREATE_strex (   dc,
  mem,
  Rd,
  Rm 
)     instr_create_2dst_1src((dc), OP_strex, (mem), (Rd), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_strexb

#define INSTR_CREATE_strexb (   dc,
  mem,
  Rd,
  Rm 
)     instr_create_2dst_1src((dc), OP_strexb, (mem), (Rd), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_strexd

#define INSTR_CREATE_strexd (   dc,
  mem,
  Rd,
  Rt,
  Rt2 
)     instr_create_2dst_2src((dc), OP_strexd, (mem), (Rd), (Rt), (Rt2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RdThe destination register opnd_t operand.
RtThe source register opnd_t operand.
Rt2The second source register opnd_t operand.

◆ INSTR_CREATE_strexh

#define INSTR_CREATE_strexh (   dc,
  mem,
  Rd,
  Rm 
)     instr_create_2dst_1src((dc), OP_strexh, (mem), (Rd), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_strh

#define INSTR_CREATE_strh (   dc,
  mem,
  Rt 
)    instr_create_1dst_1src((dc), OP_strh, (mem), (Rt))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.

◆ INSTR_CREATE_strh_wbimm

#define INSTR_CREATE_strh_wbimm (   dc,
  mem,
  Rt,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_strh, (mem), opnd_create_reg(opnd_get_base(mem)), \
(Rt), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_strh_wbreg

#define INSTR_CREATE_strh_wbreg (   dc,
  mem,
  Rt,
  Rm 
)
Value:
instr_create_2dst_3src((dc), OP_strh, (mem), opnd_create_reg(opnd_get_base(mem)), \
(Rt), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_strht

#define INSTR_CREATE_strht (   dc,
  mem,
  Rt 
)     instr_create_1dst_1src((dc), OP_strht, (mem), (Rt))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.

◆ INSTR_CREATE_strht_wbimm

#define INSTR_CREATE_strht_wbimm (   dc,
  mem,
  Rt,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_strht, (mem), opnd_create_reg(opnd_get_base(mem)), \
(Rt), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_strht_wbreg

#define INSTR_CREATE_strht_wbreg (   dc,
  mem,
  Rt,
  Rm 
)
Value:
instr_create_2dst_3src((dc), OP_strht, (mem), opnd_create_reg(opnd_get_base(mem)), \
(Rt), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_strt

#define INSTR_CREATE_strt (   dc,
  mem,
  Rt 
)    instr_create_1dst_1src((dc), OP_strt, (mem), (Rt))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.

◆ INSTR_CREATE_strt_wbimm

#define INSTR_CREATE_strt_wbimm (   dc,
  mem,
  Rt,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_strt, (mem), opnd_create_reg(opnd_get_base(mem)), \
(Rt), (imm), opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_strt_wbreg

#define INSTR_CREATE_strt_wbreg (   dc,
  mem,
  Rt,
  Rm,
  shift,
  imm 
)
Value:
instr_create_2dst_5src((dc), OP_strt, (mem), opnd_create_reg(opnd_get_base(mem)), \
(Rt), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RtThe source register opnd_t operand.
RmThe source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_sub

#define INSTR_CREATE_sub (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_sub_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_sub, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_sub_shimm

#define INSTR_CREATE_sub_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_sub, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_sub_shreg

#define INSTR_CREATE_sub_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_sub, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_subs

#define INSTR_CREATE_subs (   dc,
  Rd,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_subs_shimm((dc), (Rd), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_1dst_2src((dc), OP_subs, (Rd), (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_subs_shimm

#define INSTR_CREATE_subs_shimm (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_1dst_4src((dc), OP_subs, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_subs_shreg

#define INSTR_CREATE_subs_shreg (   dc,
  Rd,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_1dst_4src((dc), OP_subs, (Rd), (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_subw

#define INSTR_CREATE_subw (   dc,
  Rd,
  Rn,
  imm 
)     instr_create_1dst_2src((dc), OP_subw, (Rd), (Rn), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_svc

#define INSTR_CREATE_svc (   dc,
  imm 
)    instr_create_0dst_1src((dc), OP_svc, (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_swp

#define INSTR_CREATE_swp (   dc,
  Rd,
  mem,
  Rm 
)     instr_create_2dst_2src((dc), OP_swp, (mem), (Rd), (mem), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_swpb

#define INSTR_CREATE_swpb (   dc,
  Rd,
  mem,
  Rm 
)     instr_create_2dst_2src((dc), OP_swpb, (mem), (Rd), (mem), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_sxtab

#define INSTR_CREATE_sxtab (   dc,
  Rd,
  Rn,
  Rm,
  imm 
)     instr_create_1dst_3src((dc), OP_sxtab, (Rd), (Rn), (Rm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_sxtab16

#define INSTR_CREATE_sxtab16 (   dc,
  Rd,
  Rn,
  Rm,
  imm 
)     instr_create_1dst_3src((dc), OP_sxtab16, (Rd), (Rn), (Rm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_sxtah

#define INSTR_CREATE_sxtah (   dc,
  Rd,
  Rn,
  Rm,
  imm 
)     instr_create_1dst_3src((dc), OP_sxtah, (Rd), (Rn), (Rm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_sxtb

#define INSTR_CREATE_sxtb (   dc,
  Rd,
  Rn 
)    instr_create_1dst_1src((dc), OP_sxtb, (Rd), (Rn))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.

◆ INSTR_CREATE_sxtb16

#define INSTR_CREATE_sxtb16 (   dc,
  Rd,
  Rm,
  imm 
)     instr_create_1dst_2src((dc), OP_sxtb16, (Rd), (Rm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_sxtb_imm

#define INSTR_CREATE_sxtb_imm (   dc,
  Rd,
  Rm,
  imm 
)     instr_create_1dst_2src((dc), OP_sxtb, (Rd), (Rm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_sxth

#define INSTR_CREATE_sxth (   dc,
  Rd,
  Rn 
)    instr_create_1dst_1src((dc), OP_sxth, (Rd), (Rn))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.

◆ INSTR_CREATE_sxth_imm

#define INSTR_CREATE_sxth_imm (   dc,
  Rd,
  Rm,
  imm 
)     instr_create_1dst_2src((dc), OP_sxth, (Rd), (Rm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_tbb

#define INSTR_CREATE_tbb (   dc,
  mem 
)    instr_create_0dst_1src((dc), OP_tbb, (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.

◆ INSTR_CREATE_tbh

#define INSTR_CREATE_tbh (   dc,
  mem 
)    instr_create_0dst_1src((dc), OP_tbh, (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.

◆ INSTR_CREATE_teq

#define INSTR_CREATE_teq (   dc,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_teq_shimm((dc), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_0dst_2src((dc), OP_teq, (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_teq_shimm

#define INSTR_CREATE_teq_shimm (   dc,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_0dst_4src((dc), OP_teq, (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_teq_shreg

#define INSTR_CREATE_teq_shreg (   dc,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_0dst_4src((dc), OP_teq, (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_tst

#define INSTR_CREATE_tst (   dc,
  Rn,
  Rm_or_imm 
)
Value:
(opnd_is_reg(Rm_or_imm) \
? INSTR_CREATE_tst_shimm((dc), (Rn), (Rm_or_imm), \
OPND_CREATE_INT8(DR_SHIFT_NONE), OPND_CREATE_INT8(0)) \
: instr_create_0dst_2src((dc), OP_tst, (Rn), (Rm_or_imm)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe source register opnd_t operand.
Rm_or_immThe second source register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_tst_shimm

#define INSTR_CREATE_tst_shimm (   dc,
  Rn,
  Rm,
  shift,
  imm 
)
Value:
instr_create_0dst_4src((dc), OP_tst, (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_tst_shreg

#define INSTR_CREATE_tst_shreg (   dc,
  Rn,
  Rm,
  shift,
  Rs 
)
Value:
instr_create_0dst_4src((dc), OP_tst, (Rn), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (Rs))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
RsThe third source register opnd_t operand.

◆ INSTR_CREATE_uadd16

#define INSTR_CREATE_uadd16 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_uadd16, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_uadd8

#define INSTR_CREATE_uadd8 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_uadd8, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_uasx

#define INSTR_CREATE_uasx (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_uasx, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_ubfx

#define INSTR_CREATE_ubfx (   dc,
  Rd,
  Rm,
  imm,
  imm2 
)     instr_create_1dst_3src((dc), OP_ubfx, (Rd), (Rm), (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_udf

#define INSTR_CREATE_udf (   dc,
  imm 
)    instr_create_0dst_1src((dc), OP_udf, (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_udiv

#define INSTR_CREATE_udiv (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_udiv, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_uhadd16

#define INSTR_CREATE_uhadd16 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_uhadd16, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_uhadd8

#define INSTR_CREATE_uhadd8 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_uhadd8, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_uhasx

#define INSTR_CREATE_uhasx (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_uhasx, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_uhsax

#define INSTR_CREATE_uhsax (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_uhsax, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_uhsub16

#define INSTR_CREATE_uhsub16 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_uhsub16, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_uhsub8

#define INSTR_CREATE_uhsub8 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_uhsub8, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_umaal

#define INSTR_CREATE_umaal (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_4src((dc), OP_umaal, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_umlal

#define INSTR_CREATE_umlal (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_4src((dc), OP_umlal, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_umlals

#define INSTR_CREATE_umlals (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_4src((dc), OP_umlals, (Rd), (Rd2), (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_umull

#define INSTR_CREATE_umull (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_2src((dc), OP_umull, (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_umulls

#define INSTR_CREATE_umulls (   dc,
  Rd,
  Rd2,
  Rn,
  Rm 
)     instr_create_2dst_2src((dc), OP_umulls, (Rd), (Rd2), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_uqadd16

#define INSTR_CREATE_uqadd16 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_uqadd16, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_uqadd8

#define INSTR_CREATE_uqadd8 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_uqadd8, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_uqasx

#define INSTR_CREATE_uqasx (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_uqasx, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_uqsax

#define INSTR_CREATE_uqsax (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_uqsax, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_uqsub16

#define INSTR_CREATE_uqsub16 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_uqsub16, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_uqsub8

#define INSTR_CREATE_uqsub8 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_uqsub8, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_usad8

#define INSTR_CREATE_usad8 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_usad8, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_usada8

#define INSTR_CREATE_usada8 (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)     instr_create_1dst_3src((dc), OP_usada8, (Rd), (Rn), (Rm), (Ra))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
RaThe third source register opnd_t operand.

◆ INSTR_CREATE_usat16

#define INSTR_CREATE_usat16 (   dc,
  Rd,
  imm,
  Rm 
)     instr_create_1dst_2src((dc), OP_usat16, (Rd), (imm), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_usat_shimm

#define INSTR_CREATE_usat_shimm (   dc,
  Rd,
  imm,
  Rm,
  shift,
  imm2 
)
Value:
instr_create_1dst_4src((dc), OP_usat, (Rd), (imm), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_add_flags((shift), DR_OPND_IS_SHIFT), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
shiftThe dr_shift_type_t integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_usax

#define INSTR_CREATE_usax (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_usax, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_usub16

#define INSTR_CREATE_usub16 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_usub16, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_usub8

#define INSTR_CREATE_usub8 (   dc,
  Rd,
  Rn,
  Rm 
)     instr_create_1dst_2src((dc), OP_usub8, (Rd), (Rn), (Rm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.

◆ INSTR_CREATE_uxtab

#define INSTR_CREATE_uxtab (   dc,
  Rd,
  Rn,
  Rm,
  imm 
)     instr_create_1dst_3src((dc), OP_uxtab, (Rd), (Rn), (Rm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_uxtab16

#define INSTR_CREATE_uxtab16 (   dc,
  Rd,
  Rn,
  Rm,
  imm 
)     instr_create_1dst_3src((dc), OP_uxtab16, (Rd), (Rn), (Rm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_uxtah

#define INSTR_CREATE_uxtah (   dc,
  Rd,
  Rn,
  Rm,
  imm 
)     instr_create_1dst_3src((dc), OP_uxtah, (Rd), (Rn), (Rm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.
RmThe second source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_uxtb

#define INSTR_CREATE_uxtb (   dc,
  Rd,
  Rn 
)    instr_create_1dst_1src((dc), OP_uxtb, (Rd), (Rn))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.

◆ INSTR_CREATE_uxtb16

#define INSTR_CREATE_uxtb16 (   dc,
  Rd,
  Rm,
  imm 
)     instr_create_1dst_2src((dc), OP_uxtb16, (Rd), (Rm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_uxtb_imm

#define INSTR_CREATE_uxtb_imm (   dc,
  Rd,
  Rm,
  imm 
)     instr_create_1dst_2src((dc), OP_uxtb, (Rd), (Rm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_uxth

#define INSTR_CREATE_uxth (   dc,
  Rd,
  Rn 
)    instr_create_1dst_1src((dc), OP_uxth, (Rd), (Rn))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RnThe source register opnd_t operand.

◆ INSTR_CREATE_uxth_imm

#define INSTR_CREATE_uxth_imm (   dc,
  Rd,
  Rm,
  imm 
)     instr_create_1dst_2src((dc), OP_uxth, (Rd), (Rm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
RmThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vaba_s16

#define INSTR_CREATE_vaba_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaba_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaba_s32

#define INSTR_CREATE_vaba_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaba_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaba_s8

#define INSTR_CREATE_vaba_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaba_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaba_u16

#define INSTR_CREATE_vaba_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaba_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaba_u32

#define INSTR_CREATE_vaba_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaba_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaba_u8

#define INSTR_CREATE_vaba_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaba_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabal_s16

#define INSTR_CREATE_vabal_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabal_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabal_s32

#define INSTR_CREATE_vabal_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabal_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabal_s8

#define INSTR_CREATE_vabal_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabal_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabal_u16

#define INSTR_CREATE_vabal_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabal_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabal_u32

#define INSTR_CREATE_vabal_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabal_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabal_u8

#define INSTR_CREATE_vabal_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabal_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabd_s16

#define INSTR_CREATE_vabd_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabd_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabd_s32

#define INSTR_CREATE_vabd_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabd_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabd_s8

#define INSTR_CREATE_vabd_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabd_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabd_u16

#define INSTR_CREATE_vabd_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabd_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabd_u32

#define INSTR_CREATE_vabd_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabd_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabd_u8

#define INSTR_CREATE_vabd_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabd_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabdl_s16

#define INSTR_CREATE_vabdl_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabdl_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabdl_s32

#define INSTR_CREATE_vabdl_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabdl_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabdl_s8

#define INSTR_CREATE_vabdl_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabdl_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabdl_u16

#define INSTR_CREATE_vabdl_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabdl_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabdl_u32

#define INSTR_CREATE_vabdl_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabdl_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabdl_u8

#define INSTR_CREATE_vabdl_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vabdl_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabs_f32

#define INSTR_CREATE_vabs_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vabs_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabs_f64

#define INSTR_CREATE_vabs_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vabs_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabs_s16

#define INSTR_CREATE_vabs_s16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vabs_s16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabs_s32

#define INSTR_CREATE_vabs_s32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vabs_s32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vabs_s8

#define INSTR_CREATE_vabs_s8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vabs_s8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vacge_f32

#define INSTR_CREATE_vacge_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vacge_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vacgt_f32

#define INSTR_CREATE_vacgt_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vacgt_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vadd_f32

#define INSTR_CREATE_vadd_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vadd_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vadd_f64

#define INSTR_CREATE_vadd_f64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vadd_f64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vadd_i16

#define INSTR_CREATE_vadd_i16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vadd_i16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vadd_i32

#define INSTR_CREATE_vadd_i32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vadd_i32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vadd_i64

#define INSTR_CREATE_vadd_i64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vadd_i64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vadd_i8

#define INSTR_CREATE_vadd_i8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vadd_i8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaddhn_i16

#define INSTR_CREATE_vaddhn_i16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaddhn_i16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaddhn_i32

#define INSTR_CREATE_vaddhn_i32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaddhn_i32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaddhn_i64

#define INSTR_CREATE_vaddhn_i64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaddhn_i64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaddl_s16

#define INSTR_CREATE_vaddl_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaddl_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaddl_s32

#define INSTR_CREATE_vaddl_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaddl_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaddl_s8

#define INSTR_CREATE_vaddl_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaddl_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaddl_u16

#define INSTR_CREATE_vaddl_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaddl_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaddl_u32

#define INSTR_CREATE_vaddl_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaddl_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaddl_u8

#define INSTR_CREATE_vaddl_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaddl_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaddw_s16

#define INSTR_CREATE_vaddw_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaddw_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaddw_s32

#define INSTR_CREATE_vaddw_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaddw_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaddw_s8

#define INSTR_CREATE_vaddw_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaddw_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaddw_u16

#define INSTR_CREATE_vaddw_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaddw_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaddw_u32

#define INSTR_CREATE_vaddw_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaddw_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vaddw_u8

#define INSTR_CREATE_vaddw_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vaddw_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vand

#define INSTR_CREATE_vand (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vand, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vbic

#define INSTR_CREATE_vbic (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vbic, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vbic_i16

#define INSTR_CREATE_vbic_i16 (   dc,
  Vd,
  imm 
)     instr_create_1dst_1src((dc), OP_vbic_i16, (Vd), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vbic_i32

#define INSTR_CREATE_vbic_i32 (   dc,
  Vd,
  imm 
)     instr_create_1dst_1src((dc), OP_vbic_i32, (Vd), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vbif

#define INSTR_CREATE_vbif (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vbif, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vbit

#define INSTR_CREATE_vbit (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vbit, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vbsl

#define INSTR_CREATE_vbsl (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vbsl, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vceq_f32

#define INSTR_CREATE_vceq_f32 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vceq_f32, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vceq_i16

#define INSTR_CREATE_vceq_i16 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vceq_i16, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vceq_i32

#define INSTR_CREATE_vceq_i32 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vceq_i32, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vceq_i8

#define INSTR_CREATE_vceq_i8 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vceq_i8, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vcge_f32

#define INSTR_CREATE_vcge_f32 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vcge_f32, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vcge_s16

#define INSTR_CREATE_vcge_s16 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vcge_s16, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vcge_s32

#define INSTR_CREATE_vcge_s32 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vcge_s32, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vcge_s8

#define INSTR_CREATE_vcge_s8 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vcge_s8, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vcge_u16

#define INSTR_CREATE_vcge_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vcge_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcge_u32

#define INSTR_CREATE_vcge_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vcge_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcge_u8

#define INSTR_CREATE_vcge_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vcge_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcgt_f32

#define INSTR_CREATE_vcgt_f32 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vcgt_f32, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vcgt_s16

#define INSTR_CREATE_vcgt_s16 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vcgt_s16, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vcgt_s32

#define INSTR_CREATE_vcgt_s32 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vcgt_s32, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vcgt_s8

#define INSTR_CREATE_vcgt_s8 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vcgt_s8, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vcgt_u16

#define INSTR_CREATE_vcgt_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vcgt_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcgt_u32

#define INSTR_CREATE_vcgt_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vcgt_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcgt_u8

#define INSTR_CREATE_vcgt_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vcgt_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcle_f32

#define INSTR_CREATE_vcle_f32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcle_f32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcle_s16

#define INSTR_CREATE_vcle_s16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcle_s16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcle_s32

#define INSTR_CREATE_vcle_s32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcle_s32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcle_s8

#define INSTR_CREATE_vcle_s8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcle_s8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcls_s16

#define INSTR_CREATE_vcls_s16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcls_s16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcls_s32

#define INSTR_CREATE_vcls_s32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcls_s32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcls_s8

#define INSTR_CREATE_vcls_s8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcls_s8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vclt_f32

#define INSTR_CREATE_vclt_f32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vclt_f32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vclt_s16

#define INSTR_CREATE_vclt_s16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vclt_s16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vclt_s32

#define INSTR_CREATE_vclt_s32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vclt_s32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vclt_s8

#define INSTR_CREATE_vclt_s8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vclt_s8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vclz_i16

#define INSTR_CREATE_vclz_i16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vclz_i16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vclz_i32

#define INSTR_CREATE_vclz_i32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vclz_i32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vclz_i8

#define INSTR_CREATE_vclz_i8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vclz_i8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcmp_f32

#define INSTR_CREATE_vcmp_f32 (   dc,
  Vt,
  Vm_or_imm 
)
Value:
instr_create_1dst_2src((dc), OP_vcmp_f32, opnd_create_reg(DR_REG_FPSCR), (Vt), \
(Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VtThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vcmp_f64

#define INSTR_CREATE_vcmp_f64 (   dc,
  Vt,
  Vm_or_imm 
)
Value:
instr_create_1dst_2src((dc), OP_vcmp_f64, opnd_create_reg(DR_REG_FPSCR), (Vt), \
(Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VtThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vcmpe_f32

#define INSTR_CREATE_vcmpe_f32 (   dc,
  Vt,
  Vm_or_imm 
)
Value:
instr_create_1dst_2src((dc), OP_vcmpe_f32, opnd_create_reg(DR_REG_FPSCR), (Vt), \
(Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VtThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vcmpe_f64

#define INSTR_CREATE_vcmpe_f64 (   dc,
  Vt,
  Vm_or_imm 
)
Value:
instr_create_1dst_2src((dc), OP_vcmpe_f64, opnd_create_reg(DR_REG_FPSCR), (Vt), \
(Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VtThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vcnt_8

#define INSTR_CREATE_vcnt_8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcnt_8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvt_f16_f32

#define INSTR_CREATE_vcvt_f16_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvt_f16_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvt_f32_f16

#define INSTR_CREATE_vcvt_f32_f16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvt_f32_f16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvt_f32_f64

#define INSTR_CREATE_vcvt_f32_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvt_f32_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvt_f32_s16

#define INSTR_CREATE_vcvt_f32_s16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_f32_s16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvt_f32_s32

#define INSTR_CREATE_vcvt_f32_s32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvt_f32_s32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvt_f32_s32_imm

#define INSTR_CREATE_vcvt_f32_s32_imm (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_f32_s32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvt_f32_u16

#define INSTR_CREATE_vcvt_f32_u16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_f32_u16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvt_f32_u32

#define INSTR_CREATE_vcvt_f32_u32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvt_f32_u32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvt_f32_u32_imm

#define INSTR_CREATE_vcvt_f32_u32_imm (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_f32_u32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvt_f64_f32

#define INSTR_CREATE_vcvt_f64_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvt_f64_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvt_f64_s16

#define INSTR_CREATE_vcvt_f64_s16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_f64_s16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvt_f64_s32

#define INSTR_CREATE_vcvt_f64_s32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvt_f64_s32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvt_f64_s32_imm

#define INSTR_CREATE_vcvt_f64_s32_imm (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_f64_s32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvt_f64_u16

#define INSTR_CREATE_vcvt_f64_u16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_f64_u16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvt_f64_u32

#define INSTR_CREATE_vcvt_f64_u32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvt_f64_u32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvt_f64_u32_imm

#define INSTR_CREATE_vcvt_f64_u32_imm (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_f64_u32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvt_s16_f32

#define INSTR_CREATE_vcvt_s16_f32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_s16_f32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvt_s16_f64

#define INSTR_CREATE_vcvt_s16_f64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_s16_f64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvt_s32_f32

#define INSTR_CREATE_vcvt_s32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvt_s32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvt_s32_f32_imm

#define INSTR_CREATE_vcvt_s32_f32_imm (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_s32_f32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvt_s32_f64

#define INSTR_CREATE_vcvt_s32_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvt_s32_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvt_s32_f64_imm

#define INSTR_CREATE_vcvt_s32_f64_imm (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_s32_f64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvt_u16_f32

#define INSTR_CREATE_vcvt_u16_f32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_u16_f32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvt_u16_f64

#define INSTR_CREATE_vcvt_u16_f64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_u16_f64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvt_u32_f32

#define INSTR_CREATE_vcvt_u32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvt_u32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvt_u32_f32_imm

#define INSTR_CREATE_vcvt_u32_f32_imm (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_u32_f32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvt_u32_f64

#define INSTR_CREATE_vcvt_u32_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvt_u32_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvt_u32_f64_imm

#define INSTR_CREATE_vcvt_u32_f64_imm (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vcvt_u32_f64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vcvta_s32_f32

#define INSTR_CREATE_vcvta_s32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvta_s32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvta_s32_f64

#define INSTR_CREATE_vcvta_s32_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvta_s32_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvta_u32_f32

#define INSTR_CREATE_vcvta_u32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvta_u32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvta_u32_f64

#define INSTR_CREATE_vcvta_u32_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvta_u32_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtb_f16_f32

#define INSTR_CREATE_vcvtb_f16_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtb_f16_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtb_f16_f64

#define INSTR_CREATE_vcvtb_f16_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtb_f16_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtb_f32_f16

#define INSTR_CREATE_vcvtb_f32_f16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtb_f32_f16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtb_f64_f16

#define INSTR_CREATE_vcvtb_f64_f16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtb_f64_f16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtm_s32_f32

#define INSTR_CREATE_vcvtm_s32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtm_s32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtm_s32_f64

#define INSTR_CREATE_vcvtm_s32_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtm_s32_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtm_u32_f32

#define INSTR_CREATE_vcvtm_u32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtm_u32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtm_u32_f64

#define INSTR_CREATE_vcvtm_u32_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtm_u32_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtn_s32_f32

#define INSTR_CREATE_vcvtn_s32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtn_s32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtn_s32_f64

#define INSTR_CREATE_vcvtn_s32_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtn_s32_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtn_u32_f32

#define INSTR_CREATE_vcvtn_u32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtn_u32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtn_u32_f64

#define INSTR_CREATE_vcvtn_u32_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtn_u32_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtp_s32_f32

#define INSTR_CREATE_vcvtp_s32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtp_s32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtp_s32_f64

#define INSTR_CREATE_vcvtp_s32_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtp_s32_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtp_u32_f32

#define INSTR_CREATE_vcvtp_u32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtp_u32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtp_u32_f64

#define INSTR_CREATE_vcvtp_u32_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtp_u32_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtr_s32_f32

#define INSTR_CREATE_vcvtr_s32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtr_s32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtr_s32_f64

#define INSTR_CREATE_vcvtr_s32_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtr_s32_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtr_u32_f32

#define INSTR_CREATE_vcvtr_u32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtr_u32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtr_u32_f64

#define INSTR_CREATE_vcvtr_u32_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtr_u32_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtt_f16_f32

#define INSTR_CREATE_vcvtt_f16_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtt_f16_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtt_f16_f64

#define INSTR_CREATE_vcvtt_f16_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtt_f16_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtt_f32_f16

#define INSTR_CREATE_vcvtt_f32_f16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtt_f32_f16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vcvtt_f64_f16

#define INSTR_CREATE_vcvtt_f64_f16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vcvtt_f64_f16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vdiv_f32

#define INSTR_CREATE_vdiv_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vdiv_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vdiv_f64

#define INSTR_CREATE_vdiv_f64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vdiv_f64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vdup_16

#define INSTR_CREATE_vdup_16 (   dc,
  Vd,
  Rt 
)     instr_create_1dst_1src((dc), OP_vdup_16, (Vd), (Rt))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
RtThe source register opnd_t operand.

◆ INSTR_CREATE_vdup_16_imm

#define INSTR_CREATE_vdup_16_imm (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vdup_16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vdup_32

#define INSTR_CREATE_vdup_32 (   dc,
  Vd,
  Rt 
)     instr_create_1dst_1src((dc), OP_vdup_32, (Vd), (Rt))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
RtThe source register opnd_t operand.

◆ INSTR_CREATE_vdup_32_imm

#define INSTR_CREATE_vdup_32_imm (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vdup_32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vdup_8

#define INSTR_CREATE_vdup_8 (   dc,
  Vd,
  Rt 
)     instr_create_1dst_1src((dc), OP_vdup_8, (Vd), (Rt))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
RtThe source register opnd_t operand.

◆ INSTR_CREATE_vdup_8_imm

#define INSTR_CREATE_vdup_8_imm (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vdup_8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_veor

#define INSTR_CREATE_veor (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_veor, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vext

#define INSTR_CREATE_vext (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vext, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vfma_f32

#define INSTR_CREATE_vfma_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vfma_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vfma_f64

#define INSTR_CREATE_vfma_f64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vfma_f64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vfms_f32

#define INSTR_CREATE_vfms_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vfms_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vfms_f64

#define INSTR_CREATE_vfms_f64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vfms_f64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vfnma_f32

#define INSTR_CREATE_vfnma_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vfnma_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vfnma_f64

#define INSTR_CREATE_vfnma_f64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vfnma_f64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vfnms_f32

#define INSTR_CREATE_vfnms_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vfnms_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vfnms_f64

#define INSTR_CREATE_vfnms_f64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vfnms_f64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vhadd_s16

#define INSTR_CREATE_vhadd_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vhadd_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vhadd_s32

#define INSTR_CREATE_vhadd_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vhadd_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vhadd_s8

#define INSTR_CREATE_vhadd_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vhadd_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vhadd_u16

#define INSTR_CREATE_vhadd_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vhadd_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vhadd_u32

#define INSTR_CREATE_vhadd_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vhadd_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vhadd_u8

#define INSTR_CREATE_vhadd_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vhadd_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vhsub_s16

#define INSTR_CREATE_vhsub_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vhsub_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vhsub_s32

#define INSTR_CREATE_vhsub_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vhsub_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vhsub_s8

#define INSTR_CREATE_vhsub_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vhsub_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vhsub_u16

#define INSTR_CREATE_vhsub_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vhsub_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vhsub_u32

#define INSTR_CREATE_vhsub_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vhsub_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vhsub_u8

#define INSTR_CREATE_vhsub_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vhsub_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vld1_16

#define INSTR_CREATE_vld1_16 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld1_16, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_16_wbimm

#define INSTR_CREATE_vld1_16_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld1_16, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_16_wbreg

#define INSTR_CREATE_vld1_16_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld1_16, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), (mem), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_32

#define INSTR_CREATE_vld1_32 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld1_32, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_32_wbimm

#define INSTR_CREATE_vld1_32_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld1_32, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_32_wbreg

#define INSTR_CREATE_vld1_32_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld1_32, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), (mem), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_64

#define INSTR_CREATE_vld1_64 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld1_64, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_64_wbimm

#define INSTR_CREATE_vld1_64_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld1_64, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_64_wbreg

#define INSTR_CREATE_vld1_64_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld1_64, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), (mem), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_8

#define INSTR_CREATE_vld1_8 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld1_8, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_8_wbimm

#define INSTR_CREATE_vld1_8_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld1_8, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_8_wbreg

#define INSTR_CREATE_vld1_8_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld1_8, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), (mem), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_dup_16

#define INSTR_CREATE_vld1_dup_16 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld1_dup_16, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_dup_16_wbimm

#define INSTR_CREATE_vld1_dup_16_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld1_dup_16, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_dup_16_wbreg

#define INSTR_CREATE_vld1_dup_16_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld1_dup_16, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_dup_32

#define INSTR_CREATE_vld1_dup_32 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld1_dup_32, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_dup_32_wbimm

#define INSTR_CREATE_vld1_dup_32_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld1_dup_32, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_dup_32_wbreg

#define INSTR_CREATE_vld1_dup_32_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld1_dup_32, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_dup_8

#define INSTR_CREATE_vld1_dup_8 (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld1_dup_8, 0, 1, list_len, 0, (mem), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_dup_8_wb

#define INSTR_CREATE_vld1_dup_8_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld1_dup_8, 1, 2, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_dup_8_wbreg

#define INSTR_CREATE_vld1_dup_8_wbreg (   dc,
  mem,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld1_dup_8, 1, 3, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld1_lane_16

#define INSTR_CREATE_vld1_lane_16 (   dc,
  Vd,
  mem,
  imm,
  imm2 
)     instr_create_1dst_3src((dc), OP_vld1_lane_16, (Vd), (mem), (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_vld1_lane_16_wbimm

#define INSTR_CREATE_vld1_lane_16_wbimm (   dc,
  Vd,
  mem,
  imm,
  imm2 
)
Value:
instr_create_2dst_4src((dc), OP_vld1_lane_16, (Vd), \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (imm2), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_vld1_lane_16_wbreg

#define INSTR_CREATE_vld1_lane_16_wbreg (   dc,
  Vd,
  mem,
  imm,
  imm2,
  Rm 
)
Value:
instr_create_2dst_5src((dc), OP_vld1_lane_16, (Vd), \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (imm2), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_vld1_lane_32

#define INSTR_CREATE_vld1_lane_32 (   dc,
  Vd,
  mem,
  imm,
  imm2 
)     instr_create_1dst_3src((dc), OP_vld1_lane_32, (Vd), (mem), (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_vld1_lane_32_wbimm

#define INSTR_CREATE_vld1_lane_32_wbimm (   dc,
  Vd,
  mem,
  imm,
  imm2 
)
Value:
instr_create_2dst_4src((dc), OP_vld1_lane_32, (Vd), \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (imm2), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_vld1_lane_32_wbreg

#define INSTR_CREATE_vld1_lane_32_wbreg (   dc,
  Vd,
  mem,
  imm,
  imm2,
  Rm 
)
Value:
instr_create_2dst_5src((dc), OP_vld1_lane_32, (Vd), \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), (imm2), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_vld1_lane_8

#define INSTR_CREATE_vld1_lane_8 (   dc,
  Vd,
  mem,
  imm 
)     instr_create_1dst_2src((dc), OP_vld1_lane_8, (Vd), (mem), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vld1_lane_8_wbimm

#define INSTR_CREATE_vld1_lane_8_wbimm (   dc,
  Vd,
  mem,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_vld1_lane_8, (Vd), \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vld1_lane_8_wbreg

#define INSTR_CREATE_vld1_lane_8_wbreg (   dc,
  Vd,
  mem,
  imm,
  Rm 
)
Value:
instr_create_2dst_4src((dc), OP_vld1_lane_8, (Vd), \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_vld2_16

#define INSTR_CREATE_vld2_16 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_16, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_16_wbimm

#define INSTR_CREATE_vld2_16_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_16, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_16_wbreg

#define INSTR_CREATE_vld2_16_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld2_16, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), (mem), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_32

#define INSTR_CREATE_vld2_32 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_32, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_32_wbimm

#define INSTR_CREATE_vld2_32_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_32, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_32_wbreg

#define INSTR_CREATE_vld2_32_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld2_32, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), (mem), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_8

#define INSTR_CREATE_vld2_8 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_8, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_8_wbimm

#define INSTR_CREATE_vld2_8_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_8, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_8_wbreg

#define INSTR_CREATE_vld2_8_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld2_8, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), (mem), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_dup_16

#define INSTR_CREATE_vld2_dup_16 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_dup_16, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_dup_16_wbimm

#define INSTR_CREATE_vld2_dup_16_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_dup_16, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_dup_16_wbreg

#define INSTR_CREATE_vld2_dup_16_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld2_dup_16, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_dup_32

#define INSTR_CREATE_vld2_dup_32 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_dup_32, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_dup_32_wbimm

#define INSTR_CREATE_vld2_dup_32_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_dup_32, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_dup_32_wbreg

#define INSTR_CREATE_vld2_dup_32_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld2_dup_32, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_dup_8

#define INSTR_CREATE_vld2_dup_8 (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_dup_8, 0, 1, list_len, 0, (mem), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_dup_8_wb

#define INSTR_CREATE_vld2_dup_8_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_dup_8, 1, 2, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_dup_8_wbreg

#define INSTR_CREATE_vld2_dup_8_wbreg (   dc,
  mem,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld2_dup_8, 1, 3, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_lane_16

#define INSTR_CREATE_vld2_lane_16 (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_lane_16, 0, 3, list_len, 0, (mem), \
(imm), (imm2), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_lane_16_wbimm

#define INSTR_CREATE_vld2_lane_16_wbimm (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld2_lane_16, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_lane_16_wbreg

#define INSTR_CREATE_vld2_lane_16_wbreg (   dc,
  mem,
  imm,
  imm2,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld2_lane_16, 1, 5, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_lane_32

#define INSTR_CREATE_vld2_lane_32 (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_lane_32, 0, 3, list_len, 0, (mem), \
(imm), (imm2), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_lane_32_wbimm

#define INSTR_CREATE_vld2_lane_32_wbimm (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld2_lane_32, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_lane_32_wbreg

#define INSTR_CREATE_vld2_lane_32_wbreg (   dc,
  mem,
  imm,
  imm2,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld2_lane_32, 1, 5, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_lane_8

#define INSTR_CREATE_vld2_lane_8 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_lane_8, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_lane_8_wbimm

#define INSTR_CREATE_vld2_lane_8_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld2_lane_8, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld2_lane_8_wbreg

#define INSTR_CREATE_vld2_lane_8_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld2_lane_8, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_16

#define INSTR_CREATE_vld3_16 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_16, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_16_wbimm

#define INSTR_CREATE_vld3_16_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_16, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_16_wbreg

#define INSTR_CREATE_vld3_16_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld3_16, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), (mem), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_32

#define INSTR_CREATE_vld3_32 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_32, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_32_wbimm

#define INSTR_CREATE_vld3_32_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_32, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_32_wbreg

#define INSTR_CREATE_vld3_32_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld3_32, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), (mem), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_8

#define INSTR_CREATE_vld3_8 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_8, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_8_wbimm

#define INSTR_CREATE_vld3_8_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_8, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_8_wbreg

#define INSTR_CREATE_vld3_8_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld3_8, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), (mem), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_dup_16

#define INSTR_CREATE_vld3_dup_16 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_dup_16, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_dup_16_wbimm

#define INSTR_CREATE_vld3_dup_16_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_dup_16, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_dup_16_wbreg

#define INSTR_CREATE_vld3_dup_16_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld3_dup_16, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_dup_32

#define INSTR_CREATE_vld3_dup_32 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_dup_32, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_dup_32_wbimm

#define INSTR_CREATE_vld3_dup_32_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_dup_32, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_dup_32_wbreg

#define INSTR_CREATE_vld3_dup_32_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld3_dup_32, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_dup_8

#define INSTR_CREATE_vld3_dup_8 (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_dup_8, 0, 1, list_len, 0, (mem), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_dup_8_wb

#define INSTR_CREATE_vld3_dup_8_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_dup_8, 1, 2, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_dup_8_wbreg

#define INSTR_CREATE_vld3_dup_8_wbreg (   dc,
  mem,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld3_dup_8, 1, 3, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_lane_16

#define INSTR_CREATE_vld3_lane_16 (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_lane_16, 0, 3, list_len, 0, (mem), \
(imm), (imm2), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_lane_16_wbimm

#define INSTR_CREATE_vld3_lane_16_wbimm (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld3_lane_16, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_lane_16_wbreg

#define INSTR_CREATE_vld3_lane_16_wbreg (   dc,
  mem,
  imm,
  imm2,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld3_lane_16, 1, 5, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_lane_32

#define INSTR_CREATE_vld3_lane_32 (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_lane_32, 0, 3, list_len, 0, (mem), \
(imm), (imm2), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_lane_32_wbimm

#define INSTR_CREATE_vld3_lane_32_wbimm (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld3_lane_32, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_lane_32_wbreg

#define INSTR_CREATE_vld3_lane_32_wbreg (   dc,
  mem,
  imm,
  imm2,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld3_lane_32, 1, 5, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_lane_8

#define INSTR_CREATE_vld3_lane_8 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_lane_8, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_lane_8_wbimm

#define INSTR_CREATE_vld3_lane_8_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld3_lane_8, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld3_lane_8_wbreg

#define INSTR_CREATE_vld3_lane_8_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld3_lane_8, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_16

#define INSTR_CREATE_vld4_16 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_16, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_16_wbimm

#define INSTR_CREATE_vld4_16_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_16, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_16_wbreg

#define INSTR_CREATE_vld4_16_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld4_16, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), (mem), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_32

#define INSTR_CREATE_vld4_32 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_32, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_32_wbimm

#define INSTR_CREATE_vld4_32_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_32, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_32_wbreg

#define INSTR_CREATE_vld4_32_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld4_32, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), (mem), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_8

#define INSTR_CREATE_vld4_8 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_8, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_8_wbimm

#define INSTR_CREATE_vld4_8_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_8, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_8_wbreg

#define INSTR_CREATE_vld4_8_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld4_8, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), (mem), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_dup_16

#define INSTR_CREATE_vld4_dup_16 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_dup_16, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_dup_16_wbimm

#define INSTR_CREATE_vld4_dup_16_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_dup_16, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_dup_16_wbreg

#define INSTR_CREATE_vld4_dup_16_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld4_dup_16, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_dup_32

#define INSTR_CREATE_vld4_dup_32 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_dup_32, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_dup_32_wbimm

#define INSTR_CREATE_vld4_dup_32_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_dup_32, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_dup_32_wbreg

#define INSTR_CREATE_vld4_dup_32_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld4_dup_32, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_dup_8

#define INSTR_CREATE_vld4_dup_8 (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_dup_8, 0, 1, list_len, 0, (mem), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_dup_8_wb

#define INSTR_CREATE_vld4_dup_8_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_dup_8, 1, 2, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_dup_8_wbreg

#define INSTR_CREATE_vld4_dup_8_wbreg (   dc,
  mem,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld4_dup_8, 1, 3, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_lane_16

#define INSTR_CREATE_vld4_lane_16 (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_lane_16, 0, 3, list_len, 0, (mem), \
(imm), (imm2), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_lane_16_wbimm

#define INSTR_CREATE_vld4_lane_16_wbimm (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld4_lane_16, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_lane_16_wbreg

#define INSTR_CREATE_vld4_lane_16_wbreg (   dc,
  mem,
  imm,
  imm2,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld4_lane_16, 1, 5, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_lane_32

#define INSTR_CREATE_vld4_lane_32 (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_lane_32, 0, 3, list_len, 0, (mem), \
(imm), (imm2), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_lane_32_wbimm

#define INSTR_CREATE_vld4_lane_32_wbimm (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld4_lane_32, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_lane_32_wbreg

#define INSTR_CREATE_vld4_lane_32_wbreg (   dc,
  mem,
  imm,
  imm2,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld4_lane_32, 1, 5, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), (imm2), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_lane_8

#define INSTR_CREATE_vld4_lane_8 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_lane_8, 0, 2, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_lane_8_wbimm

#define INSTR_CREATE_vld4_lane_8_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vld4_lane_8, 1, 3, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vld4_lane_8_wbreg

#define INSTR_CREATE_vld4_lane_8_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst( \
(dc), OP_vld4_lane_8, 1, 4, list_len, 0, opnd_create_reg(opnd_get_base(mem)), \
(mem), (imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vldm

#define INSTR_CREATE_vldm (   dc,
  mem,
  list_len,
  ... 
)     instr_create_Ndst_Msrc_vardst((dc), OP_vldm, 0, 1, list_len, 0, (mem), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vldm_wb

#define INSTR_CREATE_vldm_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vldm, 1, 2, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vldmdb

#define INSTR_CREATE_vldmdb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_vardst((dc), OP_vldmdb, 1, 2, list_len, 0, \
opnd_create_reg(opnd_get_base(mem)), (mem), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vldr

#define INSTR_CREATE_vldr (   dc,
  Vd,
  mem 
)    instr_create_1dst_1src((dc), OP_vldr, (Vd), (mem))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
memThe memory opnd_t operand.

◆ INSTR_CREATE_vmax_f32

#define INSTR_CREATE_vmax_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmax_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmax_s16

#define INSTR_CREATE_vmax_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmax_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmax_s32

#define INSTR_CREATE_vmax_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmax_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmax_s8

#define INSTR_CREATE_vmax_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmax_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmax_u16

#define INSTR_CREATE_vmax_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmax_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmax_u32

#define INSTR_CREATE_vmax_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmax_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmax_u8

#define INSTR_CREATE_vmax_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmax_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmaxnm_f32

#define INSTR_CREATE_vmaxnm_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmaxnm_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmaxnm_f64

#define INSTR_CREATE_vmaxnm_f64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmaxnm_f64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmin_f32

#define INSTR_CREATE_vmin_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmin_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmin_s16

#define INSTR_CREATE_vmin_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmin_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmin_s32

#define INSTR_CREATE_vmin_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmin_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmin_s8

#define INSTR_CREATE_vmin_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmin_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmin_u16

#define INSTR_CREATE_vmin_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmin_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmin_u32

#define INSTR_CREATE_vmin_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmin_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmin_u8

#define INSTR_CREATE_vmin_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmin_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vminnm_f32

#define INSTR_CREATE_vminnm_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vminnm_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vminnm_f64

#define INSTR_CREATE_vminnm_f64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vminnm_f64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmla_f32

#define INSTR_CREATE_vmla_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmla_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmla_f32_imm

#define INSTR_CREATE_vmla_f32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmla_f32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmla_f64

#define INSTR_CREATE_vmla_f64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmla_f64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmla_i16

#define INSTR_CREATE_vmla_i16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmla_i16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmla_i16_imm

#define INSTR_CREATE_vmla_i16_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmla_i16, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmla_i32

#define INSTR_CREATE_vmla_i32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmla_i32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmla_i32_imm

#define INSTR_CREATE_vmla_i32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmla_i32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmla_i8

#define INSTR_CREATE_vmla_i8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmla_i8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmlal_s16

#define INSTR_CREATE_vmlal_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmlal_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmlal_s16_imm

#define INSTR_CREATE_vmlal_s16_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmlal_s16, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmlal_s32

#define INSTR_CREATE_vmlal_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmlal_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmlal_s32_imm

#define INSTR_CREATE_vmlal_s32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmlal_s32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmlal_s8

#define INSTR_CREATE_vmlal_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmlal_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmlal_u16

#define INSTR_CREATE_vmlal_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmlal_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmlal_u16_imm

#define INSTR_CREATE_vmlal_u16_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmlal_u16, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmlal_u32

#define INSTR_CREATE_vmlal_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmlal_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmlal_u32_imm

#define INSTR_CREATE_vmlal_u32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmlal_u32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmlal_u8

#define INSTR_CREATE_vmlal_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmlal_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmls_f32

#define INSTR_CREATE_vmls_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmls_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmls_f32_imm

#define INSTR_CREATE_vmls_f32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmls_f32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmls_f64

#define INSTR_CREATE_vmls_f64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmls_f64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmls_i16

#define INSTR_CREATE_vmls_i16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmls_i16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmls_i16_imm

#define INSTR_CREATE_vmls_i16_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmls_i16, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmls_i32

#define INSTR_CREATE_vmls_i32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmls_i32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmls_i32_imm

#define INSTR_CREATE_vmls_i32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmls_i32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmls_i8

#define INSTR_CREATE_vmls_i8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmls_i8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmlsl_s16

#define INSTR_CREATE_vmlsl_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmlsl_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmlsl_s16_imm

#define INSTR_CREATE_vmlsl_s16_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmlsl_s16, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmlsl_s32

#define INSTR_CREATE_vmlsl_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmlsl_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmlsl_s32_imm

#define INSTR_CREATE_vmlsl_s32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmlsl_s32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmlsl_s8

#define INSTR_CREATE_vmlsl_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmlsl_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmlsl_u16

#define INSTR_CREATE_vmlsl_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmlsl_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmlsl_u16_imm

#define INSTR_CREATE_vmlsl_u16_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmlsl_u16, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmlsl_u32

#define INSTR_CREATE_vmlsl_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmlsl_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmlsl_u32_imm

#define INSTR_CREATE_vmlsl_u32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmlsl_u32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmlsl_u8

#define INSTR_CREATE_vmlsl_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmlsl_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmov_16

#define INSTR_CREATE_vmov_16 (   dc,
  Vd,
  Rt,
  imm 
)     instr_create_1dst_2src((dc), OP_vmov_16, (Vd), (Rt), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
RtThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmov_32_g2s

#define INSTR_CREATE_vmov_32_g2s (   dc,
  Vd,
  Rt,
  imm 
)     instr_create_1dst_2src((dc), OP_vmov_32, (Vd), (Rt), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
RtThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmov_32_s2g

#define INSTR_CREATE_vmov_32_s2g (   dc,
  Rd,
  Vn,
  imm 
)     instr_create_1dst_2src((dc), OP_vmov_32, (Rd), (Vn), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
VnThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmov_8

#define INSTR_CREATE_vmov_8 (   dc,
  Vd,
  Rt,
  imm 
)     instr_create_1dst_2src((dc), OP_vmov_8, (Vd), (Rt), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
RtThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmov_f32

#define INSTR_CREATE_vmov_f32 (   dc,
  Vd,
  Vm_or_imm 
)     instr_create_1dst_1src((dc), OP_vmov_f32, (Vd), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vmov_f64

#define INSTR_CREATE_vmov_f64 (   dc,
  Vd,
  Vm_or_imm 
)     instr_create_1dst_1src((dc), OP_vmov_f64, (Vd), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vmov_g2s

#define INSTR_CREATE_vmov_g2s (   dc,
  Vd,
  Rt 
)     instr_create_1dst_1src((dc), OP_vmov, (Vd), (Rt))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
RtThe source register opnd_t operand.

◆ INSTR_CREATE_vmov_gg2s

#define INSTR_CREATE_vmov_gg2s (   dc,
  Vd,
  Rt,
  Rt2 
)     instr_create_1dst_2src((dc), OP_vmov, (Vd), (Rt), (Rt2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
RtThe source register opnd_t operand.
Rt2The second source register opnd_t operand.

◆ INSTR_CREATE_vmov_gg2ss

#define INSTR_CREATE_vmov_gg2ss (   dc,
  Vd,
  Vd2,
  Rt,
  Rt2 
)     instr_create_2dst_2src((dc), OP_vmov, (Vd), (Vd2), (Rt), (Rt2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
Vd2The second destination register opnd_t operand.
RtThe source register opnd_t operand.
Rt2The second source register opnd_t operand.

◆ INSTR_CREATE_vmov_i16

#define INSTR_CREATE_vmov_i16 (   dc,
  Vd,
  imm 
)     instr_create_1dst_1src((dc), OP_vmov_i16, (Vd), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmov_i32

#define INSTR_CREATE_vmov_i32 (   dc,
  Vd,
  imm 
)     instr_create_1dst_1src((dc), OP_vmov_i32, (Vd), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmov_i64

#define INSTR_CREATE_vmov_i64 (   dc,
  Vd,
  imm 
)     instr_create_1dst_1src((dc), OP_vmov_i64, (Vd), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmov_i8

#define INSTR_CREATE_vmov_i8 (   dc,
  Vd,
  imm 
)     instr_create_1dst_1src((dc), OP_vmov_i8, (Vd), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmov_s16

#define INSTR_CREATE_vmov_s16 (   dc,
  Rd,
  Vn,
  imm 
)     instr_create_1dst_2src((dc), OP_vmov_s16, (Rd), (Vn), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
VnThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmov_s2g

#define INSTR_CREATE_vmov_s2g (   dc,
  Rd,
  Vn 
)     instr_create_1dst_1src((dc), OP_vmov, (Rd), (Vn))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
VnThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmov_s2gg

#define INSTR_CREATE_vmov_s2gg (   dc,
  Ra,
  Rd,
  Vm 
)     instr_create_2dst_1src((dc), OP_vmov, (Ra), (Rd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RaThe third source register opnd_t operand.
RdThe destination register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmov_s8

#define INSTR_CREATE_vmov_s8 (   dc,
  Rd,
  Vn,
  imm 
)     instr_create_1dst_2src((dc), OP_vmov_s8, (Rd), (Vn), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
VnThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmov_ss2gg

#define INSTR_CREATE_vmov_ss2gg (   dc,
  Rd,
  Rd2,
  Vt,
  Vt2 
)     instr_create_2dst_2src((dc), OP_vmov, (Rd), (Rd2), (Vt), (Vt2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
Rd2The second destination register opnd_t operand.
VtThe source SIMD register opnd_t operand.
Vt2The second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmov_u16

#define INSTR_CREATE_vmov_u16 (   dc,
  Rd,
  Vn,
  imm 
)     instr_create_1dst_2src((dc), OP_vmov_u16, (Rd), (Vn), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
VnThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmov_u8

#define INSTR_CREATE_vmov_u8 (   dc,
  Rd,
  Vn,
  imm 
)     instr_create_1dst_2src((dc), OP_vmov_u8, (Rd), (Vn), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
VnThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmovl_s16

#define INSTR_CREATE_vmovl_s16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vmovl_s16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmovl_s32

#define INSTR_CREATE_vmovl_s32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vmovl_s32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmovl_s8

#define INSTR_CREATE_vmovl_s8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vmovl_s8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmovl_u16

#define INSTR_CREATE_vmovl_u16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vmovl_u16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmovl_u32

#define INSTR_CREATE_vmovl_u32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vmovl_u32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmovl_u8

#define INSTR_CREATE_vmovl_u8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vmovl_u8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmovn_i16

#define INSTR_CREATE_vmovn_i16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vmovn_i16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmovn_i32

#define INSTR_CREATE_vmovn_i32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vmovn_i32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmovn_i64

#define INSTR_CREATE_vmovn_i64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vmovn_i64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmrs

#define INSTR_CREATE_vmrs (   dc,
  Rd 
)     instr_create_1dst_1src((dc), OP_vmrs, (Rd), opnd_create_reg(DR_REG_FPSCR))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.

◆ INSTR_CREATE_vmrs_imm

#define INSTR_CREATE_vmrs_imm (   dc,
  Rd,
  imm 
)     instr_create_1dst_1src((dc), OP_vmrs, (Rd), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmsr

#define INSTR_CREATE_vmsr (   dc,
  Rt 
)     instr_create_1dst_1src((dc), OP_vmsr, opnd_create_reg(DR_REG_FPSCR), (Rt))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RtThe source register opnd_t operand.

◆ INSTR_CREATE_vmsr_imm

#define INSTR_CREATE_vmsr_imm (   dc,
  Rt,
  imm 
)     instr_create_0dst_2src((dc), OP_vmsr, (Rt), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RtThe source register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmul_f32

#define INSTR_CREATE_vmul_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmul_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmul_f32_imm

#define INSTR_CREATE_vmul_f32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmul_f32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmul_f64

#define INSTR_CREATE_vmul_f64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmul_f64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmul_i16

#define INSTR_CREATE_vmul_i16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmul_i16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmul_i16_imm

#define INSTR_CREATE_vmul_i16_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmul_i16, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmul_i32

#define INSTR_CREATE_vmul_i32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmul_i32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmul_i32_imm

#define INSTR_CREATE_vmul_i32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmul_i32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmul_i8

#define INSTR_CREATE_vmul_i8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmul_i8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmul_p32

#define INSTR_CREATE_vmul_p32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmul_p32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmul_p8

#define INSTR_CREATE_vmul_p8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmul_p8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmull_p32

#define INSTR_CREATE_vmull_p32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmull_p32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmull_p8

#define INSTR_CREATE_vmull_p8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmull_p8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmull_s16

#define INSTR_CREATE_vmull_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmull_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmull_s16_imm

#define INSTR_CREATE_vmull_s16_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmull_s16, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmull_s32

#define INSTR_CREATE_vmull_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmull_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmull_s32_imm

#define INSTR_CREATE_vmull_s32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmull_s32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmull_s8

#define INSTR_CREATE_vmull_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmull_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmull_u16

#define INSTR_CREATE_vmull_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmull_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmull_u16_imm

#define INSTR_CREATE_vmull_u16_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmull_u16, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmull_u32

#define INSTR_CREATE_vmull_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmull_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmull_u32_imm

#define INSTR_CREATE_vmull_u32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vmull_u32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmull_u8

#define INSTR_CREATE_vmull_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vmull_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmvn

#define INSTR_CREATE_vmvn (   dc,
  Vd,
  Vm 
)    instr_create_1dst_1src((dc), OP_vmvn, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vmvn_i16

#define INSTR_CREATE_vmvn_i16 (   dc,
  Vd,
  imm 
)     instr_create_1dst_1src((dc), OP_vmvn_i16, (Vd), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vmvn_i32

#define INSTR_CREATE_vmvn_i32 (   dc,
  Vd,
  imm 
)     instr_create_1dst_1src((dc), OP_vmvn_i32, (Vd), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vneg_f32

#define INSTR_CREATE_vneg_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vneg_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vneg_f64

#define INSTR_CREATE_vneg_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vneg_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vneg_s16

#define INSTR_CREATE_vneg_s16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vneg_s16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vneg_s32

#define INSTR_CREATE_vneg_s32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vneg_s32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vneg_s8

#define INSTR_CREATE_vneg_s8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vneg_s8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vnmla_f32

#define INSTR_CREATE_vnmla_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vnmla_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vnmla_f64

#define INSTR_CREATE_vnmla_f64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vnmla_f64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vnmls_f32

#define INSTR_CREATE_vnmls_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vnmls_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vnmls_f64

#define INSTR_CREATE_vnmls_f64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vnmls_f64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vnmul_f32

#define INSTR_CREATE_vnmul_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vnmul_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vnmul_f64

#define INSTR_CREATE_vnmul_f64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vnmul_f64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vorn

#define INSTR_CREATE_vorn (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vorn, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vorr

#define INSTR_CREATE_vorr (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vorr, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vorr_i16

#define INSTR_CREATE_vorr_i16 (   dc,
  Vd,
  imm 
)     instr_create_1dst_1src((dc), OP_vorr_i16, (Vd), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vorr_i32

#define INSTR_CREATE_vorr_i32 (   dc,
  Vd,
  imm 
)     instr_create_1dst_1src((dc), OP_vorr_i32, (Vd), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vpadal_s16

#define INSTR_CREATE_vpadal_s16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vpadal_s16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpadal_s32

#define INSTR_CREATE_vpadal_s32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vpadal_s32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpadal_s8

#define INSTR_CREATE_vpadal_s8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vpadal_s8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpadal_u16

#define INSTR_CREATE_vpadal_u16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vpadal_u16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpadal_u32

#define INSTR_CREATE_vpadal_u32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vpadal_u32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpadal_u8

#define INSTR_CREATE_vpadal_u8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vpadal_u8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpadd_f32

#define INSTR_CREATE_vpadd_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpadd_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpadd_i16

#define INSTR_CREATE_vpadd_i16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpadd_i16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpadd_i32

#define INSTR_CREATE_vpadd_i32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpadd_i32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpadd_i8

#define INSTR_CREATE_vpadd_i8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpadd_i8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpaddl_s16

#define INSTR_CREATE_vpaddl_s16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vpaddl_s16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpaddl_s32

#define INSTR_CREATE_vpaddl_s32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vpaddl_s32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpaddl_s8

#define INSTR_CREATE_vpaddl_s8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vpaddl_s8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpaddl_u16

#define INSTR_CREATE_vpaddl_u16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vpaddl_u16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpaddl_u32

#define INSTR_CREATE_vpaddl_u32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vpaddl_u32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpaddl_u8

#define INSTR_CREATE_vpaddl_u8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vpaddl_u8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpmax_f32

#define INSTR_CREATE_vpmax_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpmax_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpmax_s16

#define INSTR_CREATE_vpmax_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpmax_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpmax_s32

#define INSTR_CREATE_vpmax_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpmax_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpmax_s8

#define INSTR_CREATE_vpmax_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpmax_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpmax_u16

#define INSTR_CREATE_vpmax_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpmax_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpmax_u32

#define INSTR_CREATE_vpmax_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpmax_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpmax_u8

#define INSTR_CREATE_vpmax_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpmax_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpmin_f32

#define INSTR_CREATE_vpmin_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpmin_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpmin_s16

#define INSTR_CREATE_vpmin_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpmin_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpmin_s32

#define INSTR_CREATE_vpmin_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpmin_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpmin_s8

#define INSTR_CREATE_vpmin_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpmin_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpmin_u16

#define INSTR_CREATE_vpmin_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpmin_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpmin_u32

#define INSTR_CREATE_vpmin_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpmin_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vpmin_u8

#define INSTR_CREATE_vpmin_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vpmin_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqabs_s16

#define INSTR_CREATE_vqabs_s16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vqabs_s16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqabs_s32

#define INSTR_CREATE_vqabs_s32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vqabs_s32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqabs_s8

#define INSTR_CREATE_vqabs_s8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vqabs_s8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqadd_s16

#define INSTR_CREATE_vqadd_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqadd_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqadd_s32

#define INSTR_CREATE_vqadd_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqadd_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqadd_s64

#define INSTR_CREATE_vqadd_s64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqadd_s64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqadd_s8

#define INSTR_CREATE_vqadd_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqadd_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqadd_u16

#define INSTR_CREATE_vqadd_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqadd_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqadd_u32

#define INSTR_CREATE_vqadd_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqadd_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqadd_u64

#define INSTR_CREATE_vqadd_u64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqadd_u64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqadd_u8

#define INSTR_CREATE_vqadd_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqadd_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqdmlal_s16

#define INSTR_CREATE_vqdmlal_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqdmlal_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqdmlal_s16_imm

#define INSTR_CREATE_vqdmlal_s16_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vqdmlal_s16, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqdmlal_s32

#define INSTR_CREATE_vqdmlal_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqdmlal_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqdmlal_s32_imm

#define INSTR_CREATE_vqdmlal_s32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vqdmlal_s32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqdmlsl_s16

#define INSTR_CREATE_vqdmlsl_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqdmlsl_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqdmlsl_s16_imm

#define INSTR_CREATE_vqdmlsl_s16_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vqdmlsl_s16, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqdmlsl_s32

#define INSTR_CREATE_vqdmlsl_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqdmlsl_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqdmlsl_s32_imm

#define INSTR_CREATE_vqdmlsl_s32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vqdmlsl_s32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqdmulh_s16

#define INSTR_CREATE_vqdmulh_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqdmulh_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqdmulh_s16_imm

#define INSTR_CREATE_vqdmulh_s16_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vqdmulh_s16, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqdmulh_s32

#define INSTR_CREATE_vqdmulh_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqdmulh_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqdmulh_s32_imm

#define INSTR_CREATE_vqdmulh_s32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vqdmulh_s32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqdmull_s16

#define INSTR_CREATE_vqdmull_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqdmull_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqdmull_s16_imm

#define INSTR_CREATE_vqdmull_s16_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vqdmull_s16, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqdmull_s32

#define INSTR_CREATE_vqdmull_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqdmull_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqdmull_s32_imm

#define INSTR_CREATE_vqdmull_s32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vqdmull_s32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqmovn_s16

#define INSTR_CREATE_vqmovn_s16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vqmovn_s16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqmovn_s32

#define INSTR_CREATE_vqmovn_s32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vqmovn_s32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqmovn_s64

#define INSTR_CREATE_vqmovn_s64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vqmovn_s64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqmovn_u16

#define INSTR_CREATE_vqmovn_u16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vqmovn_u16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqmovn_u32

#define INSTR_CREATE_vqmovn_u32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vqmovn_u32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqmovn_u64

#define INSTR_CREATE_vqmovn_u64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vqmovn_u64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqmovun_s16

#define INSTR_CREATE_vqmovun_s16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vqmovun_s16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqmovun_s32

#define INSTR_CREATE_vqmovun_s32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vqmovun_s32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqmovun_s64

#define INSTR_CREATE_vqmovun_s64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vqmovun_s64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqneg_s16

#define INSTR_CREATE_vqneg_s16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vqneg_s16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqneg_s32

#define INSTR_CREATE_vqneg_s32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vqneg_s32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqneg_s8

#define INSTR_CREATE_vqneg_s8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vqneg_s8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqrdmulh_s16

#define INSTR_CREATE_vqrdmulh_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqrdmulh_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqrdmulh_s16_imm

#define INSTR_CREATE_vqrdmulh_s16_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vqrdmulh_s16, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqrdmulh_s32

#define INSTR_CREATE_vqrdmulh_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqrdmulh_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqrdmulh_s32_imm

#define INSTR_CREATE_vqrdmulh_s32_imm (   dc,
  Vd,
  Vn,
  Vm,
  imm 
)     instr_create_1dst_3src((dc), OP_vqrdmulh_s32, (Vd), (Vn), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqrshl_s16

#define INSTR_CREATE_vqrshl_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqrshl_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqrshl_s32

#define INSTR_CREATE_vqrshl_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqrshl_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqrshl_s64

#define INSTR_CREATE_vqrshl_s64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqrshl_s64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqrshl_s8

#define INSTR_CREATE_vqrshl_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqrshl_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqrshl_u16

#define INSTR_CREATE_vqrshl_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqrshl_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqrshl_u32

#define INSTR_CREATE_vqrshl_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqrshl_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqrshl_u64

#define INSTR_CREATE_vqrshl_u64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqrshl_u64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqrshl_u8

#define INSTR_CREATE_vqrshl_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqrshl_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqrshrn_s16

#define INSTR_CREATE_vqrshrn_s16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqrshrn_s16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqrshrn_s32

#define INSTR_CREATE_vqrshrn_s32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqrshrn_s32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqrshrn_s64

#define INSTR_CREATE_vqrshrn_s64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqrshrn_s64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqrshrn_u16

#define INSTR_CREATE_vqrshrn_u16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqrshrn_u16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqrshrn_u32

#define INSTR_CREATE_vqrshrn_u32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqrshrn_u32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqrshrn_u64

#define INSTR_CREATE_vqrshrn_u64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqrshrn_u64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqrshrun_s16

#define INSTR_CREATE_vqrshrun_s16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqrshrun_s16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqrshrun_s32

#define INSTR_CREATE_vqrshrun_s32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqrshrun_s32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqrshrun_s64

#define INSTR_CREATE_vqrshrun_s64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqrshrun_s64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqshl_s16

#define INSTR_CREATE_vqshl_s16 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vqshl_s16, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vqshl_s32

#define INSTR_CREATE_vqshl_s32 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vqshl_s32, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vqshl_s64

#define INSTR_CREATE_vqshl_s64 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vqshl_s64, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vqshl_s8

#define INSTR_CREATE_vqshl_s8 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vqshl_s8, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vqshl_u16

#define INSTR_CREATE_vqshl_u16 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vqshl_u16, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vqshl_u32

#define INSTR_CREATE_vqshl_u32 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vqshl_u32, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vqshl_u64

#define INSTR_CREATE_vqshl_u64 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vqshl_u64, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vqshl_u8

#define INSTR_CREATE_vqshl_u8 (   dc,
  Vd,
  Vn,
  Vm_or_imm 
)     instr_create_1dst_2src((dc), OP_vqshl_u8, (Vd), (Vn), (Vm_or_imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
Vm_or_immThe source SIMD register, or integer constant, opnd_t operand.

◆ INSTR_CREATE_vqshlu_s16

#define INSTR_CREATE_vqshlu_s16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqshlu_s16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqshlu_s32

#define INSTR_CREATE_vqshlu_s32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqshlu_s32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqshlu_s64

#define INSTR_CREATE_vqshlu_s64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqshlu_s64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqshlu_s8

#define INSTR_CREATE_vqshlu_s8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqshlu_s8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqshrn_s16

#define INSTR_CREATE_vqshrn_s16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqshrn_s16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqshrn_s32

#define INSTR_CREATE_vqshrn_s32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqshrn_s32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqshrn_s64

#define INSTR_CREATE_vqshrn_s64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqshrn_s64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqshrn_u16

#define INSTR_CREATE_vqshrn_u16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqshrn_u16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqshrn_u32

#define INSTR_CREATE_vqshrn_u32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqshrn_u32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqshrn_u64

#define INSTR_CREATE_vqshrn_u64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqshrn_u64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqshrun_s16

#define INSTR_CREATE_vqshrun_s16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqshrun_s16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqshrun_s32

#define INSTR_CREATE_vqshrun_s32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqshrun_s32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqshrun_s64

#define INSTR_CREATE_vqshrun_s64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vqshrun_s64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vqsub_s16

#define INSTR_CREATE_vqsub_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqsub_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqsub_s32

#define INSTR_CREATE_vqsub_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqsub_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqsub_s64

#define INSTR_CREATE_vqsub_s64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqsub_s64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqsub_s8

#define INSTR_CREATE_vqsub_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqsub_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqsub_u16

#define INSTR_CREATE_vqsub_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqsub_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqsub_u32

#define INSTR_CREATE_vqsub_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqsub_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqsub_u64

#define INSTR_CREATE_vqsub_u64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqsub_u64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vqsub_u8

#define INSTR_CREATE_vqsub_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vqsub_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vraddhn_i16

#define INSTR_CREATE_vraddhn_i16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vraddhn_i16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vraddhn_i32

#define INSTR_CREATE_vraddhn_i32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vraddhn_i32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vraddhn_i64

#define INSTR_CREATE_vraddhn_i64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vraddhn_i64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrecpe_f32

#define INSTR_CREATE_vrecpe_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrecpe_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrecpe_u32

#define INSTR_CREATE_vrecpe_u32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrecpe_u32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrecps_f32

#define INSTR_CREATE_vrecps_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrecps_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrev16_16

#define INSTR_CREATE_vrev16_16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrev16_16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrev16_8

#define INSTR_CREATE_vrev16_8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrev16_8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrev32_16

#define INSTR_CREATE_vrev32_16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrev32_16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrev32_32

#define INSTR_CREATE_vrev32_32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrev32_32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrev32_8

#define INSTR_CREATE_vrev32_8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrev32_8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrev64_16

#define INSTR_CREATE_vrev64_16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrev64_16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrev64_32

#define INSTR_CREATE_vrev64_32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrev64_32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrev64_8

#define INSTR_CREATE_vrev64_8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrev64_8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrhadd_s16

#define INSTR_CREATE_vrhadd_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrhadd_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrhadd_s32

#define INSTR_CREATE_vrhadd_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrhadd_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrhadd_s8

#define INSTR_CREATE_vrhadd_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrhadd_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrhadd_u16

#define INSTR_CREATE_vrhadd_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrhadd_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrhadd_u32

#define INSTR_CREATE_vrhadd_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrhadd_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrhadd_u8

#define INSTR_CREATE_vrhadd_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrhadd_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrinta_f32_f32

#define INSTR_CREATE_vrinta_f32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrinta_f32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrinta_f64_f64

#define INSTR_CREATE_vrinta_f64_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrinta_f64_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrintm_f32_f32

#define INSTR_CREATE_vrintm_f32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrintm_f32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrintm_f64_f64

#define INSTR_CREATE_vrintm_f64_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrintm_f64_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrintn_f32_f32

#define INSTR_CREATE_vrintn_f32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrintn_f32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrintn_f64_f64

#define INSTR_CREATE_vrintn_f64_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrintn_f64_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrintp_f32_f32

#define INSTR_CREATE_vrintp_f32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrintp_f32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrintp_f64_f64

#define INSTR_CREATE_vrintp_f64_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrintp_f64_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrintr_f32

#define INSTR_CREATE_vrintr_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrintr_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrintr_f64

#define INSTR_CREATE_vrintr_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrintr_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrintx_f32

#define INSTR_CREATE_vrintx_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrintx_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrintx_f32_f32

#define INSTR_CREATE_vrintx_f32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrintx_f32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrintx_f64

#define INSTR_CREATE_vrintx_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrintx_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrintz_f32

#define INSTR_CREATE_vrintz_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrintz_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrintz_f32_f32

#define INSTR_CREATE_vrintz_f32_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrintz_f32_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrintz_f64

#define INSTR_CREATE_vrintz_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrintz_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrshl_s16

#define INSTR_CREATE_vrshl_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrshl_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrshl_s32

#define INSTR_CREATE_vrshl_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrshl_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrshl_s64

#define INSTR_CREATE_vrshl_s64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrshl_s64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrshl_s8

#define INSTR_CREATE_vrshl_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrshl_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrshl_u16

#define INSTR_CREATE_vrshl_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrshl_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrshl_u32

#define INSTR_CREATE_vrshl_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrshl_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrshl_u64

#define INSTR_CREATE_vrshl_u64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrshl_u64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrshl_u8

#define INSTR_CREATE_vrshl_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrshl_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrshr_s16

#define INSTR_CREATE_vrshr_s16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrshr_s16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrshr_s32

#define INSTR_CREATE_vrshr_s32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrshr_s32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrshr_s64

#define INSTR_CREATE_vrshr_s64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrshr_s64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrshr_s8

#define INSTR_CREATE_vrshr_s8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrshr_s8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrshr_u16

#define INSTR_CREATE_vrshr_u16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrshr_u16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrshr_u32

#define INSTR_CREATE_vrshr_u32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrshr_u32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrshr_u64

#define INSTR_CREATE_vrshr_u64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrshr_u64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrshr_u8

#define INSTR_CREATE_vrshr_u8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrshr_u8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrshrn_i16

#define INSTR_CREATE_vrshrn_i16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrshrn_i16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrshrn_i32

#define INSTR_CREATE_vrshrn_i32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrshrn_i32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrshrn_i64

#define INSTR_CREATE_vrshrn_i64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrshrn_i64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrsqrte_f32

#define INSTR_CREATE_vrsqrte_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrsqrte_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrsqrte_u32

#define INSTR_CREATE_vrsqrte_u32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vrsqrte_u32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrsqrts_f32

#define INSTR_CREATE_vrsqrts_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrsqrts_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrsra_s16

#define INSTR_CREATE_vrsra_s16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrsra_s16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrsra_s32

#define INSTR_CREATE_vrsra_s32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrsra_s32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrsra_s64

#define INSTR_CREATE_vrsra_s64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrsra_s64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrsra_s8

#define INSTR_CREATE_vrsra_s8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrsra_s8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrsra_u16

#define INSTR_CREATE_vrsra_u16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrsra_u16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrsra_u32

#define INSTR_CREATE_vrsra_u32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrsra_u32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrsra_u64

#define INSTR_CREATE_vrsra_u64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrsra_u64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrsra_u8

#define INSTR_CREATE_vrsra_u8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vrsra_u8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vrsubhn_i16

#define INSTR_CREATE_vrsubhn_i16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrsubhn_i16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrsubhn_i32

#define INSTR_CREATE_vrsubhn_i32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrsubhn_i32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vrsubhn_i64

#define INSTR_CREATE_vrsubhn_i64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vrsubhn_i64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsel_eq_f32

#define INSTR_CREATE_vsel_eq_f32 (   dc,
  Vd,
  imm,
  Vn,
  Vm 
)     instr_create_1dst_3src((dc), OP_vsel_eq_f32, (Vd), (imm), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsel_eq_f64

#define INSTR_CREATE_vsel_eq_f64 (   dc,
  Vd,
  imm,
  Vn,
  Vm 
)     instr_create_1dst_3src((dc), OP_vsel_eq_f64, (Vd), (imm), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsel_ge_f32

#define INSTR_CREATE_vsel_ge_f32 (   dc,
  Vd,
  imm,
  Vn,
  Vm 
)     instr_create_1dst_3src((dc), OP_vsel_ge_f32, (Vd), (imm), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsel_ge_f64

#define INSTR_CREATE_vsel_ge_f64 (   dc,
  Vd,
  imm,
  Vn,
  Vm 
)     instr_create_1dst_3src((dc), OP_vsel_ge_f64, (Vd), (imm), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsel_gt_f32

#define INSTR_CREATE_vsel_gt_f32 (   dc,
  Vd,
  imm,
  Vn,
  Vm 
)     instr_create_1dst_3src((dc), OP_vsel_gt_f32, (Vd), (imm), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsel_gt_f64

#define INSTR_CREATE_vsel_gt_f64 (   dc,
  Vd,
  imm,
  Vn,
  Vm 
)     instr_create_1dst_3src((dc), OP_vsel_gt_f64, (Vd), (imm), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsel_vs_f32

#define INSTR_CREATE_vsel_vs_f32 (   dc,
  Vd,
  imm,
  Vn,
  Vm 
)     instr_create_1dst_3src((dc), OP_vsel_vs_f32, (Vd), (imm), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsel_vs_f64

#define INSTR_CREATE_vsel_vs_f64 (   dc,
  Vd,
  imm,
  Vn,
  Vm 
)     instr_create_1dst_3src((dc), OP_vsel_vs_f64, (Vd), (imm), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
immThe integer constant opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vshl_i16

#define INSTR_CREATE_vshl_i16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshl_i16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshl_i32

#define INSTR_CREATE_vshl_i32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshl_i32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshl_i64

#define INSTR_CREATE_vshl_i64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshl_i64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshl_i8

#define INSTR_CREATE_vshl_i8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshl_i8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshl_s16

#define INSTR_CREATE_vshl_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vshl_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vshl_s32

#define INSTR_CREATE_vshl_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vshl_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vshl_s64

#define INSTR_CREATE_vshl_s64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vshl_s64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vshl_s8

#define INSTR_CREATE_vshl_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vshl_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vshl_u16

#define INSTR_CREATE_vshl_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vshl_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vshl_u32

#define INSTR_CREATE_vshl_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vshl_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vshl_u64

#define INSTR_CREATE_vshl_u64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vshl_u64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vshl_u8

#define INSTR_CREATE_vshl_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vshl_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vshll_i16

#define INSTR_CREATE_vshll_i16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshll_i16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshll_i32

#define INSTR_CREATE_vshll_i32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshll_i32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshll_i8

#define INSTR_CREATE_vshll_i8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshll_i8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshll_s16

#define INSTR_CREATE_vshll_s16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshll_s16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshll_s32

#define INSTR_CREATE_vshll_s32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshll_s32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshll_s8

#define INSTR_CREATE_vshll_s8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshll_s8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshll_u16

#define INSTR_CREATE_vshll_u16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshll_u16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshll_u32

#define INSTR_CREATE_vshll_u32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshll_u32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshll_u8

#define INSTR_CREATE_vshll_u8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshll_u8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshr_s16

#define INSTR_CREATE_vshr_s16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshr_s16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshr_s32

#define INSTR_CREATE_vshr_s32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshr_s32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshr_s64

#define INSTR_CREATE_vshr_s64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshr_s64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshr_s8

#define INSTR_CREATE_vshr_s8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshr_s8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshr_u16

#define INSTR_CREATE_vshr_u16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshr_u16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshr_u32

#define INSTR_CREATE_vshr_u32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshr_u32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshr_u64

#define INSTR_CREATE_vshr_u64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshr_u64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshr_u8

#define INSTR_CREATE_vshr_u8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshr_u8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshrn_i16

#define INSTR_CREATE_vshrn_i16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshrn_i16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshrn_i32

#define INSTR_CREATE_vshrn_i32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshrn_i32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vshrn_i64

#define INSTR_CREATE_vshrn_i64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vshrn_i64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsli_16

#define INSTR_CREATE_vsli_16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsli_16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsli_32

#define INSTR_CREATE_vsli_32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsli_32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsli_64

#define INSTR_CREATE_vsli_64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsli_64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsli_8

#define INSTR_CREATE_vsli_8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsli_8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsqrt_f32

#define INSTR_CREATE_vsqrt_f32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vsqrt_f32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsqrt_f64

#define INSTR_CREATE_vsqrt_f64 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vsqrt_f64, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsra_s16

#define INSTR_CREATE_vsra_s16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsra_s16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsra_s32

#define INSTR_CREATE_vsra_s32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsra_s32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsra_s64

#define INSTR_CREATE_vsra_s64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsra_s64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsra_s8

#define INSTR_CREATE_vsra_s8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsra_s8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsra_u16

#define INSTR_CREATE_vsra_u16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsra_u16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsra_u32

#define INSTR_CREATE_vsra_u32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsra_u32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsra_u64

#define INSTR_CREATE_vsra_u64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsra_u64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsra_u8

#define INSTR_CREATE_vsra_u8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsra_u8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsri_16

#define INSTR_CREATE_vsri_16 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsri_16, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsri_32

#define INSTR_CREATE_vsri_32 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsri_32, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsri_64

#define INSTR_CREATE_vsri_64 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsri_64, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vsri_8

#define INSTR_CREATE_vsri_8 (   dc,
  Vd,
  Vm,
  imm 
)     instr_create_1dst_2src((dc), OP_vsri_8, (Vd), (Vm), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vst1_16

#define INSTR_CREATE_vst1_16 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_16, 1, 1, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst1_16_wbimm

#define INSTR_CREATE_vst1_16_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_16, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst1_16_wbreg

#define INSTR_CREATE_vst1_16_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst1_16, 2, 3, list_len, 0, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst1_32

#define INSTR_CREATE_vst1_32 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_32, 1, 1, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst1_32_wbimm

#define INSTR_CREATE_vst1_32_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_32, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst1_32_wbreg

#define INSTR_CREATE_vst1_32_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst1_32, 2, 3, list_len, 0, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst1_64

#define INSTR_CREATE_vst1_64 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_64, 1, 1, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst1_64_wbimm

#define INSTR_CREATE_vst1_64_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_64, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst1_64_wbreg

#define INSTR_CREATE_vst1_64_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst1_64, 2, 3, list_len, 0, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst1_8

#define INSTR_CREATE_vst1_8 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_8, 1, 1, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst1_8_wbimm

#define INSTR_CREATE_vst1_8_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst1_8, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst1_8_wbreg

#define INSTR_CREATE_vst1_8_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst1_8, 2, 3, list_len, 0, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst1_lane_16

#define INSTR_CREATE_vst1_lane_16 (   dc,
  mem,
  Vt,
  imm,
  imm2 
)     instr_create_1dst_3src((dc), OP_vst1_lane_16, (mem), (Vt), (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
VtThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_vst1_lane_16_wbimm

#define INSTR_CREATE_vst1_lane_16_wbimm (   dc,
  mem,
  Vt,
  imm,
  imm2 
)
Value:
instr_create_2dst_4src((dc), OP_vst1_lane_16, (mem), \
opnd_create_reg(opnd_get_base(mem)), (Vt), (imm), (imm2), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
VtThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_vst1_lane_16_wbreg

#define INSTR_CREATE_vst1_lane_16_wbreg (   dc,
  mem,
  Vt,
  imm,
  imm2,
  Rm 
)
Value:
instr_create_2dst_5src((dc), OP_vst1_lane_16, (mem), \
opnd_create_reg(opnd_get_base(mem)), (Vt), (imm), (imm2), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
VtThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_vst1_lane_32

#define INSTR_CREATE_vst1_lane_32 (   dc,
  mem,
  Vt,
  imm,
  imm2 
)     instr_create_1dst_3src((dc), OP_vst1_lane_32, (mem), (Vt), (imm), (imm2))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
VtThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_vst1_lane_32_wbimm

#define INSTR_CREATE_vst1_lane_32_wbimm (   dc,
  mem,
  Vt,
  imm,
  imm2 
)
Value:
instr_create_2dst_4src((dc), OP_vst1_lane_32, (mem), \
opnd_create_reg(opnd_get_base(mem)), (Vt), (imm), (imm2), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
VtThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.

◆ INSTR_CREATE_vst1_lane_32_wbreg

#define INSTR_CREATE_vst1_lane_32_wbreg (   dc,
  mem,
  Vt,
  imm,
  imm2,
  Rm 
)
Value:
instr_create_2dst_5src((dc), OP_vst1_lane_32, (mem), \
opnd_create_reg(opnd_get_base(mem)), (Vt), (imm), (imm2), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
VtThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_vst1_lane_8

#define INSTR_CREATE_vst1_lane_8 (   dc,
  mem,
  Vt,
  imm 
)     instr_create_1dst_2src((dc), OP_vst1_lane_8, (mem), (Vt), (imm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
VtThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vst1_lane_8_wbimm

#define INSTR_CREATE_vst1_lane_8_wbimm (   dc,
  mem,
  Vt,
  imm 
)
Value:
instr_create_2dst_3src((dc), OP_vst1_lane_8, (mem), \
opnd_create_reg(opnd_get_base(mem)), (Vt), (imm), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
VtThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.

◆ INSTR_CREATE_vst1_lane_8_wbreg

#define INSTR_CREATE_vst1_lane_8_wbreg (   dc,
  mem,
  Vt,
  imm,
  Rm 
)
Value:
instr_create_2dst_4src((dc), OP_vst1_lane_8, (mem), \
opnd_create_reg(opnd_get_base(mem)), (Vt), (imm), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
VtThe source SIMD register opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.

◆ INSTR_CREATE_vst2_16

#define INSTR_CREATE_vst2_16 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_16, 1, 1, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_16_wbimm

#define INSTR_CREATE_vst2_16_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_16, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_16_wbreg

#define INSTR_CREATE_vst2_16_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst2_16, 2, 3, list_len, 0, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_32

#define INSTR_CREATE_vst2_32 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_32, 1, 1, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_32_wbimm

#define INSTR_CREATE_vst2_32_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_32, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_32_wbreg

#define INSTR_CREATE_vst2_32_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst2_32, 2, 3, list_len, 0, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_8

#define INSTR_CREATE_vst2_8 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_8, 1, 1, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_8_wbimm

#define INSTR_CREATE_vst2_8_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_8, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_8_wbreg

#define INSTR_CREATE_vst2_8_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst2_8, 2, 3, list_len, 0, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_lane_16

#define INSTR_CREATE_vst2_lane_16 (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_lane_16, 1, 2, list_len, 0, (mem), \
(imm), (imm2), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_lane_16_wbimm

#define INSTR_CREATE_vst2_lane_16_wbimm (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_lane_16, 2, 3, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), (imm2), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_lane_16_wbreg

#define INSTR_CREATE_vst2_lane_16_wbreg (   dc,
  mem,
  imm,
  imm2,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst2_lane_16, 2, 4, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), (imm2), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_lane_32

#define INSTR_CREATE_vst2_lane_32 (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_lane_32, 1, 2, list_len, 0, (mem), \
(imm), (imm2), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_lane_32_wbimm

#define INSTR_CREATE_vst2_lane_32_wbimm (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_lane_32, 2, 3, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), (imm2), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_lane_32_wbreg

#define INSTR_CREATE_vst2_lane_32_wbreg (   dc,
  mem,
  imm,
  imm2,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst2_lane_32, 2, 4, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), (imm2), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_lane_8

#define INSTR_CREATE_vst2_lane_8 (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_lane_8, 1, 2, list_len, 0, (mem), (imm), \
(imm2), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_lane_8_wbimm

#define INSTR_CREATE_vst2_lane_8_wbimm (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst2_lane_8, 2, 3, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), (imm2), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst2_lane_8_wbreg

#define INSTR_CREATE_vst2_lane_8_wbreg (   dc,
  mem,
  imm,
  imm2,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst2_lane_8, 2, 4, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), (imm2), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_16

#define INSTR_CREATE_vst3_16 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_16, 1, 1, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_16_wbimm

#define INSTR_CREATE_vst3_16_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_16, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_16_wbreg

#define INSTR_CREATE_vst3_16_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst3_16, 2, 3, list_len, 0, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_32

#define INSTR_CREATE_vst3_32 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_32, 1, 1, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_32_wbimm

#define INSTR_CREATE_vst3_32_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_32, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_32_wbreg

#define INSTR_CREATE_vst3_32_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst3_32, 2, 3, list_len, 0, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_8

#define INSTR_CREATE_vst3_8 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_8, 1, 1, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_8_wbimm

#define INSTR_CREATE_vst3_8_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_8, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_8_wbreg

#define INSTR_CREATE_vst3_8_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst3_8, 2, 3, list_len, 0, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_lane_16

#define INSTR_CREATE_vst3_lane_16 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_lane_16, 1, 1, list_len, 0, (mem), \
(imm), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_lane_16_wbimm

#define INSTR_CREATE_vst3_lane_16_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_lane_16, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_lane_16_wbreg

#define INSTR_CREATE_vst3_lane_16_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst3_lane_16, 2, 3, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_lane_32

#define INSTR_CREATE_vst3_lane_32 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_lane_32, 1, 1, list_len, 0, (mem), \
(imm), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_lane_32_wbimm

#define INSTR_CREATE_vst3_lane_32_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_lane_32, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_lane_32_wbreg

#define INSTR_CREATE_vst3_lane_32_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst3_lane_32, 2, 3, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_lane_8

#define INSTR_CREATE_vst3_lane_8 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_lane_8, 1, 1, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_lane_8_wbimm

#define INSTR_CREATE_vst3_lane_8_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst3_lane_8, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst3_lane_8_wbreg

#define INSTR_CREATE_vst3_lane_8_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst3_lane_8, 2, 3, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_16

#define INSTR_CREATE_vst4_16 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_16, 1, 1, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_16_wbimm

#define INSTR_CREATE_vst4_16_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_16, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_16_wbreg

#define INSTR_CREATE_vst4_16_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst4_16, 2, 3, list_len, 0, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_32

#define INSTR_CREATE_vst4_32 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_32, 1, 1, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_32_wbimm

#define INSTR_CREATE_vst4_32_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_32, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_32_wbreg

#define INSTR_CREATE_vst4_32_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst4_32, 2, 3, list_len, 0, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_8

#define INSTR_CREATE_vst4_8 (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_8, 1, 1, list_len, 0, (mem), (imm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_8_wbimm

#define INSTR_CREATE_vst4_8_wbimm (   dc,
  mem,
  imm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_8, 2, 2, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_8_wbreg

#define INSTR_CREATE_vst4_8_wbreg (   dc,
  mem,
  imm,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst4_8, 2, 3, list_len, 0, (mem), opnd_create_reg(opnd_get_base(mem)), \
(imm), opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_lane_16

#define INSTR_CREATE_vst4_lane_16 (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_lane_16, 1, 2, list_len, 0, (mem), \
(imm), (imm2), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_lane_16_wbimm

#define INSTR_CREATE_vst4_lane_16_wbimm (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_lane_16, 2, 3, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), (imm2), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_lane_16_wbreg

#define INSTR_CREATE_vst4_lane_16_wbreg (   dc,
  mem,
  imm,
  imm2,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst4_lane_16, 2, 4, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), (imm2), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_lane_32

#define INSTR_CREATE_vst4_lane_32 (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_lane_32, 1, 2, list_len, 0, (mem), \
(imm), (imm2), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_lane_32_wbimm

#define INSTR_CREATE_vst4_lane_32_wbimm (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_lane_32, 2, 3, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), (imm2), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_lane_32_wbreg

#define INSTR_CREATE_vst4_lane_32_wbreg (   dc,
  mem,
  imm,
  imm2,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst4_lane_32, 2, 4, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), (imm2), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_lane_8

#define INSTR_CREATE_vst4_lane_8 (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_lane_8, 1, 2, list_len, 0, (mem), (imm), \
(imm2), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_lane_8_wbimm

#define INSTR_CREATE_vst4_lane_8_wbimm (   dc,
  mem,
  imm,
  imm2,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vst4_lane_8, 2, 3, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), (imm2), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vst4_lane_8_wbreg

#define INSTR_CREATE_vst4_lane_8_wbreg (   dc,
  mem,
  imm,
  imm2,
  Rm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc( \
(dc), OP_vst4_lane_8, 2, 4, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), (imm), (imm2), \
opnd_create_reg_ex(opnd_get_reg(Rm), 0, DR_OPND_SHIFTED), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
immThe integer constant opnd_t operand.
imm2The second integer constant opnd_t operand.
RmThe source register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vstm

#define INSTR_CREATE_vstm (   dc,
  mem,
  list_len,
  ... 
)     instr_create_Ndst_Msrc_varsrc((dc), OP_vstm, 1, 0, list_len, 0, (mem), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vstm_wb

#define INSTR_CREATE_vstm_wb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vstm, 2, 1, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vstmdb

#define INSTR_CREATE_vstmdb (   dc,
  mem,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vstmdb, 2, 1, list_len, 0, (mem), \
opnd_create_reg(opnd_get_base(mem)), \
opnd_create_reg(opnd_get_base(mem)), __VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vstr

#define INSTR_CREATE_vstr (   dc,
  mem,
  Vt 
)    instr_create_1dst_1src((dc), OP_vstr, (mem), (Vt))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
memThe memory opnd_t operand.
VtThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsub_f32

#define INSTR_CREATE_vsub_f32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsub_f32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsub_f64

#define INSTR_CREATE_vsub_f64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsub_f64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsub_i16

#define INSTR_CREATE_vsub_i16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsub_i16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsub_i32

#define INSTR_CREATE_vsub_i32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsub_i32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsub_i64

#define INSTR_CREATE_vsub_i64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsub_i64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsub_i8

#define INSTR_CREATE_vsub_i8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsub_i8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsubhn_i16

#define INSTR_CREATE_vsubhn_i16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsubhn_i16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsubhn_i32

#define INSTR_CREATE_vsubhn_i32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsubhn_i32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsubhn_i64

#define INSTR_CREATE_vsubhn_i64 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsubhn_i64, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsubl_s16

#define INSTR_CREATE_vsubl_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsubl_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsubl_s32

#define INSTR_CREATE_vsubl_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsubl_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsubl_s8

#define INSTR_CREATE_vsubl_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsubl_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsubl_u16

#define INSTR_CREATE_vsubl_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsubl_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsubl_u32

#define INSTR_CREATE_vsubl_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsubl_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsubl_u8

#define INSTR_CREATE_vsubl_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsubl_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsubw_s16

#define INSTR_CREATE_vsubw_s16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsubw_s16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsubw_s32

#define INSTR_CREATE_vsubw_s32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsubw_s32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsubw_s8

#define INSTR_CREATE_vsubw_s8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsubw_s8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsubw_u16

#define INSTR_CREATE_vsubw_u16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsubw_u16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsubw_u32

#define INSTR_CREATE_vsubw_u32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsubw_u32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vsubw_u8

#define INSTR_CREATE_vsubw_u8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vsubw_u8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vswp

#define INSTR_CREATE_vswp (   dc,
  Vd,
  Vm 
)    instr_create_1dst_1src((dc), OP_vswp, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vtbl_8

#define INSTR_CREATE_vtbl_8 (   dc,
  Vd,
  Vm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vtbl_8, 1, 1, list_len, 0, (Vd), (Vm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vtbx_8

#define INSTR_CREATE_vtbx_8 (   dc,
  Vd,
  Vm,
  list_len,
  ... 
)
Value:
instr_create_Ndst_Msrc_varsrc((dc), OP_vtbx_8, 1, 1, list_len, 0, (Vd), (Vm), \
__VA_ARGS__)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.
list_lenThe number of registers in the register list.
...The register list as separate opnd_t arguments. The registers in the list must be in increasing order.

◆ INSTR_CREATE_vtrn_16

#define INSTR_CREATE_vtrn_16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vtrn_16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vtrn_32

#define INSTR_CREATE_vtrn_32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vtrn_32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vtrn_8

#define INSTR_CREATE_vtrn_8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vtrn_8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vtst_16

#define INSTR_CREATE_vtst_16 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vtst_16, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vtst_32

#define INSTR_CREATE_vtst_32 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vtst_32, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vtst_8

#define INSTR_CREATE_vtst_8 (   dc,
  Vd,
  Vn,
  Vm 
)     instr_create_1dst_2src((dc), OP_vtst_8, (Vd), (Vn), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VnThe source SIMD register opnd_t operand.
VmThe second source SIMD register opnd_t operand.

◆ INSTR_CREATE_vuzp_16

#define INSTR_CREATE_vuzp_16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vuzp_16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vuzp_32

#define INSTR_CREATE_vuzp_32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vuzp_32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vuzp_8

#define INSTR_CREATE_vuzp_8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vuzp_8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vzip_16

#define INSTR_CREATE_vzip_16 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vzip_16, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vzip_32

#define INSTR_CREATE_vzip_32 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vzip_32, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_vzip_8

#define INSTR_CREATE_vzip_8 (   dc,
  Vd,
  Vm 
)     instr_create_1dst_1src((dc), OP_vzip_8, (Vd), (Vm))

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination SIMD register opnd_t operand.
VmThe source SIMD register opnd_t operand.

◆ INSTR_CREATE_wfe

#define INSTR_CREATE_wfe (   dc)    instr_create_0dst_0src((dc), OP_wfe)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ INSTR_CREATE_wfi

#define INSTR_CREATE_wfi (   dc)    instr_create_0dst_0src((dc), OP_wfi)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ INSTR_CREATE_yield

#define INSTR_CREATE_yield (   dc)    instr_create_0dst_0src((dc), OP_yield)

This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the given explicit operands, automatically supplying any implicit operands. The operands should be listed with destinations first, followed by sources. The ordering within these two groups should follow the conventional assembly ordering.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ OPND_CREATE_ABSMEM

#define OPND_CREATE_ABSMEM (   addr,
  size 
)    opnd_create_rel_addr(addr, size)

Create an absolute address operand encoded as pc-relative. Encoding will fail if addr is out of the maximum signed displacement reach for the architecture and ISA mode.

◆ OPND_CREATE_INT

#define OPND_CREATE_INT (   val)    OPND_CREATE_INTPTR(val)

Create an immediate integer operand. For ARM, the size of an immediate is ignored when encoding, so there is no need to specify the final size.

◆ OPND_CREATE_INT_MSR_G

#define OPND_CREATE_INT_MSR_G ( )    opnd_create_immed_int(EFLAGS_MSR_G, OPSZ_4b)

The immediate opnd_t for use with OP_msr to write the apsr_g status flags.

◆ OPND_CREATE_INT_MSR_NZCVQ

#define OPND_CREATE_INT_MSR_NZCVQ ( )    opnd_create_immed_int(EFLAGS_MSR_NZCVQ, OPSZ_4b)

The immediate opnd_t for use with OP_msr to write the nzcvq status flags.

◆ OPND_CREATE_INT_MSR_NZCVQG

#define OPND_CREATE_INT_MSR_NZCVQG ( )    opnd_create_immed_int(EFLAGS_MSR_NZCVQG, OPSZ_4b)

The immediate opnd_t for use with OP_msr to write the apsr_nzcvqg status flags.

◆ OPND_CREATE_MEMLIST

#define OPND_CREATE_MEMLIST (   base)     opnd_create_base_disp(base, DR_REG_NULL, 0, 0, OPSZ_VAR_REGLIST)

A memory opnd_t that auto-sizes at encode time to match a register list.

◆ OPND_CREATE_NEG_REG

#define OPND_CREATE_NEG_REG (   reg)    opnd_create_reg_ex(reg, 0, DR_OPND_NEGATED)

Create a negated register operand.

◆ XINST_CREATE_add

#define XINST_CREATE_add (   dc,
  d,
  s 
)    INSTR_CREATE_add((dc), (d), (d), (s))

This platform-independent macro creates an instr_t for an addition instruction that does not affect the status flags.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
sThe opnd_t explicit source operand for the instruction.

◆ XINST_CREATE_add_2src

#define XINST_CREATE_add_2src (   dc,
  d,
  s1,
  s2 
)    INSTR_CREATE_add((dc), (d), (s1), (s2))

This platform-independent macro creates an instr_t for an addition instruction that does not affect the status flags and takes two sources plus a destination.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
s1The opnd_t explicit first source operand for the instruction. This must be a register.
s2The opnd_t explicit source operand for the instruction. This can be either a register or a 32-bit immediate integer on x86.

◆ XINST_CREATE_add_s

#define XINST_CREATE_add_s (   dc,
  d,
  s 
)    INSTR_CREATE_adds((dc), (d), (d), (s))

This platform-independent macro creates an instr_t for an addition instruction that does affect the status flags.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
sThe opnd_t explicit source operand for the instruction.

◆ XINST_CREATE_add_sll

#define XINST_CREATE_add_sll (   dc,
  d,
  s1,
  s2_toshift,
  shift_amount 
)
Value:
INSTR_CREATE_add_shimm((dc), (d), (s1), (s2_toshift), \
OPND_CREATE_INT8(DR_SHIFT_LSL), \
OPND_CREATE_INT8(shift_amount))

This platform-independent macro creates an instr_t for an addition instruction that does not affect the status flags and takes two register sources plus a destination, with one source being shifted logically left by an immediate amount that is limited to either 0, 1, 2, or 3.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
s1The opnd_t explicit first source operand for the instruction. This must be a register.
s2_toshiftThe opnd_t explicit source operand for the instruction. This must be a register.
shift_amountAn integer value that must be either 0, 1, 2, or 3.

◆ XINST_CREATE_and_s

#define XINST_CREATE_and_s (   dc,
  d,
  s 
)    INSTR_CREATE_ands((dc), (d), (d), (s))

This platform-independent macro creates an instr_t for a bitwise and instruction that does affect the status flags.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
sThe opnd_t explicit source operand for the instruction.

◆ XINST_CREATE_call

#define XINST_CREATE_call (   dc,
  t 
)    INSTR_CREATE_bl((dc), (t))

This platform-independent macro creates an instr_t for an unconditional branch instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
tThe opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded).

◆ XINST_CREATE_call_reg

#define XINST_CREATE_call_reg (   dc,
  r 
)    INSTR_CREATE_blx_ind(dc, r)

This platform-independent macro creates an instr_t for an indirect call instr through a register.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe opnd_t explicit source operand for the instruction. This should be a reg_id_t operand with the address of the subroutine.

◆ XINST_CREATE_cmp

#define XINST_CREATE_cmp (   dc,
  s1,
  s2 
)    INSTR_CREATE_cmp((dc), (s1), (s2))

This platform-independent macro creates an instr_t for a comparison instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
s1The opnd_t explicit source operand for the instruction.
s2The opnd_t explicit source operand for the instruction.

◆ XINST_CREATE_debug_instr

#define XINST_CREATE_debug_instr (   dc)    INSTR_CREATE_bkpt((dc), OPND_CREATE_INT8(1))

This platform-independent macro creates an instr_t for a debug trap instruction, automatically supplying any implicit operands.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ XINST_CREATE_interrupt

#define XINST_CREATE_interrupt (   dc,
  i 
)    INSTR_CREATE_svc(dc, (i))

This platform-independent macro creates an instr_t for a software interrupt instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
iThe source integer constant opnd_t operand.

◆ XINST_CREATE_jump

#define XINST_CREATE_jump (   dc,
  t 
)    INSTR_CREATE_b((dc), (t))

This platform-independent macro creates an instr_t for an unconditional branch instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
tThe opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded).

◆ XINST_CREATE_jump_cond

#define XINST_CREATE_jump_cond (   dc,
  pred,
  t 
)     (INSTR_PRED(INSTR_CREATE_b((dc), (t)), (pred)))

This platform-independent macro creates an instr_t for a conditional branch instruction that branches if the previously-set condition codes indicate the condition indicated by pred.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
predThe dr_pred_type_t condition to match.
tThe opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded).

◆ XINST_CREATE_jump_mem

#define XINST_CREATE_jump_mem (   dc,
  m 
)     INSTR_CREATE_ldr((dc), opnd_create_reg(DR_REG_PC), (m))

This platform-independent macro creates an instr_t for an indirect jump through memory instruction. For AArch32, the memory address must be aligned to 4.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
mThe memory opnd holding the target.

◆ XINST_CREATE_jump_reg

#define XINST_CREATE_jump_reg (   dc,
  r 
)    INSTR_CREATE_bx((dc), (r))

This platform-independent macro creates an instr_t for an indirect jump instruction through a register.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe register opnd holding the target.

◆ XINST_CREATE_jump_short

#define XINST_CREATE_jump_short (   dc,
  t 
)
Value:
(dr_get_isa_mode(dc) == DR_ISA_ARM_THUMB ? INSTR_CREATE_b_short((dc), (t)) \
: INSTR_CREATE_b((dc), (t)))

This platform-independent macro creates an instr_t for an unconditional branch instruction with the smallest available reach.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
tThe opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded).

◆ XINST_CREATE_load

#define XINST_CREATE_load (   dc,
  r,
  m 
)    INSTR_CREATE_ldr((dc), (r), (m))

This platform-independent macro creates an instr_t for a 4-byte or 8-byte (x64 only) memory load instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe destination register opnd.
mThe source memory opnd.

◆ XINST_CREATE_load_1byte

#define XINST_CREATE_load_1byte (   dc,
  r,
  m 
)    INSTR_CREATE_ldrb((dc), (r), (m))

This platform-independent macro creates an instr_t for a 1-byte memory load instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe destination register opnd.
mThe source memory opnd.

◆ XINST_CREATE_load_1byte_zext4

#define XINST_CREATE_load_1byte_zext4 (   dc,
  r,
  m 
)    INSTR_CREATE_ldrb((dc), (r), (m))

This platform-independent macro creates an instr_t which loads 1 byte from memory, zero-extends it to 4 bytes, and writes it to a 4 byte destination register.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe destination register opnd.
mThe source memory opnd.

◆ XINST_CREATE_load_2bytes

#define XINST_CREATE_load_2bytes (   dc,
  r,
  m 
)    INSTR_CREATE_ldrh((dc), (r), (m))

This platform-independent macro creates an instr_t for a 2-byte memory load instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe destination register opnd.
mThe source memory opnd.

◆ XINST_CREATE_load_int

#define XINST_CREATE_load_int (   dc,
  r,
  i 
)
Value:
(opnd_get_immed_int(i) < 0 \
? INSTR_CREATE_mvn((dc), (r), OPND_CREATE_INTPTR(-opnd_get_immed_int(i))) \
: INSTR_CREATE_movw((dc), (r), (i)))

This platform-independent macro creates an instr_t for an immediate integer load instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe destination register opnd.
iThe source immediate integer opnd.

◆ XINST_CREATE_load_pair

#define XINST_CREATE_load_pair (   dc,
  r1,
  r2,
  m 
)    INSTR_CREATE_ldrd((dc), (r1), (r2), (m))

This AArchXX-platform-independent macro creates an instr_t for a 2-register memory store instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
r1The first register opnd.
r2The second register opnd.
mThe source memory opnd.

◆ XINST_CREATE_load_simd

#define XINST_CREATE_load_simd (   dc,
  r,
  m 
)    INSTR_CREATE_vldr((dc), (r), (m))

This platform-independent macro creates an instr_t for a multimedia register load instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe destination register opnd.
mThe source memory opnd.
Note
Loading to 128-bit registers is not supported on 32-bit ARM.

◆ XINST_CREATE_move

#define XINST_CREATE_move (   dc,
  d,
  s 
)    INSTR_CREATE_mov((dc), (d), (s))

This platform-independent macro creates an instr_t for a register to register move instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe destination register opnd.
sThe source register opnd.

◆ XINST_CREATE_nop

#define XINST_CREATE_nop (   dc)    INSTR_CREATE_nop(dc)

This platform-independent macro creates an instr_t for a nop instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ XINST_CREATE_return

#define XINST_CREATE_return (   dc)    INSTR_CREATE_pop(dc, opnd_create_reg(DR_REG_PC))

This platform-independent macro creates an instr_t for a return instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ XINST_CREATE_slr_s

#define XINST_CREATE_slr_s (   dc,
  d,
  s 
)    INSTR_CREATE_lsrs((dc), (d), (d), (s))

This platform-independent macro creates an instr_t for a logical right shift instruction that does affect the status flags.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
sThe opnd_t explicit source operand for the instruction.

◆ XINST_CREATE_store

#define XINST_CREATE_store (   dc,
  m,
  r 
)    INSTR_CREATE_str((dc), (m), (r))

This platform-independent macro creates an instr_t for a 4-byte or 8-byte (x64 only) memory store instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
mThe destination memory opnd.
rThe source register opnd.

◆ XINST_CREATE_store_1byte

#define XINST_CREATE_store_1byte (   dc,
  m,
  r 
)    INSTR_CREATE_strb((dc), (m), (r))

This platform-independent macro creates an instr_t for a 1-byte memory store instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
mThe destination memory opnd.
rThe source register opnd.

◆ XINST_CREATE_store_2bytes

#define XINST_CREATE_store_2bytes (   dc,
  m,
  r 
)    INSTR_CREATE_strh((dc), (m), (r))

This platform-independent macro creates an instr_t for a 2-byte memory store instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
mThe destination memory opnd.
rThe source register opnd.

◆ XINST_CREATE_store_pair

#define XINST_CREATE_store_pair (   dc,
  m,
  r1,
  r2 
)    INSTR_CREATE_strd((dc), (m), (r1), (r2))

This AArchXX-platform-independent macro creates an instr_t for a 2-register memory store instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
mThe destination memory opnd.
r1The first register opnd.
r2The second register opnd.

◆ XINST_CREATE_store_simd

#define XINST_CREATE_store_simd (   dc,
  m,
  r 
)    INSTR_CREATE_vstr((dc), (m), (r))

This platform-independent macro creates an instr_t for a multimedia register store instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
mThe destination memory opnd.
rThe source register opnd.
Note
Storing from 128-bit registers is not supported on 32-bit ARM.

◆ XINST_CREATE_sub

#define XINST_CREATE_sub (   dc,
  d,
  s 
)    INSTR_CREATE_sub((dc), (d), (d), (s))

This platform-independent macro creates an instr_t for a subtraction instruction that does not affect the status flags.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
sThe opnd_t explicit source operand for the instruction.

◆ XINST_CREATE_sub_s

#define XINST_CREATE_sub_s (   dc,
  d,
  s 
)    INSTR_CREATE_subs((dc), (d), (d), (s))

This platform-independent macro creates an instr_t for a subtraction instruction that does affect the status flags.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
sThe opnd_t explicit source operand for the instruction.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Immediate values for INSTR_CREATE_dmb().

Enumerator
DR_VG_NUM_ARGS 

Defines the maximum number of arguments that can be passed to a Valgrind annotation, and accordingly specifies the length of the array vg_client_request_t.args.

DR_NOTE_ANNOTATION 

Identifies an annotation point. This label will be replaced by a clean call to the registered annotation handler.

DR_NOTE_CLEAN_CALL_END 

Identifies the end of a clean call.

DR_NOTE_REG_BARRIER 

Identifies a point at which clients should restore all registers to their application values, as required for DR's internal block mangling.

EFLAGS_CF 

The bit in the eflags register of CF (Carry Flag).

EFLAGS_PF 

The bit in the eflags register of PF (Parity Flag).

EFLAGS_AF 

The bit in the eflags register of AF (Aux Carry Flag).

EFLAGS_ZF 

The bit in the eflags register of ZF (Zero Flag).

EFLAGS_SF 

The bit in the eflags register of SF (Sign Flag).

EFLAGS_DF 

The bit in the eflags register of DF (Direction Flag).

EFLAGS_OF 

The bit in the eflags register of OF (Overflow Flag).

EFLAGS_ARITH 

The bits in the eflags register of CF, PF, AF, ZF, SF, OF.

DR_DMB_OSHLD 

DMB Outer Shareable - Loads.

DR_DMB_OSHST 

DMB Outer Shareable - Stores.

DR_DMB_OSH 

DMB Outer Shareable - Loads and Stores.

DR_DMB_NSHLD 

DMB Non Shareable - Loads.

DR_DMB_NSHST 

DMB Non Shareable - Stores.

DR_DMB_NSH 

DMB Non Shareable - Loads and Stores.

DR_DMB_ISHLD 

DMB Inner Shareable - Loads.

DR_DMB_ISHST 

DMB Inner Shareable - Stores.

DR_DMB_ISH 

DMB Inner Shareable - Loads and Stores.

DR_DMB_LD 

DMB Full System - Loads.

DR_DMB_ST 

DMB Full System - Stores.

DR_DMB_SY 

DMB Full System - Loads and Stores.

OP_UNDECODED 

INVALID opcode

OP_CONTD 

UNDECODED opcode

OP_LABEL 

CONTD opcode

OP_adc 

LABEL opcode ARM adc opcode.

OP_adcs 

ARM adcs opcode.

OP_add 

ARM add opcode.

OP_adds 

ARM adds opcode.

OP_addw 

ARM addw opcode.

OP_aesd_8 

ARM aesd_8 opcode.

OP_aese_8 

ARM aese_8 opcode.

OP_aesimc_8 

ARM aesimc_8 opcode.

OP_aesmc_8 

ARM aesmc_8 opcode.

OP_and 

ARM and opcode.

OP_ands 

ARM ands opcode.

OP_asr 

ARM asr opcode.

OP_asrs 

ARM asrs opcode.

OP_b 

ARM b opcode.

OP_b_short 

ARM b_short opcode.

OP_bfc 

ARM bfc opcode.

OP_bfi 

ARM bfi opcode.

OP_bic 

ARM bic opcode.

OP_bics 

ARM bics opcode.

OP_bkpt 

ARM bkpt opcode.

OP_bl 

ARM bl opcode.

OP_blx 

ARM blx opcode.

OP_blx_ind 

ARM blx_ind opcode.

OP_bx 

ARM bx opcode.

OP_bxj 

ARM bxj opcode.

OP_cbnz 

ARM cbnz opcode.

OP_cbz 

ARM cbz opcode.

OP_cdp 

ARM cdp opcode.

OP_cdp2 

ARM cdp2 opcode.

OP_clrex 

ARM clrex opcode.

OP_clz 

ARM clz opcode.

OP_cmn 

ARM cmn opcode.

OP_cmp 

ARM cmp opcode.

OP_cps 

ARM cps opcode.

OP_cpsid 

ARM cpsid opcode.

OP_cpsie 

ARM cpsie opcode.

OP_crc32b 

ARM crc32b opcode.

OP_crc32cb 

ARM crc32cb opcode.

OP_crc32h 

ARM crc32h opcode.

OP_crc32ch 

ARM crc32ch opcode.

OP_crc32w 

ARM crc32w opcode.

OP_crc32cw 

ARM crc32cw opcode.

OP_dbg 

ARM dbg opcode.

OP_dcps1 

ARM dcps1 opcode.

OP_dcps2 

ARM dcps2 opcode.

OP_dcps3 

ARM dcps3 opcode.

OP_dmb 

ARM dmb opcode.

OP_dsb 

ARM dsb opcode.

OP_enterx 

ARM enterx opcode.

OP_eor 

ARM eor opcode.

OP_eors 

ARM eors opcode.

OP_eret 

ARM eret opcode.

OP_hlt 

ARM hlt opcode.

OP_hvc 

ARM hvc opcode.

OP_isb 

ARM isb opcode.

OP_it 

ARM it opcode.

OP_lda 

ARM lda opcode.

OP_ldab 

ARM ldab opcode.

OP_ldaex 

ARM ldaex opcode.

OP_ldaexb 

ARM ldaexb opcode.

OP_ldaexd 

ARM ldaexd opcode.

OP_ldaexh 

ARM ldaexh opcode.

OP_ldah 

ARM ldah opcode.

OP_ldc 

ARM ldc opcode.

OP_ldc2 

ARM ldc2 opcode.

OP_ldc2l 

ARM ldc2l opcode.

OP_ldcl 

ARM ldcl opcode.

OP_ldm 

ARM ldm opcode.

OP_ldm_priv 

ARM ldm_priv opcode.

OP_ldmda 

ARM ldmda opcode.

OP_ldmda_priv 

ARM ldmda_priv opcode.

OP_ldmdb 

ARM ldmdb opcode.

OP_ldmdb_priv 

ARM ldmdb_priv opcode.

OP_ldmib 

ARM ldmib opcode.

OP_ldmib_priv 

ARM ldmib_priv opcode.

OP_ldr 

ARM ldr opcode.

OP_ldrb 

ARM ldrb opcode.

OP_ldrbt 

ARM ldrbt opcode.

OP_ldrd 

ARM ldrd opcode.

OP_ldrex 

ARM ldrex opcode.

OP_ldrexb 

ARM ldrexb opcode.

OP_ldrexd 

ARM ldrexd opcode.

OP_ldrexh 

ARM ldrexh opcode.

OP_ldrh 

ARM ldrh opcode.

OP_ldrht 

ARM ldrht opcode.

OP_ldrsb 

ARM ldrsb opcode.

OP_ldrsbt 

ARM ldrsbt opcode.

OP_ldrsh 

ARM ldrsh opcode.

OP_ldrsht 

ARM ldrsht opcode.

OP_ldrt 

ARM ldrt opcode.

OP_leavex 

ARM leavex opcode.

OP_lsl 

ARM lsl opcode.

OP_lsls 

ARM lsls opcode.

OP_lsr 

ARM lsr opcode.

OP_lsrs 

ARM lsrs opcode.

OP_mcr 

ARM mcr opcode.

OP_mcr2 

ARM mcr2 opcode.

OP_mcrr 

ARM mcrr opcode.

OP_mcrr2 

ARM mcrr2 opcode.

OP_mla 

ARM mla opcode.

OP_mlas 

ARM mlas opcode.

OP_mls 

ARM mls opcode.

OP_mov 

ARM mov opcode.

OP_movs 

ARM movs opcode.

OP_movt 

ARM movt opcode.

OP_movw 

ARM movw opcode.

OP_mrc 

ARM mrc opcode.

OP_mrc2 

ARM mrc2 opcode.

OP_mrrc 

ARM mrrc opcode.

OP_mrrc2 

ARM mrrc2 opcode.

OP_mrs 

ARM mrs opcode.

OP_mrs_priv 

ARM mrs_priv opcode.

OP_msr 

ARM msr opcode.

OP_msr_priv 

ARM msr_priv opcode.

OP_mul 

ARM mul opcode.

OP_muls 

ARM muls opcode.

OP_mvn 

ARM mvn opcode.

OP_mvns 

ARM mvns opcode.

OP_nop 

ARM nop opcode.

OP_orn 

ARM orn opcode.

OP_orns 

ARM orns opcode.

OP_orr 

ARM orr opcode.

OP_orrs 

ARM orrs opcode.

OP_pkhbt 

ARM pkhbt opcode.

OP_pkhtb 

ARM pkhtb opcode.

OP_pld 

ARM pld opcode.

OP_pldw 

ARM pldw opcode.

OP_pli 

ARM pli opcode.

OP_qadd 

ARM qadd opcode.

OP_qadd16 

ARM qadd16 opcode.

OP_qadd8 

ARM qadd8 opcode.

OP_qasx 

ARM qasx opcode.

OP_qdadd 

ARM qdadd opcode.

OP_qdsub 

ARM qdsub opcode.

OP_qsax 

ARM qsax opcode.

OP_qsub 

ARM qsub opcode.

OP_qsub16 

ARM qsub16 opcode.

OP_qsub8 

ARM qsub8 opcode.

OP_rbit 

ARM rbit opcode.

OP_rev 

ARM rev opcode.

OP_rev16 

ARM rev16 opcode.

OP_revsh 

ARM revsh opcode.

OP_rfe 

ARM rfe opcode.

OP_rfeda 

ARM rfeda opcode.

OP_rfedb 

ARM rfedb opcode.

OP_rfeib 

ARM rfeib opcode.

OP_ror 

ARM ror opcode.

OP_rors 

ARM rors opcode.

OP_rrx 

ARM rrx opcode.

OP_rrxs 

ARM rrxs opcode.

OP_rsb 

ARM rsb opcode.

OP_rsbs 

ARM rsbs opcode.

OP_rsc 

ARM rsc opcode.

OP_rscs 

ARM rscs opcode.

OP_sadd16 

ARM sadd16 opcode.

OP_sadd8 

ARM sadd8 opcode.

OP_sasx 

ARM sasx opcode.

OP_sbc 

ARM sbc opcode.

OP_sbcs 

ARM sbcs opcode.

OP_sbfx 

ARM sbfx opcode.

OP_sdiv 

ARM sdiv opcode.

OP_sel 

ARM sel opcode.

OP_setend 

ARM setend opcode.

OP_sev 

ARM sev opcode.

OP_sevl 

ARM sevl opcode.

OP_sha1c_32 

ARM sha1c_32 opcode.

OP_sha1h_32 

ARM sha1h_32 opcode.

OP_sha1m_32 

ARM sha1m_32 opcode.

OP_sha1p_32 

ARM sha1p_32 opcode.

OP_sha1su0_32 

ARM sha1su0_32 opcode.

OP_sha1su1_32 

ARM sha1su1_32 opcode.

OP_sha256h2_32 

ARM sha256h2_32 opcode.

OP_sha256h_32 

ARM sha256h_32 opcode.

OP_sha256su0_32 

ARM sha256su0_32 opcode.

OP_sha256su1_32 

ARM sha256su1_32 opcode.

OP_shadd16 

ARM shadd16 opcode.

OP_shadd8 

ARM shadd8 opcode.

OP_shasx 

ARM shasx opcode.

OP_shsax 

ARM shsax opcode.

OP_shsub16 

ARM shsub16 opcode.

OP_shsub8 

ARM shsub8 opcode.

OP_smc 

ARM smc opcode.

OP_smlabb 

ARM smlabb opcode.

OP_smlabt 

ARM smlabt opcode.

OP_smlad 

ARM smlad opcode.

OP_smladx 

ARM smladx opcode.

OP_smlal 

ARM smlal opcode.

OP_smlalbb 

ARM smlalbb opcode.

OP_smlalbt 

ARM smlalbt opcode.

OP_smlald 

ARM smlald opcode.

OP_smlaldx 

ARM smlaldx opcode.

OP_smlals 

ARM smlals opcode.

OP_smlaltb 

ARM smlaltb opcode.

OP_smlaltt 

ARM smlaltt opcode.

OP_smlatb 

ARM smlatb opcode.

OP_smlatt 

ARM smlatt opcode.

OP_smlawb 

ARM smlawb opcode.

OP_smlawt 

ARM smlawt opcode.

OP_smlsd 

ARM smlsd opcode.

OP_smlsdx 

ARM smlsdx opcode.

OP_smlsld 

ARM smlsld opcode.

OP_smlsldx 

ARM smlsldx opcode.

OP_smmla 

ARM smmla opcode.

OP_smmlar 

ARM smmlar opcode.

OP_smmls 

ARM smmls opcode.

OP_smmlsr 

ARM smmlsr opcode.

OP_smmul 

ARM smmul opcode.

OP_smmulr 

ARM smmulr opcode.

OP_smuad 

ARM smuad opcode.

OP_smuadx 

ARM smuadx opcode.

OP_smulbb 

ARM smulbb opcode.

OP_smulbt 

ARM smulbt opcode.

OP_smull 

ARM smull opcode.

OP_smulls 

ARM smulls opcode.

OP_smultb 

ARM smultb opcode.

OP_smultt 

ARM smultt opcode.

OP_smulwb 

ARM smulwb opcode.

OP_smulwt 

ARM smulwt opcode.

OP_smusd 

ARM smusd opcode.

OP_smusdx 

ARM smusdx opcode.

OP_srs 

ARM srs opcode.

OP_srsda 

ARM srsda opcode.

OP_srsdb 

ARM srsdb opcode.

OP_srsib 

ARM srsib opcode.

OP_ssat 

ARM ssat opcode.

OP_ssat16 

ARM ssat16 opcode.

OP_ssax 

ARM ssax opcode.

OP_ssub16 

ARM ssub16 opcode.

OP_ssub8 

ARM ssub8 opcode.

OP_stc 

ARM stc opcode.

OP_stc2 

ARM stc2 opcode.

OP_stc2l 

ARM stc2l opcode.

OP_stcl 

ARM stcl opcode.

OP_stl 

ARM stl opcode.

OP_stlb 

ARM stlb opcode.

OP_stlex 

ARM stlex opcode.

OP_stlexb 

ARM stlexb opcode.

OP_stlexd 

ARM stlexd opcode.

OP_stlexh 

ARM stlexh opcode.

OP_stlh 

ARM stlh opcode.

OP_stm 

ARM stm opcode.

OP_stm_priv 

ARM stm_priv opcode.

OP_stmda 

ARM stmda opcode.

OP_stmda_priv 

ARM stmda_priv opcode.

OP_stmdb 

ARM stmdb opcode.

OP_stmdb_priv 

ARM stmdb_priv opcode.

OP_stmib 

ARM stmib opcode.

OP_stmib_priv 

ARM stmib_priv opcode.

OP_str 

ARM str opcode.

OP_strb 

ARM strb opcode.

OP_strbt 

ARM strbt opcode.

OP_strd 

ARM strd opcode.

OP_strex 

ARM strex opcode.

OP_strexb 

ARM strexb opcode.

OP_strexd 

ARM strexd opcode.

OP_strexh 

ARM strexh opcode.

OP_strh 

ARM strh opcode.

OP_strht 

ARM strht opcode.

OP_strt 

ARM strt opcode.

OP_sub 

ARM sub opcode.

OP_subs 

ARM subs opcode.

OP_subw 

ARM subw opcode.

OP_svc 

ARM svc opcode.

OP_swp 

ARM swp opcode.

OP_swpb 

ARM swpb opcode.

OP_sxtab 

ARM sxtab opcode.

OP_sxtab16 

ARM sxtab16 opcode.

OP_sxtah 

ARM sxtah opcode.

OP_sxtb 

ARM sxtb opcode.

OP_sxtb16 

ARM sxtb16 opcode.

OP_sxth 

ARM sxth opcode.

OP_tbb 

ARM tbb opcode.

OP_tbh 

ARM tbh opcode.

OP_teq 

ARM teq opcode.

OP_tst 

ARM tst opcode.

OP_uadd16 

ARM uadd16 opcode.

OP_uadd8 

ARM uadd8 opcode.

OP_uasx 

ARM uasx opcode.

OP_ubfx 

ARM ubfx opcode.

OP_udf 

ARM udf opcode.

OP_udiv 

ARM udiv opcode.

OP_uhadd16 

ARM uhadd16 opcode.

OP_uhadd8 

ARM uhadd8 opcode.

OP_uhasx 

ARM uhasx opcode.

OP_uhsax 

ARM uhsax opcode.

OP_uhsub16 

ARM uhsub16 opcode.

OP_uhsub8 

ARM uhsub8 opcode.

OP_umaal 

ARM umaal opcode.

OP_umlal 

ARM umlal opcode.

OP_umlals 

ARM umlals opcode.

OP_umull 

ARM umull opcode.

OP_umulls 

ARM umulls opcode.

OP_uqadd16 

ARM uqadd16 opcode.

OP_uqadd8 

ARM uqadd8 opcode.

OP_uqasx 

ARM uqasx opcode.

OP_uqsax 

ARM uqsax opcode.

OP_uqsub16 

ARM uqsub16 opcode.

OP_uqsub8 

ARM uqsub8 opcode.

OP_usad8 

ARM usad8 opcode.

OP_usada8 

ARM usada8 opcode.

OP_usat 

ARM usat opcode.

OP_usat16 

ARM usat16 opcode.

OP_usax 

ARM usax opcode.

OP_usub16 

ARM usub16 opcode.

OP_usub8 

ARM usub8 opcode.

OP_uxtab 

ARM uxtab opcode.

OP_uxtab16 

ARM uxtab16 opcode.

OP_uxtah 

ARM uxtah opcode.

OP_uxtb 

ARM uxtb opcode.

OP_uxtb16 

ARM uxtb16 opcode.

OP_uxth 

ARM uxth opcode.

OP_vaba_s16 

ARM vaba_s16 opcode.

OP_vaba_s32 

ARM vaba_s32 opcode.

OP_vaba_s8 

ARM vaba_s8 opcode.

OP_vaba_u16 

ARM vaba_u16 opcode.

OP_vaba_u32 

ARM vaba_u32 opcode.

OP_vaba_u8 

ARM vaba_u8 opcode.

OP_vabal_s16 

ARM vabal_s16 opcode.

OP_vabal_s32 

ARM vabal_s32 opcode.

OP_vabal_s8 

ARM vabal_s8 opcode.

OP_vabal_u16 

ARM vabal_u16 opcode.

OP_vabal_u32 

ARM vabal_u32 opcode.

OP_vabal_u8 

ARM vabal_u8 opcode.

OP_vabd_s16 

ARM vabd_s16 opcode.

OP_vabd_s32 

ARM vabd_s32 opcode.

OP_vabd_s8 

ARM vabd_s8 opcode.

OP_vabd_u16 

ARM vabd_u16 opcode.

OP_vabd_u32 

ARM vabd_u32 opcode.

OP_vabd_u8 

ARM vabd_u8 opcode.

OP_vabdl_s16 

ARM vabdl_s16 opcode.

OP_vabdl_s32 

ARM vabdl_s32 opcode.

OP_vabdl_s8 

ARM vabdl_s8 opcode.

OP_vabdl_u16 

ARM vabdl_u16 opcode.

OP_vabdl_u32 

ARM vabdl_u32 opcode.

OP_vabdl_u8 

ARM vabdl_u8 opcode.

OP_vabs_f32 

ARM vabs_f32 opcode.

OP_vabs_f64 

ARM vabs_f64 opcode.

OP_vabs_s16 

ARM vabs_s16 opcode.

OP_vabs_s32 

ARM vabs_s32 opcode.

OP_vabs_s8 

ARM vabs_s8 opcode.

OP_vacge_f32 

ARM vacge_f32 opcode.

OP_vacgt_f32 

ARM vacgt_f32 opcode.

OP_vadd_f32 

ARM vadd_f32 opcode.

OP_vadd_f64 

ARM vadd_f64 opcode.

OP_vadd_i16 

ARM vadd_i16 opcode.

OP_vadd_i32 

ARM vadd_i32 opcode.

OP_vadd_i64 

ARM vadd_i64 opcode.

OP_vadd_i8 

ARM vadd_i8 opcode.

OP_vaddhn_i16 

ARM vaddhn_i16 opcode.

OP_vaddhn_i32 

ARM vaddhn_i32 opcode.

OP_vaddhn_i64 

ARM vaddhn_i64 opcode.

OP_vaddl_s16 

ARM vaddl_s16 opcode.

OP_vaddl_s32 

ARM vaddl_s32 opcode.

OP_vaddl_s8 

ARM vaddl_s8 opcode.

OP_vaddl_u16 

ARM vaddl_u16 opcode.

OP_vaddl_u32 

ARM vaddl_u32 opcode.

OP_vaddl_u8 

ARM vaddl_u8 opcode.

OP_vaddw_s16 

ARM vaddw_s16 opcode.

OP_vaddw_s32 

ARM vaddw_s32 opcode.

OP_vaddw_s8 

ARM vaddw_s8 opcode.

OP_vaddw_u16 

ARM vaddw_u16 opcode.

OP_vaddw_u32 

ARM vaddw_u32 opcode.

OP_vaddw_u8 

ARM vaddw_u8 opcode.

OP_vand 

ARM vand opcode.

OP_vbic 

ARM vbic opcode.

OP_vbic_i16 

ARM vbic_i16 opcode.

OP_vbic_i32 

ARM vbic_i32 opcode.

OP_vbif 

ARM vbif opcode.

OP_vbit 

ARM vbit opcode.

OP_vbsl 

ARM vbsl opcode.

OP_vceq_f32 

ARM vceq_f32 opcode.

OP_vceq_i16 

ARM vceq_i16 opcode.

OP_vceq_i32 

ARM vceq_i32 opcode.

OP_vceq_i8 

ARM vceq_i8 opcode.

OP_vcge_f32 

ARM vcge_f32 opcode.

OP_vcge_s16 

ARM vcge_s16 opcode.

OP_vcge_s32 

ARM vcge_s32 opcode.

OP_vcge_s8 

ARM vcge_s8 opcode.

OP_vcge_u16 

ARM vcge_u16 opcode.

OP_vcge_u32 

ARM vcge_u32 opcode.

OP_vcge_u8 

ARM vcge_u8 opcode.

OP_vcgt_f32 

ARM vcgt_f32 opcode.

OP_vcgt_s16 

ARM vcgt_s16 opcode.

OP_vcgt_s32 

ARM vcgt_s32 opcode.

OP_vcgt_s8 

ARM vcgt_s8 opcode.

OP_vcgt_u16 

ARM vcgt_u16 opcode.

OP_vcgt_u32 

ARM vcgt_u32 opcode.

OP_vcgt_u8 

ARM vcgt_u8 opcode.

OP_vcle_f32 

ARM vcle_f32 opcode.

OP_vcle_s16 

ARM vcle_s16 opcode.

OP_vcle_s32 

ARM vcle_s32 opcode.

OP_vcle_s8 

ARM vcle_s8 opcode.

OP_vcls_s16 

ARM vcls_s16 opcode.

OP_vcls_s32 

ARM vcls_s32 opcode.

OP_vcls_s8 

ARM vcls_s8 opcode.

OP_vclt_f32 

ARM vclt_f32 opcode.

OP_vclt_s16 

ARM vclt_s16 opcode.

OP_vclt_s32 

ARM vclt_s32 opcode.

OP_vclt_s8 

ARM vclt_s8 opcode.

OP_vclz_i16 

ARM vclz_i16 opcode.

OP_vclz_i32 

ARM vclz_i32 opcode.

OP_vclz_i8 

ARM vclz_i8 opcode.

OP_vcmp_f32 

ARM vcmp_f32 opcode.

OP_vcmp_f64 

ARM vcmp_f64 opcode.

OP_vcmpe_f32 

ARM vcmpe_f32 opcode.

OP_vcmpe_f64 

ARM vcmpe_f64 opcode.

OP_vcnt_8 

ARM vcnt_8 opcode.

OP_vcvt_f16_f32 

ARM vcvt_f16_f32 opcode.

OP_vcvt_f32_f16 

ARM vcvt_f32_f16 opcode.

OP_vcvt_f32_f64 

ARM vcvt_f32_f64 opcode.

OP_vcvt_f32_s16 

ARM vcvt_f32_s16 opcode.

OP_vcvt_f32_s32 

ARM vcvt_f32_s32 opcode.

OP_vcvt_f32_u16 

ARM vcvt_f32_u16 opcode.

OP_vcvt_f32_u32 

ARM vcvt_f32_u32 opcode.

OP_vcvt_f64_f32 

ARM vcvt_f64_f32 opcode.

OP_vcvt_f64_s16 

ARM vcvt_f64_s16 opcode.

OP_vcvt_f64_s32 

ARM vcvt_f64_s32 opcode.

OP_vcvt_f64_u16 

ARM vcvt_f64_u16 opcode.

OP_vcvt_f64_u32 

ARM vcvt_f64_u32 opcode.

OP_vcvt_s16_f32 

ARM vcvt_s16_f32 opcode.

OP_vcvt_s16_f64 

ARM vcvt_s16_f64 opcode.

OP_vcvt_s32_f32 

ARM vcvt_s32_f32 opcode.

OP_vcvt_s32_f64 

ARM vcvt_s32_f64 opcode.

OP_vcvt_u16_f32 

ARM vcvt_u16_f32 opcode.

OP_vcvt_u16_f64 

ARM vcvt_u16_f64 opcode.

OP_vcvt_u32_f32 

ARM vcvt_u32_f32 opcode.

OP_vcvt_u32_f64 

ARM vcvt_u32_f64 opcode.

OP_vcvta_s32_f32 

ARM vcvta_s32_f32 opcode.

OP_vcvta_s32_f64 

ARM vcvta_s32_f64 opcode.

OP_vcvta_u32_f32 

ARM vcvta_u32_f32 opcode.

OP_vcvta_u32_f64 

ARM vcvta_u32_f64 opcode.

OP_vcvtb_f16_f32 

ARM vcvtb_f16_f32 opcode.

OP_vcvtb_f16_f64 

ARM vcvtb_f16_f64 opcode.

OP_vcvtb_f32_f16 

ARM vcvtb_f32_f16 opcode.

OP_vcvtb_f64_f16 

ARM vcvtb_f64_f16 opcode.

OP_vcvtm_s32_f32 

ARM vcvtm_s32_f32 opcode.

OP_vcvtm_s32_f64 

ARM vcvtm_s32_f64 opcode.

OP_vcvtm_u32_f32 

ARM vcvtm_u32_f32 opcode.

OP_vcvtm_u32_f64 

ARM vcvtm_u32_f64 opcode.

OP_vcvtn_s32_f32 

ARM vcvtn_s32_f32 opcode.

OP_vcvtn_s32_f64 

ARM vcvtn_s32_f64 opcode.

OP_vcvtn_u32_f32 

ARM vcvtn_u32_f32 opcode.

OP_vcvtn_u32_f64 

ARM vcvtn_u32_f64 opcode.

OP_vcvtp_s32_f32 

ARM vcvtp_s32_f32 opcode.

OP_vcvtp_s32_f64 

ARM vcvtp_s32_f64 opcode.

OP_vcvtp_u32_f32 

ARM vcvtp_u32_f32 opcode.

OP_vcvtp_u32_f64 

ARM vcvtp_u32_f64 opcode.

OP_vcvtr_s32_f32 

ARM vcvtr_s32_f32 opcode.

OP_vcvtr_s32_f64 

ARM vcvtr_s32_f64 opcode.

OP_vcvtr_u32_f32 

ARM vcvtr_u32_f32 opcode.

OP_vcvtr_u32_f64 

ARM vcvtr_u32_f64 opcode.

OP_vcvtt_f16_f32 

ARM vcvtt_f16_f32 opcode.

OP_vcvtt_f16_f64 

ARM vcvtt_f16_f64 opcode.

OP_vcvtt_f32_f16 

ARM vcvtt_f32_f16 opcode.

OP_vcvtt_f64_f16 

ARM vcvtt_f64_f16 opcode.

OP_vdiv_f32 

ARM vdiv_f32 opcode.

OP_vdiv_f64 

ARM vdiv_f64 opcode.

OP_vdup_16 

ARM vdup_16 opcode.

OP_vdup_32 

ARM vdup_32 opcode.

OP_vdup_8 

ARM vdup_8 opcode.

OP_veor 

ARM veor opcode.

OP_vext 

ARM vext opcode.

OP_vfma_f32 

ARM vfma_f32 opcode.

OP_vfma_f64 

ARM vfma_f64 opcode.

OP_vfms_f32 

ARM vfms_f32 opcode.

OP_vfms_f64 

ARM vfms_f64 opcode.

OP_vfnma_f32 

ARM vfnma_f32 opcode.

OP_vfnma_f64 

ARM vfnma_f64 opcode.

OP_vfnms_f32 

ARM vfnms_f32 opcode.

OP_vfnms_f64 

ARM vfnms_f64 opcode.

OP_vhadd_s16 

ARM vhadd_s16 opcode.

OP_vhadd_s32 

ARM vhadd_s32 opcode.

OP_vhadd_s8 

ARM vhadd_s8 opcode.

OP_vhadd_u16 

ARM vhadd_u16 opcode.

OP_vhadd_u32 

ARM vhadd_u32 opcode.

OP_vhadd_u8 

ARM vhadd_u8 opcode.

OP_vhsub_s16 

ARM vhsub_s16 opcode.

OP_vhsub_s32 

ARM vhsub_s32 opcode.

OP_vhsub_s8 

ARM vhsub_s8 opcode.

OP_vhsub_u16 

ARM vhsub_u16 opcode.

OP_vhsub_u32 

ARM vhsub_u32 opcode.

OP_vhsub_u8 

ARM vhsub_u8 opcode.

OP_vld1_16 

ARM vld1_16 opcode.

OP_vld1_32 

ARM vld1_32 opcode.

OP_vld1_64 

ARM vld1_64 opcode.

OP_vld1_8 

ARM vld1_8 opcode.

OP_vld1_dup_16 

ARM vld1_dup_16 opcode.

OP_vld1_dup_32 

ARM vld1_dup_32 opcode.

OP_vld1_dup_8 

ARM vld1_dup_8 opcode.

OP_vld1_lane_16 

ARM vld1_lane_16 opcode.

OP_vld1_lane_32 

ARM vld1_lane_32 opcode.

OP_vld1_lane_8 

ARM vld1_lane_8 opcode.

OP_vld2_16 

ARM vld2_16 opcode.

OP_vld2_32 

ARM vld2_32 opcode.

OP_vld2_8 

ARM vld2_8 opcode.

OP_vld2_dup_16 

ARM vld2_dup_16 opcode.

OP_vld2_dup_32 

ARM vld2_dup_32 opcode.

OP_vld2_dup_8 

ARM vld2_dup_8 opcode.

OP_vld2_lane_16 

ARM vld2_lane_16 opcode.

OP_vld2_lane_32 

ARM vld2_lane_32 opcode.

OP_vld2_lane_8 

ARM vld2_lane_8 opcode.

OP_vld3_16 

ARM vld3_16 opcode.

OP_vld3_32 

ARM vld3_32 opcode.

OP_vld3_8 

ARM vld3_8 opcode.

OP_vld3_dup_16 

ARM vld3_dup_16 opcode.

OP_vld3_dup_32 

ARM vld3_dup_32 opcode.

OP_vld3_dup_8 

ARM vld3_dup_8 opcode.

OP_vld3_lane_16 

ARM vld3_lane_16 opcode.

OP_vld3_lane_32 

ARM vld3_lane_32 opcode.

OP_vld3_lane_8 

ARM vld3_lane_8 opcode.

OP_vld4_16 

ARM vld4_16 opcode.

OP_vld4_32 

ARM vld4_32 opcode.

OP_vld4_8 

ARM vld4_8 opcode.

OP_vld4_dup_16 

ARM vld4_dup_16 opcode.

OP_vld4_dup_32 

ARM vld4_dup_32 opcode.

OP_vld4_dup_8 

ARM vld4_dup_8 opcode.

OP_vld4_lane_16 

ARM vld4_lane_16 opcode.

OP_vld4_lane_32 

ARM vld4_lane_32 opcode.

OP_vld4_lane_8 

ARM vld4_lane_8 opcode.

OP_vldm 

ARM vldm opcode.

OP_vldmdb 

ARM vldmdb opcode.

OP_vldr 

ARM vldr opcode.

OP_vmax_f32 

ARM vmax_f32 opcode.

OP_vmax_s16 

ARM vmax_s16 opcode.

OP_vmax_s32 

ARM vmax_s32 opcode.

OP_vmax_s8 

ARM vmax_s8 opcode.

OP_vmax_u16 

ARM vmax_u16 opcode.

OP_vmax_u32 

ARM vmax_u32 opcode.

OP_vmax_u8 

ARM vmax_u8 opcode.

OP_vmaxnm_f32 

ARM vmaxnm_f32 opcode.

OP_vmaxnm_f64 

ARM vmaxnm_f64 opcode.

OP_vmin_f32 

ARM vmin_f32 opcode.

OP_vmin_s16 

ARM vmin_s16 opcode.

OP_vmin_s32 

ARM vmin_s32 opcode.

OP_vmin_s8 

ARM vmin_s8 opcode.

OP_vmin_u16 

ARM vmin_u16 opcode.

OP_vmin_u32 

ARM vmin_u32 opcode.

OP_vmin_u8 

ARM vmin_u8 opcode.

OP_vminnm_f32 

ARM vminnm_f32 opcode.

OP_vminnm_f64 

ARM vminnm_f64 opcode.

OP_vmla_f32 

ARM vmla_f32 opcode.

OP_vmla_f64 

ARM vmla_f64 opcode.

OP_vmla_i16 

ARM vmla_i16 opcode.

OP_vmla_i32 

ARM vmla_i32 opcode.

OP_vmla_i8 

ARM vmla_i8 opcode.

OP_vmlal_s16 

ARM vmlal_s16 opcode.

OP_vmlal_s32 

ARM vmlal_s32 opcode.

OP_vmlal_s8 

ARM vmlal_s8 opcode.

OP_vmlal_u16 

ARM vmlal_u16 opcode.

OP_vmlal_u32 

ARM vmlal_u32 opcode.

OP_vmlal_u8 

ARM vmlal_u8 opcode.

OP_vmls_f32 

ARM vmls_f32 opcode.

OP_vmls_f64 

ARM vmls_f64 opcode.

OP_vmls_i16 

ARM vmls_i16 opcode.

OP_vmls_i32 

ARM vmls_i32 opcode.

OP_vmls_i8 

ARM vmls_i8 opcode.

OP_vmlsl_s16 

ARM vmlsl_s16 opcode.

OP_vmlsl_s32 

ARM vmlsl_s32 opcode.

OP_vmlsl_s8 

ARM vmlsl_s8 opcode.

OP_vmlsl_u16 

ARM vmlsl_u16 opcode.

OP_vmlsl_u32 

ARM vmlsl_u32 opcode.

OP_vmlsl_u8 

ARM vmlsl_u8 opcode.

OP_vmov 

ARM vmov opcode.

OP_vmov_16 

ARM vmov_16 opcode.

OP_vmov_32 

ARM vmov_32 opcode.

OP_vmov_8 

ARM vmov_8 opcode.

OP_vmov_f32 

ARM vmov_f32 opcode.

OP_vmov_f64 

ARM vmov_f64 opcode.

OP_vmov_i16 

ARM vmov_i16 opcode.

OP_vmov_i32 

ARM vmov_i32 opcode.

OP_vmov_i64 

ARM vmov_i64 opcode.

OP_vmov_i8 

ARM vmov_i8 opcode.

OP_vmov_s16 

ARM vmov_s16 opcode.

OP_vmov_s8 

ARM vmov_s8 opcode.

OP_vmov_u16 

ARM vmov_u16 opcode.

OP_vmov_u8 

ARM vmov_u8 opcode.

OP_vmovl_s16 

ARM vmovl_s16 opcode.

OP_vmovl_s32 

ARM vmovl_s32 opcode.

OP_vmovl_s8 

ARM vmovl_s8 opcode.

OP_vmovl_u16 

ARM vmovl_u16 opcode.

OP_vmovl_u32 

ARM vmovl_u32 opcode.

OP_vmovl_u8 

ARM vmovl_u8 opcode.

OP_vmovn_i16 

ARM vmovn_i16 opcode.

OP_vmovn_i32 

ARM vmovn_i32 opcode.

OP_vmovn_i64 

ARM vmovn_i64 opcode.

OP_vmrs 

ARM vmrs opcode.

OP_vmsr 

ARM vmsr opcode.

OP_vmul_f32 

ARM vmul_f32 opcode.

OP_vmul_f64 

ARM vmul_f64 opcode.

OP_vmul_i16 

ARM vmul_i16 opcode.

OP_vmul_i32 

ARM vmul_i32 opcode.

OP_vmul_i8 

ARM vmul_i8 opcode.

OP_vmul_p32 

ARM vmul_p32 opcode.

OP_vmul_p8 

ARM vmul_p8 opcode.

OP_vmull_p32 

ARM vmull_p32 opcode.

OP_vmull_p8 

ARM vmull_p8 opcode.

OP_vmull_s16 

ARM vmull_s16 opcode.

OP_vmull_s32 

ARM vmull_s32 opcode.

OP_vmull_s8 

ARM vmull_s8 opcode.

OP_vmull_u16 

ARM vmull_u16 opcode.

OP_vmull_u32 

ARM vmull_u32 opcode.

OP_vmull_u8 

ARM vmull_u8 opcode.

OP_vmvn 

ARM vmvn opcode.

OP_vmvn_i16 

ARM vmvn_i16 opcode.

OP_vmvn_i32 

ARM vmvn_i32 opcode.

OP_vneg_f32 

ARM vneg_f32 opcode.

OP_vneg_f64 

ARM vneg_f64 opcode.

OP_vneg_s16 

ARM vneg_s16 opcode.

OP_vneg_s32 

ARM vneg_s32 opcode.

OP_vneg_s8 

ARM vneg_s8 opcode.

OP_vnmla_f32 

ARM vnmla_f32 opcode.

OP_vnmla_f64 

ARM vnmla_f64 opcode.

OP_vnmls_f32 

ARM vnmls_f32 opcode.

OP_vnmls_f64 

ARM vnmls_f64 opcode.

OP_vnmul_f32 

ARM vnmul_f32 opcode.

OP_vnmul_f64 

ARM vnmul_f64 opcode.

OP_vorn 

ARM vorn opcode.

OP_vorr 

ARM vorr opcode.

OP_vorr_i16 

ARM vorr_i16 opcode.

OP_vorr_i32 

ARM vorr_i32 opcode.

OP_vpadal_s16 

ARM vpadal_s16 opcode.

OP_vpadal_s32 

ARM vpadal_s32 opcode.

OP_vpadal_s8 

ARM vpadal_s8 opcode.

OP_vpadal_u16 

ARM vpadal_u16 opcode.

OP_vpadal_u32 

ARM vpadal_u32 opcode.

OP_vpadal_u8 

ARM vpadal_u8 opcode.

OP_vpadd_f32 

ARM vpadd_f32 opcode.

OP_vpadd_i16 

ARM vpadd_i16 opcode.

OP_vpadd_i32 

ARM vpadd_i32 opcode.

OP_vpadd_i8 

ARM vpadd_i8 opcode.

OP_vpaddl_s16 

ARM vpaddl_s16 opcode.

OP_vpaddl_s32 

ARM vpaddl_s32 opcode.

OP_vpaddl_s8 

ARM vpaddl_s8 opcode.

OP_vpaddl_u16 

ARM vpaddl_u16 opcode.

OP_vpaddl_u32 

ARM vpaddl_u32 opcode.

OP_vpaddl_u8 

ARM vpaddl_u8 opcode.

OP_vpmax_f32 

ARM vpmax_f32 opcode.

OP_vpmax_s16 

ARM vpmax_s16 opcode.

OP_vpmax_s32 

ARM vpmax_s32 opcode.

OP_vpmax_s8 

ARM vpmax_s8 opcode.

OP_vpmax_u16 

ARM vpmax_u16 opcode.

OP_vpmax_u32 

ARM vpmax_u32 opcode.

OP_vpmax_u8 

ARM vpmax_u8 opcode.

OP_vpmin_f32 

ARM vpmin_f32 opcode.

OP_vpmin_s16 

ARM vpmin_s16 opcode.

OP_vpmin_s32 

ARM vpmin_s32 opcode.

OP_vpmin_s8 

ARM vpmin_s8 opcode.

OP_vpmin_u16 

ARM vpmin_u16 opcode.

OP_vpmin_u32 

ARM vpmin_u32 opcode.

OP_vpmin_u8 

ARM vpmin_u8 opcode.

OP_vqabs_s16 

ARM vqabs_s16 opcode.

OP_vqabs_s32 

ARM vqabs_s32 opcode.

OP_vqabs_s8 

ARM vqabs_s8 opcode.

OP_vqadd_s16 

ARM vqadd_s16 opcode.

OP_vqadd_s32 

ARM vqadd_s32 opcode.

OP_vqadd_s64 

ARM vqadd_s64 opcode.

OP_vqadd_s8 

ARM vqadd_s8 opcode.

OP_vqadd_u16 

ARM vqadd_u16 opcode.

OP_vqadd_u32 

ARM vqadd_u32 opcode.

OP_vqadd_u64 

ARM vqadd_u64 opcode.

OP_vqadd_u8 

ARM vqadd_u8 opcode.

OP_vqdmlal_s16 

ARM vqdmlal_s16 opcode.

OP_vqdmlal_s32 

ARM vqdmlal_s32 opcode.

OP_vqdmlsl_s16 

ARM vqdmlsl_s16 opcode.

OP_vqdmlsl_s32 

ARM vqdmlsl_s32 opcode.

OP_vqdmulh_s16 

ARM vqdmulh_s16 opcode.

OP_vqdmulh_s32 

ARM vqdmulh_s32 opcode.

OP_vqdmull_s16 

ARM vqdmull_s16 opcode.

OP_vqdmull_s32 

ARM vqdmull_s32 opcode.

OP_vqmovn_s16 

ARM vqmovn_s16 opcode.

OP_vqmovn_s32 

ARM vqmovn_s32 opcode.

OP_vqmovn_s64 

ARM vqmovn_s64 opcode.

OP_vqmovn_u16 

ARM vqmovn_u16 opcode.

OP_vqmovn_u32 

ARM vqmovn_u32 opcode.

OP_vqmovn_u64 

ARM vqmovn_u64 opcode.

OP_vqmovun_s16 

ARM vqmovun_s16 opcode.

OP_vqmovun_s32 

ARM vqmovun_s32 opcode.

OP_vqmovun_s64 

ARM vqmovun_s64 opcode.

OP_vqneg_s16 

ARM vqneg_s16 opcode.

OP_vqneg_s32 

ARM vqneg_s32 opcode.

OP_vqneg_s8 

ARM vqneg_s8 opcode.

OP_vqrdmulh_s16 

ARM vqrdmulh_s16 opcode.

OP_vqrdmulh_s32 

ARM vqrdmulh_s32 opcode.

OP_vqrshl_s16 

ARM vqrshl_s16 opcode.

OP_vqrshl_s32 

ARM vqrshl_s32 opcode.

OP_vqrshl_s64 

ARM vqrshl_s64 opcode.

OP_vqrshl_s8 

ARM vqrshl_s8 opcode.

OP_vqrshl_u16 

ARM vqrshl_u16 opcode.

OP_vqrshl_u32 

ARM vqrshl_u32 opcode.

OP_vqrshl_u64 

ARM vqrshl_u64 opcode.

OP_vqrshl_u8 

ARM vqrshl_u8 opcode.

OP_vqrshrn_s16 

ARM vqrshrn_s16 opcode.

OP_vqrshrn_s32 

ARM vqrshrn_s32 opcode.

OP_vqrshrn_s64 

ARM vqrshrn_s64 opcode.

OP_vqrshrn_u16 

ARM vqrshrn_u16 opcode.

OP_vqrshrn_u32 

ARM vqrshrn_u32 opcode.

OP_vqrshrn_u64 

ARM vqrshrn_u64 opcode.

OP_vqrshrun_s16 

ARM vqrshrun_s16 opcode.

OP_vqrshrun_s32 

ARM vqrshrun_s32 opcode.

OP_vqrshrun_s64 

ARM vqrshrun_s64 opcode.

OP_vqshl_s16 

ARM vqshl_s16 opcode.

OP_vqshl_s32 

ARM vqshl_s32 opcode.

OP_vqshl_s64 

ARM vqshl_s64 opcode.

OP_vqshl_s8 

ARM vqshl_s8 opcode.

OP_vqshl_u16 

ARM vqshl_u16 opcode.

OP_vqshl_u32 

ARM vqshl_u32 opcode.

OP_vqshl_u64 

ARM vqshl_u64 opcode.

OP_vqshl_u8 

ARM vqshl_u8 opcode.

OP_vqshlu_s16 

ARM vqshlu_s16 opcode.

OP_vqshlu_s32 

ARM vqshlu_s32 opcode.

OP_vqshlu_s64 

ARM vqshlu_s64 opcode.

OP_vqshlu_s8 

ARM vqshlu_s8 opcode.

OP_vqshrn_s16 

ARM vqshrn_s16 opcode.

OP_vqshrn_s32 

ARM vqshrn_s32 opcode.

OP_vqshrn_s64 

ARM vqshrn_s64 opcode.

OP_vqshrn_u16 

ARM vqshrn_u16 opcode.

OP_vqshrn_u32 

ARM vqshrn_u32 opcode.

OP_vqshrn_u64 

ARM vqshrn_u64 opcode.

OP_vqshrun_s16 

ARM vqshrun_s16 opcode.

OP_vqshrun_s32 

ARM vqshrun_s32 opcode.

OP_vqshrun_s64 

ARM vqshrun_s64 opcode.

OP_vqsub_s16 

ARM vqsub_s16 opcode.

OP_vqsub_s32 

ARM vqsub_s32 opcode.

OP_vqsub_s64 

ARM vqsub_s64 opcode.

OP_vqsub_s8 

ARM vqsub_s8 opcode.

OP_vqsub_u16 

ARM vqsub_u16 opcode.

OP_vqsub_u32 

ARM vqsub_u32 opcode.

OP_vqsub_u64 

ARM vqsub_u64 opcode.

OP_vqsub_u8 

ARM vqsub_u8 opcode.

OP_vraddhn_i16 

ARM vraddhn_i16 opcode.

OP_vraddhn_i32 

ARM vraddhn_i32 opcode.

OP_vraddhn_i64 

ARM vraddhn_i64 opcode.

OP_vrecpe_f32 

ARM vrecpe_f32 opcode.

OP_vrecpe_u32 

ARM vrecpe_u32 opcode.

OP_vrecps_f32 

ARM vrecps_f32 opcode.

OP_vrev16_16 

ARM vrev16_16 opcode.

OP_vrev16_8 

ARM vrev16_8 opcode.

OP_vrev32_16 

ARM vrev32_16 opcode.

OP_vrev32_32 

ARM vrev32_32 opcode.

OP_vrev32_8 

ARM vrev32_8 opcode.

OP_vrev64_16 

ARM vrev64_16 opcode.

OP_vrev64_32 

ARM vrev64_32 opcode.

OP_vrev64_8 

ARM vrev64_8 opcode.

OP_vrhadd_s16 

ARM vrhadd_s16 opcode.

OP_vrhadd_s32 

ARM vrhadd_s32 opcode.

OP_vrhadd_s8 

ARM vrhadd_s8 opcode.

OP_vrhadd_u16 

ARM vrhadd_u16 opcode.

OP_vrhadd_u32 

ARM vrhadd_u32 opcode.

OP_vrhadd_u8 

ARM vrhadd_u8 opcode.

OP_vrinta_f32_f32 

ARM vrinta_f32_f32 opcode.

OP_vrinta_f64_f64 

ARM vrinta_f64_f64 opcode.

OP_vrintm_f32_f32 

ARM vrintm_f32_f32 opcode.

OP_vrintm_f64_f64 

ARM vrintm_f64_f64 opcode.

OP_vrintn_f32_f32 

ARM vrintn_f32_f32 opcode.

OP_vrintn_f64_f64 

ARM vrintn_f64_f64 opcode.

OP_vrintp_f32_f32 

ARM vrintp_f32_f32 opcode.

OP_vrintp_f64_f64 

ARM vrintp_f64_f64 opcode.

OP_vrintr_f32 

ARM vrintr_f32 opcode.

OP_vrintr_f64 

ARM vrintr_f64 opcode.

OP_vrintx_f32 

ARM vrintx_f32 opcode.

OP_vrintx_f32_f32 

ARM vrintx_f32_f32 opcode.

OP_vrintx_f64 

ARM vrintx_f64 opcode.

OP_vrintz_f32 

ARM vrintz_f32 opcode.

OP_vrintz_f32_f32 

ARM vrintz_f32_f32 opcode.

OP_vrintz_f64 

ARM vrintz_f64 opcode.

OP_vrshl_s16 

ARM vrshl_s16 opcode.

OP_vrshl_s32 

ARM vrshl_s32 opcode.

OP_vrshl_s64 

ARM vrshl_s64 opcode.

OP_vrshl_s8 

ARM vrshl_s8 opcode.

OP_vrshl_u16 

ARM vrshl_u16 opcode.

OP_vrshl_u32 

ARM vrshl_u32 opcode.

OP_vrshl_u64 

ARM vrshl_u64 opcode.

OP_vrshl_u8 

ARM vrshl_u8 opcode.

OP_vrshr_s16 

ARM vrshr_s16 opcode.

OP_vrshr_s32 

ARM vrshr_s32 opcode.

OP_vrshr_s64 

ARM vrshr_s64 opcode.

OP_vrshr_s8 

ARM vrshr_s8 opcode.

OP_vrshr_u16 

ARM vrshr_u16 opcode.

OP_vrshr_u32 

ARM vrshr_u32 opcode.

OP_vrshr_u64 

ARM vrshr_u64 opcode.

OP_vrshr_u8 

ARM vrshr_u8 opcode.

OP_vrshrn_i16 

ARM vrshrn_i16 opcode.

OP_vrshrn_i32 

ARM vrshrn_i32 opcode.

OP_vrshrn_i64 

ARM vrshrn_i64 opcode.

OP_vrsqrte_f32 

ARM vrsqrte_f32 opcode.

OP_vrsqrte_u32 

ARM vrsqrte_u32 opcode.

OP_vrsqrts_f32 

ARM vrsqrts_f32 opcode.

OP_vrsra_s16 

ARM vrsra_s16 opcode.

OP_vrsra_s32 

ARM vrsra_s32 opcode.

OP_vrsra_s64 

ARM vrsra_s64 opcode.

OP_vrsra_s8 

ARM vrsra_s8 opcode.

OP_vrsra_u16 

ARM vrsra_u16 opcode.

OP_vrsra_u32 

ARM vrsra_u32 opcode.

OP_vrsra_u64 

ARM vrsra_u64 opcode.

OP_vrsra_u8 

ARM vrsra_u8 opcode.

OP_vrsubhn_i16 

ARM vrsubhn_i16 opcode.

OP_vrsubhn_i32 

ARM vrsubhn_i32 opcode.

OP_vrsubhn_i64 

ARM vrsubhn_i64 opcode.

OP_vsel_eq_f32 

ARM vsel_eq_f32 opcode.

OP_vsel_eq_f64 

ARM vsel_eq_f64 opcode.

OP_vsel_ge_f32 

ARM vsel_ge_f32 opcode.

OP_vsel_ge_f64 

ARM vsel_ge_f64 opcode.

OP_vsel_gt_f32 

ARM vsel_gt_f32 opcode.

OP_vsel_gt_f64 

ARM vsel_gt_f64 opcode.

OP_vsel_vs_f32 

ARM vsel_vs_f32 opcode.

OP_vsel_vs_f64 

ARM vsel_vs_f64 opcode.

OP_vshl_i16 

ARM vshl_i16 opcode.

OP_vshl_i32 

ARM vshl_i32 opcode.

OP_vshl_i64 

ARM vshl_i64 opcode.

OP_vshl_i8 

ARM vshl_i8 opcode.

OP_vshl_s16 

ARM vshl_s16 opcode.

OP_vshl_s32 

ARM vshl_s32 opcode.

OP_vshl_s64 

ARM vshl_s64 opcode.

OP_vshl_s8 

ARM vshl_s8 opcode.

OP_vshl_u16 

ARM vshl_u16 opcode.

OP_vshl_u32 

ARM vshl_u32 opcode.

OP_vshl_u64 

ARM vshl_u64 opcode.

OP_vshl_u8 

ARM vshl_u8 opcode.

OP_vshll_i16 

ARM vshll_i16 opcode.

OP_vshll_i32 

ARM vshll_i32 opcode.

OP_vshll_i8 

ARM vshll_i8 opcode.

OP_vshll_s16 

ARM vshll_s16 opcode.

OP_vshll_s32 

ARM vshll_s32 opcode.

OP_vshll_s8 

ARM vshll_s8 opcode.

OP_vshll_u16 

ARM vshll_u16 opcode.

OP_vshll_u32 

ARM vshll_u32 opcode.

OP_vshll_u8 

ARM vshll_u8 opcode.

OP_vshr_s16 

ARM vshr_s16 opcode.

OP_vshr_s32 

ARM vshr_s32 opcode.

OP_vshr_s64 

ARM vshr_s64 opcode.

OP_vshr_s8 

ARM vshr_s8 opcode.

OP_vshr_u16 

ARM vshr_u16 opcode.

OP_vshr_u32 

ARM vshr_u32 opcode.

OP_vshr_u64 

ARM vshr_u64 opcode.

OP_vshr_u8 

ARM vshr_u8 opcode.

OP_vshrn_i16 

ARM vshrn_i16 opcode.

OP_vshrn_i32 

ARM vshrn_i32 opcode.

OP_vshrn_i64 

ARM vshrn_i64 opcode.

OP_vsli_16 

ARM vsli_16 opcode.

OP_vsli_32 

ARM vsli_32 opcode.

OP_vsli_64 

ARM vsli_64 opcode.

OP_vsli_8 

ARM vsli_8 opcode.

OP_vsqrt_f32 

ARM vsqrt_f32 opcode.

OP_vsqrt_f64 

ARM vsqrt_f64 opcode.

OP_vsra_s16 

ARM vsra_s16 opcode.

OP_vsra_s32 

ARM vsra_s32 opcode.

OP_vsra_s64 

ARM vsra_s64 opcode.

OP_vsra_s8 

ARM vsra_s8 opcode.

OP_vsra_u16 

ARM vsra_u16 opcode.

OP_vsra_u32 

ARM vsra_u32 opcode.

OP_vsra_u64 

ARM vsra_u64 opcode.

OP_vsra_u8 

ARM vsra_u8 opcode.

OP_vsri_16 

ARM vsri_16 opcode.

OP_vsri_32 

ARM vsri_32 opcode.

OP_vsri_64 

ARM vsri_64 opcode.

OP_vsri_8 

ARM vsri_8 opcode.

OP_vst1_16 

ARM vst1_16 opcode.

OP_vst1_32 

ARM vst1_32 opcode.

OP_vst1_64 

ARM vst1_64 opcode.

OP_vst1_8 

ARM vst1_8 opcode.

OP_vst1_lane_16 

ARM vst1_lane_16 opcode.

OP_vst1_lane_32 

ARM vst1_lane_32 opcode.

OP_vst1_lane_8 

ARM vst1_lane_8 opcode.

OP_vst2_16 

ARM vst2_16 opcode.

OP_vst2_32 

ARM vst2_32 opcode.

OP_vst2_8 

ARM vst2_8 opcode.

OP_vst2_lane_16 

ARM vst2_lane_16 opcode.

OP_vst2_lane_32 

ARM vst2_lane_32 opcode.

OP_vst2_lane_8 

ARM vst2_lane_8 opcode.

OP_vst3_16 

ARM vst3_16 opcode.

OP_vst3_32 

ARM vst3_32 opcode.

OP_vst3_8 

ARM vst3_8 opcode.

OP_vst3_lane_16 

ARM vst3_lane_16 opcode.

OP_vst3_lane_32 

ARM vst3_lane_32 opcode.

OP_vst3_lane_8 

ARM vst3_lane_8 opcode.

OP_vst4_16 

ARM vst4_16 opcode.

OP_vst4_32 

ARM vst4_32 opcode.

OP_vst4_8 

ARM vst4_8 opcode.

OP_vst4_lane_16 

ARM vst4_lane_16 opcode.

OP_vst4_lane_32 

ARM vst4_lane_32 opcode.

OP_vst4_lane_8 

ARM vst4_lane_8 opcode.

OP_vstm 

ARM vstm opcode.

OP_vstmdb 

ARM vstmdb opcode.

OP_vstr 

ARM vstr opcode.

OP_vsub_f32 

ARM vsub_f32 opcode.

OP_vsub_f64 

ARM vsub_f64 opcode.

OP_vsub_i16 

ARM vsub_i16 opcode.

OP_vsub_i32 

ARM vsub_i32 opcode.

OP_vsub_i64 

ARM vsub_i64 opcode.

OP_vsub_i8 

ARM vsub_i8 opcode.

OP_vsubhn_i16 

ARM vsubhn_i16 opcode.

OP_vsubhn_i32 

ARM vsubhn_i32 opcode.

OP_vsubhn_i64 

ARM vsubhn_i64 opcode.

OP_vsubl_s16 

ARM vsubl_s16 opcode.

OP_vsubl_s32 

ARM vsubl_s32 opcode.

OP_vsubl_s8 

ARM vsubl_s8 opcode.

OP_vsubl_u16 

ARM vsubl_u16 opcode.

OP_vsubl_u32 

ARM vsubl_u32 opcode.

OP_vsubl_u8 

ARM vsubl_u8 opcode.

OP_vsubw_s16 

ARM vsubw_s16 opcode.

OP_vsubw_s32 

ARM vsubw_s32 opcode.

OP_vsubw_s8 

ARM vsubw_s8 opcode.

OP_vsubw_u16 

ARM vsubw_u16 opcode.

OP_vsubw_u32 

ARM vsubw_u32 opcode.

OP_vsubw_u8 

ARM vsubw_u8 opcode.

OP_vswp 

ARM vswp opcode.

OP_vtbl_8 

ARM vtbl_8 opcode.

OP_vtbx_8 

ARM vtbx_8 opcode.

OP_vtrn_16 

ARM vtrn_16 opcode.

OP_vtrn_32 

ARM vtrn_32 opcode.

OP_vtrn_8 

ARM vtrn_8 opcode.

OP_vtst_16 

ARM vtst_16 opcode.

OP_vtst_32 

ARM vtst_32 opcode.

OP_vtst_8 

ARM vtst_8 opcode.

OP_vuzp_16 

ARM vuzp_16 opcode.

OP_vuzp_32 

ARM vuzp_32 opcode.

OP_vuzp_8 

ARM vuzp_8 opcode.

OP_vzip_16 

ARM vzip_16 opcode.

OP_vzip_32 

ARM vzip_32 opcode.

OP_vzip_8 

ARM vzip_8 opcode.

OP_wfe 

ARM wfe opcode.

OP_wfi 

ARM wfi opcode.

OP_yield 

ARM yield opcode.

OP_FIRST 

First real opcode.

OP_LAST 

Last real opcode.

OP_UNDECODED 

INVALID opcode

OP_CONTD 

UNDECODED opcode

OP_LABEL 

CONTD opcode

OP_add 

LABEL opcode IA-32/AMD64 add opcode.

OP_or 

IA-32/AMD64 or opcode.

OP_adc 

IA-32/AMD64 adc opcode.

OP_sbb 

IA-32/AMD64 sbb opcode.

OP_and 

IA-32/AMD64 and opcode.

OP_daa 

IA-32/AMD64 daa opcode.

OP_sub 

IA-32/AMD64 sub opcode.

OP_das 

IA-32/AMD64 das opcode.

OP_xor 

IA-32/AMD64 xor opcode.

OP_aaa 

IA-32/AMD64 aaa opcode.

OP_cmp 

IA-32/AMD64 cmp opcode.

OP_aas 

IA-32/AMD64 aas opcode.

OP_inc 

IA-32/AMD64 inc opcode.

OP_dec 

IA-32/AMD64 dec opcode.

OP_push 

IA-32/AMD64 push opcode.

OP_push_imm 

IA-32/AMD64 push_imm opcode.

OP_pop 

IA-32/AMD64 pop opcode.

OP_pusha 

IA-32/AMD64 pusha opcode.

OP_popa 

IA-32/AMD64 popa opcode.

OP_bound 

IA-32/AMD64 bound opcode.

OP_arpl 

IA-32/AMD64 arpl opcode.

OP_imul 

IA-32/AMD64 imul opcode.

OP_jo_short 

IA-32/AMD64 jo_short opcode.

OP_jno_short 

IA-32/AMD64 jno_short opcode.

OP_jb_short 

IA-32/AMD64 jb_short opcode.

OP_jnb_short 

IA-32/AMD64 jnb_short opcode.

OP_jz_short 

IA-32/AMD64 jz_short opcode.

OP_jnz_short 

IA-32/AMD64 jnz_short opcode.

OP_jbe_short 

IA-32/AMD64 jbe_short opcode.

OP_jnbe_short 

IA-32/AMD64 jnbe_short opcode.

OP_js_short 

IA-32/AMD64 js_short opcode.

OP_jns_short 

IA-32/AMD64 jns_short opcode.

OP_jp_short 

IA-32/AMD64 jp_short opcode.

OP_jnp_short 

IA-32/AMD64 jnp_short opcode.

OP_jl_short 

IA-32/AMD64 jl_short opcode.

OP_jnl_short 

IA-32/AMD64 jnl_short opcode.

OP_jle_short 

IA-32/AMD64 jle_short opcode.

OP_jnle_short 

IA-32/AMD64 jnle_short opcode.

OP_call 

IA-32/AMD64 call opcode.

OP_call_ind 

IA-32/AMD64 call_ind opcode.

OP_call_far 

IA-32/AMD64 call_far opcode.

OP_call_far_ind 

IA-32/AMD64 call_far_ind opcode.

OP_jmp 

IA-32/AMD64 jmp opcode.

OP_jmp_short 

IA-32/AMD64 jmp_short opcode.

OP_jmp_ind 

IA-32/AMD64 jmp_ind opcode.

OP_jmp_far 

IA-32/AMD64 jmp_far opcode.

OP_jmp_far_ind 

IA-32/AMD64 jmp_far_ind opcode.

OP_loopne 

IA-32/AMD64 loopne opcode.

OP_loope 

IA-32/AMD64 loope opcode.

OP_loop 

IA-32/AMD64 loop opcode.

OP_jecxz 

IA-32/AMD64 jecxz opcode.

OP_mov_ld 

IA-32/AMD64 mov_ld opcode.

OP_mov_st 

IA-32/AMD64 mov_st opcode.

OP_mov_imm 

IA-32/AMD64 mov_imm opcode.

OP_mov_seg 

IA-32/AMD64 mov_seg opcode.

OP_mov_priv 

IA-32/AMD64 mov_priv opcode.

OP_test 

IA-32/AMD64 test opcode.

OP_lea 

IA-32/AMD64 lea opcode.

OP_xchg 

IA-32/AMD64 xchg opcode.

OP_cwde 

IA-32/AMD64 cwde opcode.

OP_cdq 

IA-32/AMD64 cdq opcode.

OP_fwait 

IA-32/AMD64 fwait opcode.

OP_pushf 

IA-32/AMD64 pushf opcode.

OP_popf 

IA-32/AMD64 popf opcode.

OP_sahf 

IA-32/AMD64 sahf opcode.

OP_lahf 

IA-32/AMD64 lahf opcode.

OP_ret 

IA-32/AMD64 ret opcode.

OP_ret_far 

IA-32/AMD64 ret_far opcode.

OP_les 

IA-32/AMD64 les opcode.

OP_lds 

IA-32/AMD64 lds opcode.

OP_enter 

IA-32/AMD64 enter opcode.

OP_leave 

IA-32/AMD64 leave opcode.

OP_int3 

IA-32/AMD64 int3 opcode.

OP_int 

IA-32/AMD64 int opcode.

OP_into 

IA-32/AMD64 into opcode.

OP_iret 

IA-32/AMD64 iret opcode.

OP_aam 

IA-32/AMD64 aam opcode.

OP_aad 

IA-32/AMD64 aad opcode.

OP_xlat 

IA-32/AMD64 xlat opcode.

OP_in 

IA-32/AMD64 in opcode.

OP_out 

IA-32/AMD64 out opcode.

OP_hlt 

IA-32/AMD64 hlt opcode.

OP_cmc 

IA-32/AMD64 cmc opcode.

OP_clc 

IA-32/AMD64 clc opcode.

OP_stc 

IA-32/AMD64 stc opcode.

OP_cli 

IA-32/AMD64 cli opcode.

OP_sti 

IA-32/AMD64 sti opcode.

OP_cld 

IA-32/AMD64 cld opcode.

OP_std 

IA-32/AMD64 std opcode.

OP_lar 

IA-32/AMD64 lar opcode.

OP_lsl 

IA-32/AMD64 lsl opcode.

OP_syscall 

IA-32/AMD64 syscall opcode.

OP_clts 

IA-32/AMD64 clts opcode.

OP_sysret 

IA-32/AMD64 sysret opcode.

OP_invd 

IA-32/AMD64 invd opcode.

OP_wbinvd 

IA-32/AMD64 wbinvd opcode.

OP_ud2a 

IA-32/AMD64 ud2a opcode.

OP_nop_modrm 

IA-32/AMD64 nop_modrm opcode.

OP_movntps 

IA-32/AMD64 movntps opcode.

OP_movntpd 

IA-32/AMD64 movntpd opcode.

OP_wrmsr 

IA-32/AMD64 wrmsr opcode.

OP_rdtsc 

IA-32/AMD64 rdtsc opcode.

OP_rdmsr 

IA-32/AMD64 rdmsr opcode.

OP_rdpmc 

IA-32/AMD64 rdpmc opcode.

OP_sysenter 

IA-32/AMD64 sysenter opcode.

OP_sysexit 

IA-32/AMD64 sysexit opcode.

OP_cmovo 

IA-32/AMD64 cmovo opcode.

OP_cmovno 

IA-32/AMD64 cmovno opcode.

OP_cmovb 

IA-32/AMD64 cmovb opcode.

OP_cmovnb 

IA-32/AMD64 cmovnb opcode.

OP_cmovz 

IA-32/AMD64 cmovz opcode.

OP_cmovnz 

IA-32/AMD64 cmovnz opcode.

OP_cmovbe 

IA-32/AMD64 cmovbe opcode.

OP_cmovnbe 

IA-32/AMD64 cmovnbe opcode.

OP_cmovs 

IA-32/AMD64 cmovs opcode.

OP_cmovns 

IA-32/AMD64 cmovns opcode.

OP_cmovp 

IA-32/AMD64 cmovp opcode.

OP_cmovnp 

IA-32/AMD64 cmovnp opcode.

OP_cmovl 

IA-32/AMD64 cmovl opcode.

OP_cmovnl 

IA-32/AMD64 cmovnl opcode.

OP_cmovle 

IA-32/AMD64 cmovle opcode.

OP_cmovnle 

IA-32/AMD64 cmovnle opcode.

OP_punpcklbw 

IA-32/AMD64 punpcklbw opcode.

OP_punpcklwd 

IA-32/AMD64 punpcklwd opcode.

OP_punpckldq 

IA-32/AMD64 punpckldq opcode.

OP_packsswb 

IA-32/AMD64 packsswb opcode.

OP_pcmpgtb 

IA-32/AMD64 pcmpgtb opcode.

OP_pcmpgtw 

IA-32/AMD64 pcmpgtw opcode.

OP_pcmpgtd 

IA-32/AMD64 pcmpgtd opcode.

OP_packuswb 

IA-32/AMD64 packuswb opcode.

OP_punpckhbw 

IA-32/AMD64 punpckhbw opcode.

OP_punpckhwd 

IA-32/AMD64 punpckhwd opcode.

OP_punpckhdq 

IA-32/AMD64 punpckhdq opcode.

OP_packssdw 

IA-32/AMD64 packssdw opcode.

OP_punpcklqdq 

IA-32/AMD64 punpcklqdq opcode.

OP_punpckhqdq 

IA-32/AMD64 punpckhqdq opcode.

OP_movd 

IA-32/AMD64 movd opcode.

OP_movq 

IA-32/AMD64 movq opcode.

OP_movdqu 

IA-32/AMD64 movdqu opcode.

OP_movdqa 

IA-32/AMD64 movdqa opcode.

OP_pshufw 

IA-32/AMD64 pshufw opcode.

OP_pshufd 

IA-32/AMD64 pshufd opcode.

OP_pshufhw 

IA-32/AMD64 pshufhw opcode.

OP_pshuflw 

IA-32/AMD64 pshuflw opcode.

OP_pcmpeqb 

IA-32/AMD64 pcmpeqb opcode.

OP_pcmpeqw 

IA-32/AMD64 pcmpeqw opcode.

OP_pcmpeqd 

IA-32/AMD64 pcmpeqd opcode.

OP_emms 

IA-32/AMD64 emms opcode.

OP_jo 

IA-32/AMD64 jo opcode.

OP_jno 

IA-32/AMD64 jno opcode.

OP_jb 

IA-32/AMD64 jb opcode.

OP_jnb 

IA-32/AMD64 jnb opcode.

OP_jz 

IA-32/AMD64 jz opcode.

OP_jnz 

IA-32/AMD64 jnz opcode.

OP_jbe 

IA-32/AMD64 jbe opcode.

OP_jnbe 

IA-32/AMD64 jnbe opcode.

OP_js 

IA-32/AMD64 js opcode.

OP_jns 

IA-32/AMD64 jns opcode.

OP_jp 

IA-32/AMD64 jp opcode.

OP_jnp 

IA-32/AMD64 jnp opcode.

OP_jl 

IA-32/AMD64 jl opcode.

OP_jnl 

IA-32/AMD64 jnl opcode.

OP_jle 

IA-32/AMD64 jle opcode.

OP_jnle 

IA-32/AMD64 jnle opcode.

OP_seto 

IA-32/AMD64 seto opcode.

OP_setno 

IA-32/AMD64 setno opcode.

OP_setb 

IA-32/AMD64 setb opcode.

OP_setnb 

IA-32/AMD64 setnb opcode.

OP_setz 

IA-32/AMD64 setz opcode.

OP_setnz 

IA-32/AMD64 setnz opcode.

OP_setbe 

IA-32/AMD64 setbe opcode.

OP_setnbe 

IA-32/AMD64 setnbe opcode.

OP_sets 

IA-32/AMD64 sets opcode.

OP_setns 

IA-32/AMD64 setns opcode.

OP_setp 

IA-32/AMD64 setp opcode.

OP_setnp 

IA-32/AMD64 setnp opcode.

OP_setl 

IA-32/AMD64 setl opcode.

OP_setnl 

IA-32/AMD64 setnl opcode.

OP_setle 

IA-32/AMD64 setle opcode.

OP_setnle 

IA-32/AMD64 setnle opcode.

OP_cpuid 

IA-32/AMD64 cpuid opcode.

OP_bt 

IA-32/AMD64 bt opcode.

OP_shld 

IA-32/AMD64 shld opcode.

OP_rsm 

IA-32/AMD64 rsm opcode.

OP_bts 

IA-32/AMD64 bts opcode.

OP_shrd 

IA-32/AMD64 shrd opcode.

OP_cmpxchg 

IA-32/AMD64 cmpxchg opcode.

OP_lss 

IA-32/AMD64 lss opcode.

OP_btr 

IA-32/AMD64 btr opcode.

OP_lfs 

IA-32/AMD64 lfs opcode.

OP_lgs 

IA-32/AMD64 lgs opcode.

OP_movzx 

IA-32/AMD64 movzx opcode.

OP_ud2b 

IA-32/AMD64 ud2b opcode.

OP_btc 

IA-32/AMD64 btc opcode.

OP_bsf 

IA-32/AMD64 bsf opcode.

OP_bsr 

IA-32/AMD64 bsr opcode.

OP_movsx 

IA-32/AMD64 movsx opcode.

OP_xadd 

IA-32/AMD64 xadd opcode.

OP_movnti 

IA-32/AMD64 movnti opcode.

OP_pinsrw 

IA-32/AMD64 pinsrw opcode.

OP_pextrw 

IA-32/AMD64 pextrw opcode.

OP_bswap 

IA-32/AMD64 bswap opcode.

OP_psrlw 

IA-32/AMD64 psrlw opcode.

OP_psrld 

IA-32/AMD64 psrld opcode.

OP_psrlq 

IA-32/AMD64 psrlq opcode.

OP_paddq 

IA-32/AMD64 paddq opcode.

OP_pmullw 

IA-32/AMD64 pmullw opcode.

OP_pmovmskb 

IA-32/AMD64 pmovmskb opcode.

OP_psubusb 

IA-32/AMD64 psubusb opcode.

OP_psubusw 

IA-32/AMD64 psubusw opcode.

OP_pminub 

IA-32/AMD64 pminub opcode.

OP_pand 

IA-32/AMD64 pand opcode.

OP_paddusb 

IA-32/AMD64 paddusb opcode.

OP_paddusw 

IA-32/AMD64 paddusw opcode.

OP_pmaxub 

IA-32/AMD64 pmaxub opcode.

OP_pandn 

IA-32/AMD64 pandn opcode.

OP_pavgb 

IA-32/AMD64 pavgb opcode.

OP_psraw 

IA-32/AMD64 psraw opcode.

OP_psrad 

IA-32/AMD64 psrad opcode.

OP_pavgw 

IA-32/AMD64 pavgw opcode.

OP_pmulhuw 

IA-32/AMD64 pmulhuw opcode.

OP_pmulhw 

IA-32/AMD64 pmulhw opcode.

OP_movntq 

IA-32/AMD64 movntq opcode.

OP_movntdq 

IA-32/AMD64 movntdq opcode.

OP_psubsb 

IA-32/AMD64 psubsb opcode.

OP_psubsw 

IA-32/AMD64 psubsw opcode.

OP_pminsw 

IA-32/AMD64 pminsw opcode.

OP_por 

IA-32/AMD64 por opcode.

OP_paddsb 

IA-32/AMD64 paddsb opcode.

OP_paddsw 

IA-32/AMD64 paddsw opcode.

OP_pmaxsw 

IA-32/AMD64 pmaxsw opcode.

OP_pxor 

IA-32/AMD64 pxor opcode.

OP_psllw 

IA-32/AMD64 psllw opcode.

OP_pslld 

IA-32/AMD64 pslld opcode.

OP_psllq 

IA-32/AMD64 psllq opcode.

OP_pmuludq 

IA-32/AMD64 pmuludq opcode.

OP_pmaddwd 

IA-32/AMD64 pmaddwd opcode.

OP_psadbw 

IA-32/AMD64 psadbw opcode.

OP_maskmovq 

IA-32/AMD64 maskmovq opcode.

OP_maskmovdqu 

IA-32/AMD64 maskmovdqu opcode.

OP_psubb 

IA-32/AMD64 psubb opcode.

OP_psubw 

IA-32/AMD64 psubw opcode.

OP_psubd 

IA-32/AMD64 psubd opcode.

OP_psubq 

IA-32/AMD64 psubq opcode.

OP_paddb 

IA-32/AMD64 paddb opcode.

OP_paddw 

IA-32/AMD64 paddw opcode.

OP_paddd 

IA-32/AMD64 paddd opcode.

OP_psrldq 

IA-32/AMD64 psrldq opcode.

OP_pslldq 

IA-32/AMD64 pslldq opcode.

OP_rol 

IA-32/AMD64 rol opcode.

OP_ror 

IA-32/AMD64 ror opcode.

OP_rcl 

IA-32/AMD64 rcl opcode.

OP_rcr 

IA-32/AMD64 rcr opcode.

OP_shl 

IA-32/AMD64 shl opcode.

OP_shr 

IA-32/AMD64 shr opcode.

OP_sar 

IA-32/AMD64 sar opcode.

OP_not 

IA-32/AMD64 not opcode.

OP_neg 

IA-32/AMD64 neg opcode.

OP_mul 

IA-32/AMD64 mul opcode.

OP_div 

IA-32/AMD64 div opcode.

OP_idiv 

IA-32/AMD64 idiv opcode.

OP_sldt 

IA-32/AMD64 sldt opcode.

OP_str 

IA-32/AMD64 str opcode.

OP_lldt 

IA-32/AMD64 lldt opcode.

OP_ltr 

IA-32/AMD64 ltr opcode.

OP_verr 

IA-32/AMD64 verr opcode.

OP_verw 

IA-32/AMD64 verw opcode.

OP_sgdt 

IA-32/AMD64 sgdt opcode.

OP_sidt 

IA-32/AMD64 sidt opcode.

OP_lgdt 

IA-32/AMD64 lgdt opcode.

OP_lidt 

IA-32/AMD64 lidt opcode.

OP_smsw 

IA-32/AMD64 smsw opcode.

OP_lmsw 

IA-32/AMD64 lmsw opcode.

OP_invlpg 

IA-32/AMD64 invlpg opcode.

OP_cmpxchg8b 

IA-32/AMD64 cmpxchg8b opcode.

OP_fxsave32 

IA-32/AMD64 fxsave opcode.

OP_fxrstor32 

IA-32/AMD64 fxrstor opcode.

OP_ldmxcsr 

IA-32/AMD64 ldmxcsr opcode.

OP_stmxcsr 

IA-32/AMD64 stmxcsr opcode.

OP_lfence 

IA-32/AMD64 lfence opcode.

OP_mfence 

IA-32/AMD64 mfence opcode.

OP_clflush 

IA-32/AMD64 clflush opcode.

OP_sfence 

IA-32/AMD64 sfence opcode.

OP_prefetchnta 

IA-32/AMD64 prefetchnta opcode.

OP_prefetcht0 

IA-32/AMD64 prefetcht0 opcode.

OP_prefetcht1 

IA-32/AMD64 prefetcht1 opcode.

OP_prefetcht2 

IA-32/AMD64 prefetcht2 opcode.

OP_prefetch 

IA-32/AMD64 prefetch opcode.

OP_prefetchw 

IA-32/AMD64 prefetchw opcode.

OP_movups 

IA-32/AMD64 movups opcode.

OP_movss 

IA-32/AMD64 movss opcode.

OP_movupd 

IA-32/AMD64 movupd opcode.

OP_movsd 

IA-32/AMD64 movsd opcode.

OP_movlps 

IA-32/AMD64 movlps opcode.

OP_movlpd 

IA-32/AMD64 movlpd opcode.

OP_unpcklps 

IA-32/AMD64 unpcklps opcode.

OP_unpcklpd 

IA-32/AMD64 unpcklpd opcode.

OP_unpckhps 

IA-32/AMD64 unpckhps opcode.

OP_unpckhpd 

IA-32/AMD64 unpckhpd opcode.

OP_movhps 

IA-32/AMD64 movhps opcode.

OP_movhpd 

IA-32/AMD64 movhpd opcode.

OP_movaps 

IA-32/AMD64 movaps opcode.

OP_movapd 

IA-32/AMD64 movapd opcode.

OP_cvtpi2ps 

IA-32/AMD64 cvtpi2ps opcode.

OP_cvtsi2ss 

IA-32/AMD64 cvtsi2ss opcode.

OP_cvtpi2pd 

IA-32/AMD64 cvtpi2pd opcode.

OP_cvtsi2sd 

IA-32/AMD64 cvtsi2sd opcode.

OP_cvttps2pi 

IA-32/AMD64 cvttps2pi opcode.

OP_cvttss2si 

IA-32/AMD64 cvttss2si opcode.

OP_cvttpd2pi 

IA-32/AMD64 cvttpd2pi opcode.

OP_cvttsd2si 

IA-32/AMD64 cvttsd2si opcode.

OP_cvtps2pi 

IA-32/AMD64 cvtps2pi opcode.

OP_cvtss2si 

IA-32/AMD64 cvtss2si opcode.

OP_cvtpd2pi 

IA-32/AMD64 cvtpd2pi opcode.

OP_cvtsd2si 

IA-32/AMD64 cvtsd2si opcode.

OP_ucomiss 

IA-32/AMD64 ucomiss opcode.

OP_ucomisd 

IA-32/AMD64 ucomisd opcode.

OP_comiss 

IA-32/AMD64 comiss opcode.

OP_comisd 

IA-32/AMD64 comisd opcode.

OP_movmskps 

IA-32/AMD64 movmskps opcode.

OP_movmskpd 

IA-32/AMD64 movmskpd opcode.

OP_sqrtps 

IA-32/AMD64 sqrtps opcode.

OP_sqrtss 

IA-32/AMD64 sqrtss opcode.

OP_sqrtpd 

IA-32/AMD64 sqrtpd opcode.

OP_sqrtsd 

IA-32/AMD64 sqrtsd opcode.

OP_rsqrtps 

IA-32/AMD64 rsqrtps opcode.

OP_rsqrtss 

IA-32/AMD64 rsqrtss opcode.

OP_rcpps 

IA-32/AMD64 rcpps opcode.

OP_rcpss 

IA-32/AMD64 rcpss opcode.

OP_andps 

IA-32/AMD64 andps opcode.

OP_andpd 

IA-32/AMD64 andpd opcode.

OP_andnps 

IA-32/AMD64 andnps opcode.

OP_andnpd 

IA-32/AMD64 andnpd opcode.

OP_orps 

IA-32/AMD64 orps opcode.

OP_orpd 

IA-32/AMD64 orpd opcode.

OP_xorps 

IA-32/AMD64 xorps opcode.

OP_xorpd 

IA-32/AMD64 xorpd opcode.

OP_addps 

IA-32/AMD64 addps opcode.

OP_addss 

IA-32/AMD64 addss opcode.

OP_addpd 

IA-32/AMD64 addpd opcode.

OP_addsd 

IA-32/AMD64 addsd opcode.

OP_mulps 

IA-32/AMD64 mulps opcode.

OP_mulss 

IA-32/AMD64 mulss opcode.

OP_mulpd 

IA-32/AMD64 mulpd opcode.

OP_mulsd 

IA-32/AMD64 mulsd opcode.

OP_cvtps2pd 

IA-32/AMD64 cvtps2pd opcode.

OP_cvtss2sd 

IA-32/AMD64 cvtss2sd opcode.

OP_cvtpd2ps 

IA-32/AMD64 cvtpd2ps opcode.

OP_cvtsd2ss 

IA-32/AMD64 cvtsd2ss opcode.

OP_cvtdq2ps 

IA-32/AMD64 cvtdq2ps opcode.

OP_cvttps2dq 

IA-32/AMD64 cvttps2dq opcode.

OP_cvtps2dq 

IA-32/AMD64 cvtps2dq opcode.

OP_subps 

IA-32/AMD64 subps opcode.

OP_subss 

IA-32/AMD64 subss opcode.

OP_subpd 

IA-32/AMD64 subpd opcode.

OP_subsd 

IA-32/AMD64 subsd opcode.

OP_minps 

IA-32/AMD64 minps opcode.

OP_minss 

IA-32/AMD64 minss opcode.

OP_minpd 

IA-32/AMD64 minpd opcode.

OP_minsd 

IA-32/AMD64 minsd opcode.

OP_divps 

IA-32/AMD64 divps opcode.

OP_divss 

IA-32/AMD64 divss opcode.

OP_divpd 

IA-32/AMD64 divpd opcode.

OP_divsd 

IA-32/AMD64 divsd opcode.

OP_maxps 

IA-32/AMD64 maxps opcode.

OP_maxss 

IA-32/AMD64 maxss opcode.

OP_maxpd 

IA-32/AMD64 maxpd opcode.

OP_maxsd 

IA-32/AMD64 maxsd opcode.

OP_cmpps 

IA-32/AMD64 cmpps opcode.

OP_cmpss 

IA-32/AMD64 cmpss opcode.

OP_cmppd 

IA-32/AMD64 cmppd opcode.

OP_cmpsd 

IA-32/AMD64 cmpsd opcode.

OP_shufps 

IA-32/AMD64 shufps opcode.

OP_shufpd 

IA-32/AMD64 shufpd opcode.

OP_cvtdq2pd 

IA-32/AMD64 cvtdq2pd opcode.

OP_cvttpd2dq 

IA-32/AMD64 cvttpd2dq opcode.

OP_cvtpd2dq 

IA-32/AMD64 cvtpd2dq opcode.

OP_nop 

IA-32/AMD64 nop opcode.

OP_pause 

IA-32/AMD64 pause opcode.

OP_ins 

IA-32/AMD64 ins opcode.

OP_rep_ins 

IA-32/AMD64 rep_ins opcode.

OP_outs 

IA-32/AMD64 outs opcode.

OP_rep_outs 

IA-32/AMD64 rep_outs opcode.

OP_movs 

IA-32/AMD64 movs opcode.

OP_rep_movs 

IA-32/AMD64 rep_movs opcode.

OP_stos 

IA-32/AMD64 stos opcode.

OP_rep_stos 

IA-32/AMD64 rep_stos opcode.

OP_lods 

IA-32/AMD64 lods opcode.

OP_rep_lods 

IA-32/AMD64 rep_lods opcode.

OP_cmps 

IA-32/AMD64 cmps opcode.

OP_rep_cmps 

IA-32/AMD64 rep_cmps opcode.

OP_repne_cmps 

IA-32/AMD64 repne_cmps opcode.

OP_scas 

IA-32/AMD64 scas opcode.

OP_rep_scas 

IA-32/AMD64 rep_scas opcode.

OP_repne_scas 

IA-32/AMD64 repne_scas opcode.

OP_fadd 

IA-32/AMD64 fadd opcode.

OP_fmul 

IA-32/AMD64 fmul opcode.

OP_fcom 

IA-32/AMD64 fcom opcode.

OP_fcomp 

IA-32/AMD64 fcomp opcode.

OP_fsub 

IA-32/AMD64 fsub opcode.

OP_fsubr 

IA-32/AMD64 fsubr opcode.

OP_fdiv 

IA-32/AMD64 fdiv opcode.

OP_fdivr 

IA-32/AMD64 fdivr opcode.

OP_fld 

IA-32/AMD64 fld opcode.

OP_fst 

IA-32/AMD64 fst opcode.

OP_fstp 

IA-32/AMD64 fstp opcode.

OP_fldenv 

IA-32/AMD64 fldenv opcode.

OP_fldcw 

IA-32/AMD64 fldcw opcode.

OP_fnstenv 

IA-32/AMD64 fnstenv opcode.

OP_fnstcw 

IA-32/AMD64 fnstcw opcode.

OP_fiadd 

IA-32/AMD64 fiadd opcode.

OP_fimul 

IA-32/AMD64 fimul opcode.

OP_ficom 

IA-32/AMD64 ficom opcode.

OP_ficomp 

IA-32/AMD64 ficomp opcode.

OP_fisub 

IA-32/AMD64 fisub opcode.

OP_fisubr 

IA-32/AMD64 fisubr opcode.

OP_fidiv 

IA-32/AMD64 fidiv opcode.

OP_fidivr 

IA-32/AMD64 fidivr opcode.

OP_fild 

IA-32/AMD64 fild opcode.

OP_fist 

IA-32/AMD64 fist opcode.

OP_fistp 

IA-32/AMD64 fistp opcode.

OP_frstor 

IA-32/AMD64 frstor opcode.

OP_fnsave 

IA-32/AMD64 fnsave opcode.

OP_fnstsw 

IA-32/AMD64 fnstsw opcode.

OP_fbld 

IA-32/AMD64 fbld opcode.

OP_fbstp 

IA-32/AMD64 fbstp opcode.

OP_fxch 

IA-32/AMD64 fxch opcode.

OP_fnop 

IA-32/AMD64 fnop opcode.

OP_fchs 

IA-32/AMD64 fchs opcode.

OP_fabs 

IA-32/AMD64 fabs opcode.

OP_ftst 

IA-32/AMD64 ftst opcode.

OP_fxam 

IA-32/AMD64 fxam opcode.

OP_fld1 

IA-32/AMD64 fld1 opcode.

OP_fldl2t 

IA-32/AMD64 fldl2t opcode.

OP_fldl2e 

IA-32/AMD64 fldl2e opcode.

OP_fldpi 

IA-32/AMD64 fldpi opcode.

OP_fldlg2 

IA-32/AMD64 fldlg2 opcode.

OP_fldln2 

IA-32/AMD64 fldln2 opcode.

OP_fldz 

IA-32/AMD64 fldz opcode.

OP_f2xm1 

IA-32/AMD64 f2xm1 opcode.

OP_fyl2x 

IA-32/AMD64 fyl2x opcode.

OP_fptan 

IA-32/AMD64 fptan opcode.

OP_fpatan 

IA-32/AMD64 fpatan opcode.

OP_fxtract 

IA-32/AMD64 fxtract opcode.

OP_fprem1 

IA-32/AMD64 fprem1 opcode.

OP_fdecstp 

IA-32/AMD64 fdecstp opcode.

OP_fincstp 

IA-32/AMD64 fincstp opcode.

OP_fprem 

IA-32/AMD64 fprem opcode.

OP_fyl2xp1 

IA-32/AMD64 fyl2xp1 opcode.

OP_fsqrt 

IA-32/AMD64 fsqrt opcode.

OP_fsincos 

IA-32/AMD64 fsincos opcode.

OP_frndint 

IA-32/AMD64 frndint opcode.

OP_fscale 

IA-32/AMD64 fscale opcode.

OP_fsin 

IA-32/AMD64 fsin opcode.

OP_fcos 

IA-32/AMD64 fcos opcode.

OP_fcmovb 

IA-32/AMD64 fcmovb opcode.

OP_fcmove 

IA-32/AMD64 fcmove opcode.

OP_fcmovbe 

IA-32/AMD64 fcmovbe opcode.

OP_fcmovu 

IA-32/AMD64 fcmovu opcode.

OP_fucompp 

IA-32/AMD64 fucompp opcode.

OP_fcmovnb 

IA-32/AMD64 fcmovnb opcode.

OP_fcmovne 

IA-32/AMD64 fcmovne opcode.

OP_fcmovnbe 

IA-32/AMD64 fcmovnbe opcode.

OP_fcmovnu 

IA-32/AMD64 fcmovnu opcode.

OP_fnclex 

IA-32/AMD64 fnclex opcode.

OP_fninit 

IA-32/AMD64 fninit opcode.

OP_fucomi 

IA-32/AMD64 fucomi opcode.

OP_fcomi 

IA-32/AMD64 fcomi opcode.

OP_ffree 

IA-32/AMD64 ffree opcode.

OP_fucom 

IA-32/AMD64 fucom opcode.

OP_fucomp 

IA-32/AMD64 fucomp opcode.

OP_faddp 

IA-32/AMD64 faddp opcode.

OP_fmulp 

IA-32/AMD64 fmulp opcode.

OP_fcompp 

IA-32/AMD64 fcompp opcode.

OP_fsubrp 

IA-32/AMD64 fsubrp opcode.

OP_fsubp 

IA-32/AMD64 fsubp opcode.

OP_fdivrp 

IA-32/AMD64 fdivrp opcode.

OP_fdivp 

IA-32/AMD64 fdivp opcode.

OP_fucomip 

IA-32/AMD64 fucomip opcode.

OP_fcomip 

IA-32/AMD64 fcomip opcode.

OP_fisttp 

IA-32/AMD64 fisttp opcode.

OP_haddpd 

IA-32/AMD64 haddpd opcode.

OP_haddps 

IA-32/AMD64 haddps opcode.

OP_hsubpd 

IA-32/AMD64 hsubpd opcode.

OP_hsubps 

IA-32/AMD64 hsubps opcode.

OP_addsubpd 

IA-32/AMD64 addsubpd opcode.

OP_addsubps 

IA-32/AMD64 addsubps opcode.

OP_lddqu 

IA-32/AMD64 lddqu opcode.

OP_monitor 

IA-32/AMD64 monitor opcode.

OP_mwait 

IA-32/AMD64 mwait opcode.

OP_movsldup 

IA-32/AMD64 movsldup opcode.

OP_movshdup 

IA-32/AMD64 movshdup opcode.

OP_movddup 

IA-32/AMD64 movddup opcode.

OP_femms 

IA-32/AMD64 femms opcode.

OP_unknown_3dnow 

IA-32/AMD64 unknown_3dnow opcode.

OP_pavgusb 

IA-32/AMD64 pavgusb opcode.

OP_pfadd 

IA-32/AMD64 pfadd opcode.

OP_pfacc 

IA-32/AMD64 pfacc opcode.

OP_pfcmpge 

IA-32/AMD64 pfcmpge opcode.

OP_pfcmpgt 

IA-32/AMD64 pfcmpgt opcode.

OP_pfcmpeq 

IA-32/AMD64 pfcmpeq opcode.

OP_pfmin 

IA-32/AMD64 pfmin opcode.

OP_pfmax 

IA-32/AMD64 pfmax opcode.

OP_pfmul 

IA-32/AMD64 pfmul opcode.

OP_pfrcp 

IA-32/AMD64 pfrcp opcode.

OP_pfrcpit1 

IA-32/AMD64 pfrcpit1 opcode.

OP_pfrcpit2 

IA-32/AMD64 pfrcpit2 opcode.

OP_pfrsqrt 

IA-32/AMD64 pfrsqrt opcode.

OP_pfrsqit1 

IA-32/AMD64 pfrsqit1 opcode.

OP_pmulhrw 

IA-32/AMD64 pmulhrw opcode.

OP_pfsub 

IA-32/AMD64 pfsub opcode.

OP_pfsubr 

IA-32/AMD64 pfsubr opcode.

OP_pi2fd 

IA-32/AMD64 pi2fd opcode.

OP_pf2id 

IA-32/AMD64 pf2id opcode.

OP_pi2fw 

IA-32/AMD64 pi2fw opcode.

OP_pf2iw 

IA-32/AMD64 pf2iw opcode.

OP_pfnacc 

IA-32/AMD64 pfnacc opcode.

OP_pfpnacc 

IA-32/AMD64 pfpnacc opcode.

OP_pswapd 

IA-32/AMD64 pswapd opcode.

OP_pshufb 

IA-32/AMD64 pshufb opcode.

OP_phaddw 

IA-32/AMD64 phaddw opcode.

OP_phaddd 

IA-32/AMD64 phaddd opcode.

OP_phaddsw 

IA-32/AMD64 phaddsw opcode.

OP_pmaddubsw 

IA-32/AMD64 pmaddubsw opcode.

OP_phsubw 

IA-32/AMD64 phsubw opcode.

OP_phsubd 

IA-32/AMD64 phsubd opcode.

OP_phsubsw 

IA-32/AMD64 phsubsw opcode.

OP_psignb 

IA-32/AMD64 psignb opcode.

OP_psignw 

IA-32/AMD64 psignw opcode.

OP_psignd 

IA-32/AMD64 psignd opcode.

OP_pmulhrsw 

IA-32/AMD64 pmulhrsw opcode.

OP_pabsb 

IA-32/AMD64 pabsb opcode.

OP_pabsw 

IA-32/AMD64 pabsw opcode.

OP_pabsd 

IA-32/AMD64 pabsd opcode.

OP_palignr 

IA-32/AMD64 palignr opcode.

OP_popcnt 

IA-32/AMD64 popcnt opcode.

OP_movntss 

IA-32/AMD64 movntss opcode.

OP_movntsd 

IA-32/AMD64 movntsd opcode.

OP_extrq 

IA-32/AMD64 extrq opcode.

OP_insertq 

IA-32/AMD64 insertq opcode.

OP_lzcnt 

IA-32/AMD64 lzcnt opcode.

OP_pblendvb 

IA-32/AMD64 pblendvb opcode.

OP_blendvps 

IA-32/AMD64 blendvps opcode.

OP_blendvpd 

IA-32/AMD64 blendvpd opcode.

OP_ptest 

IA-32/AMD64 ptest opcode.

OP_pmovsxbw 

IA-32/AMD64 pmovsxbw opcode.

OP_pmovsxbd 

IA-32/AMD64 pmovsxbd opcode.

OP_pmovsxbq 

IA-32/AMD64 pmovsxbq opcode.

OP_pmovsxwd 

IA-32/AMD64 pmovsxwd opcode.

OP_pmovsxwq 

IA-32/AMD64 pmovsxwq opcode.

OP_pmovsxdq 

IA-32/AMD64 pmovsxdq opcode.

OP_pmuldq 

IA-32/AMD64 pmuldq opcode.

OP_pcmpeqq 

IA-32/AMD64 pcmpeqq opcode.

OP_movntdqa 

IA-32/AMD64 movntdqa opcode.

OP_packusdw 

IA-32/AMD64 packusdw opcode.

OP_pmovzxbw 

IA-32/AMD64 pmovzxbw opcode.

OP_pmovzxbd 

IA-32/AMD64 pmovzxbd opcode.

OP_pmovzxbq 

IA-32/AMD64 pmovzxbq opcode.

OP_pmovzxwd 

IA-32/AMD64 pmovzxwd opcode.

OP_pmovzxwq 

IA-32/AMD64 pmovzxwq opcode.

OP_pmovzxdq 

IA-32/AMD64 pmovzxdq opcode.

OP_pcmpgtq 

IA-32/AMD64 pcmpgtq opcode.

OP_pminsb 

IA-32/AMD64 pminsb opcode.

OP_pminsd 

IA-32/AMD64 pminsd opcode.

OP_pminuw 

IA-32/AMD64 pminuw opcode.

OP_pminud 

IA-32/AMD64 pminud opcode.

OP_pmaxsb 

IA-32/AMD64 pmaxsb opcode.

OP_pmaxsd 

IA-32/AMD64 pmaxsd opcode.

OP_pmaxuw 

IA-32/AMD64 pmaxuw opcode.

OP_pmaxud 

IA-32/AMD64 pmaxud opcode.

OP_pmulld 

IA-32/AMD64 pmulld opcode.

OP_phminposuw 

IA-32/AMD64 phminposuw opcode.

OP_crc32 

IA-32/AMD64 crc32 opcode.

OP_pextrb 

IA-32/AMD64 pextrb opcode.

OP_pextrd 

IA-32/AMD64 pextrd opcode.

OP_extractps 

IA-32/AMD64 extractps opcode.

OP_roundps 

IA-32/AMD64 roundps opcode.

OP_roundpd 

IA-32/AMD64 roundpd opcode.

OP_roundss 

IA-32/AMD64 roundss opcode.

OP_roundsd 

IA-32/AMD64 roundsd opcode.

OP_blendps 

IA-32/AMD64 blendps opcode.

OP_blendpd 

IA-32/AMD64 blendpd opcode.

OP_pblendw 

IA-32/AMD64 pblendw opcode.

OP_pinsrb 

IA-32/AMD64 pinsrb opcode.

OP_insertps 

IA-32/AMD64 insertps opcode.

OP_pinsrd 

IA-32/AMD64 pinsrd opcode.

OP_dpps 

IA-32/AMD64 dpps opcode.

OP_dppd 

IA-32/AMD64 dppd opcode.

OP_mpsadbw 

IA-32/AMD64 mpsadbw opcode.

OP_pcmpestrm 

IA-32/AMD64 pcmpestrm opcode.

OP_pcmpestri 

IA-32/AMD64 pcmpestri opcode.

OP_pcmpistrm 

IA-32/AMD64 pcmpistrm opcode.

OP_pcmpistri 

IA-32/AMD64 pcmpistri opcode.

OP_movsxd 

IA-32/AMD64 movsxd opcode.

OP_swapgs 

IA-32/AMD64 swapgs opcode.

OP_vmcall 

IA-32/AMD64 vmcall opcode.

OP_vmlaunch 

IA-32/AMD64 vmlaunch opcode.

OP_vmresume 

IA-32/AMD64 vmresume opcode.

OP_vmxoff 

IA-32/AMD64 vmxoff opcode.

OP_vmptrst 

IA-32/AMD64 vmptrst opcode.

OP_vmptrld 

IA-32/AMD64 vmptrld opcode.

OP_vmxon 

IA-32/AMD64 vmxon opcode.

OP_vmclear 

IA-32/AMD64 vmclear opcode.

OP_vmread 

IA-32/AMD64 vmread opcode.

OP_vmwrite 

IA-32/AMD64 vmwrite opcode.

OP_int1 

IA-32/AMD64 int1 opcode.

OP_salc 

IA-32/AMD64 salc opcode.

OP_ffreep 

IA-32/AMD64 ffreep opcode.

OP_vmrun 

IA-32/AMD64 vmrun opcode.

OP_vmmcall 

IA-32/AMD64 vmmcall opcode.

OP_vmload 

IA-32/AMD64 vmload opcode.

OP_vmsave 

IA-32/AMD64 vmsave opcode.

OP_stgi 

IA-32/AMD64 stgi opcode.

OP_clgi 

IA-32/AMD64 clgi opcode.

OP_skinit 

IA-32/AMD64 skinit opcode.

OP_invlpga 

IA-32/AMD64 invlpga opcode.

OP_rdtscp 

IA-32/AMD64 rdtscp opcode.

OP_invept 

IA-32/AMD64 invept opcode.

OP_invvpid 

IA-32/AMD64 invvpid opcode.

OP_pclmulqdq 

IA-32/AMD64 pclmulqdq opcode.

OP_aesimc 

IA-32/AMD64 aesimc opcode.

OP_aesenc 

IA-32/AMD64 aesenc opcode.

OP_aesenclast 

IA-32/AMD64 aesenclast opcode.

OP_aesdec 

IA-32/AMD64 aesdec opcode.

OP_aesdeclast 

IA-32/AMD64 aesdeclast opcode.

OP_aeskeygenassist 

IA-32/AMD64 aeskeygenassist opcode.

OP_movbe 

IA-32/AMD64 movbe opcode.

OP_xgetbv 

IA-32/AMD64 xgetbv opcode.

OP_xsetbv 

IA-32/AMD64 xsetbv opcode.

OP_xsave32 

IA-32/AMD64 xsave opcode.

OP_xrstor32 

IA-32/AMD64 xrstor opcode.

OP_xsaveopt32 

IA-32/AMD64 xsaveopt opcode.

OP_vmovss 

IA-32/AMD64 vmovss opcode.

OP_vmovsd 

IA-32/AMD64 vmovsd opcode.

OP_vmovups 

IA-32/AMD64 vmovups opcode.

OP_vmovupd 

IA-32/AMD64 vmovupd opcode.

OP_vmovlps 

IA-32/AMD64 vmovlps opcode.

OP_vmovsldup 

IA-32/AMD64 vmovsldup opcode.

OP_vmovlpd 

IA-32/AMD64 vmovlpd opcode.

OP_vmovddup 

IA-32/AMD64 vmovddup opcode.

OP_vunpcklps 

IA-32/AMD64 vunpcklps opcode.

OP_vunpcklpd 

IA-32/AMD64 vunpcklpd opcode.

OP_vunpckhps 

IA-32/AMD64 vunpckhps opcode.

OP_vunpckhpd 

IA-32/AMD64 vunpckhpd opcode.

OP_vmovhps 

IA-32/AMD64 vmovhps opcode.

OP_vmovshdup 

IA-32/AMD64 vmovshdup opcode.

OP_vmovhpd 

IA-32/AMD64 vmovhpd opcode.

OP_vmovaps 

IA-32/AMD64 vmovaps opcode.

OP_vmovapd 

IA-32/AMD64 vmovapd opcode.

OP_vcvtsi2ss 

IA-32/AMD64 vcvtsi2ss opcode.

OP_vcvtsi2sd 

IA-32/AMD64 vcvtsi2sd opcode.

OP_vmovntps 

IA-32/AMD64 vmovntps opcode.

OP_vmovntpd 

IA-32/AMD64 vmovntpd opcode.

OP_vcvttss2si 

IA-32/AMD64 vcvttss2si opcode.

OP_vcvttsd2si 

IA-32/AMD64 vcvttsd2si opcode.

OP_vcvtss2si 

IA-32/AMD64 vcvtss2si opcode.

OP_vcvtsd2si 

IA-32/AMD64 vcvtsd2si opcode.

OP_vucomiss 

IA-32/AMD64 vucomiss opcode.

OP_vucomisd 

IA-32/AMD64 vucomisd opcode.

OP_vcomiss 

IA-32/AMD64 vcomiss opcode.

OP_vcomisd 

IA-32/AMD64 vcomisd opcode.

OP_vmovmskps 

IA-32/AMD64 vmovmskps opcode.

OP_vmovmskpd 

IA-32/AMD64 vmovmskpd opcode.

OP_vsqrtps 

IA-32/AMD64 vsqrtps opcode.

OP_vsqrtss 

IA-32/AMD64 vsqrtss opcode.

OP_vsqrtpd 

IA-32/AMD64 vsqrtpd opcode.

OP_vsqrtsd 

IA-32/AMD64 vsqrtsd opcode.

OP_vrsqrtps 

IA-32/AMD64 vrsqrtps opcode.

OP_vrsqrtss 

IA-32/AMD64 vrsqrtss opcode.

OP_vrcpps 

IA-32/AMD64 vrcpps opcode.

OP_vrcpss 

IA-32/AMD64 vrcpss opcode.

OP_vandps 

IA-32/AMD64 vandps opcode.

OP_vandpd 

IA-32/AMD64 vandpd opcode.

OP_vandnps 

IA-32/AMD64 vandnps opcode.

OP_vandnpd 

IA-32/AMD64 vandnpd opcode.

OP_vorps 

IA-32/AMD64 vorps opcode.

OP_vorpd 

IA-32/AMD64 vorpd opcode.

OP_vxorps 

IA-32/AMD64 vxorps opcode.

OP_vxorpd 

IA-32/AMD64 vxorpd opcode.

OP_vaddps 

IA-32/AMD64 vaddps opcode.

OP_vaddss 

IA-32/AMD64 vaddss opcode.

OP_vaddpd 

IA-32/AMD64 vaddpd opcode.

OP_vaddsd 

IA-32/AMD64 vaddsd opcode.

OP_vmulps 

IA-32/AMD64 vmulps opcode.

OP_vmulss 

IA-32/AMD64 vmulss opcode.

OP_vmulpd 

IA-32/AMD64 vmulpd opcode.

OP_vmulsd 

IA-32/AMD64 vmulsd opcode.

OP_vcvtps2pd 

IA-32/AMD64 vcvtps2pd opcode.

OP_vcvtss2sd 

IA-32/AMD64 vcvtss2sd opcode.

OP_vcvtpd2ps 

IA-32/AMD64 vcvtpd2ps opcode.

OP_vcvtsd2ss 

IA-32/AMD64 vcvtsd2ss opcode.

OP_vcvtdq2ps 

IA-32/AMD64 vcvtdq2ps opcode.

OP_vcvttps2dq 

IA-32/AMD64 vcvttps2dq opcode.

OP_vcvtps2dq 

IA-32/AMD64 vcvtps2dq opcode.

OP_vsubps 

IA-32/AMD64 vsubps opcode.

OP_vsubss 

IA-32/AMD64 vsubss opcode.

OP_vsubpd 

IA-32/AMD64 vsubpd opcode.

OP_vsubsd 

IA-32/AMD64 vsubsd opcode.

OP_vminps 

IA-32/AMD64 vminps opcode.

OP_vminss 

IA-32/AMD64 vminss opcode.

OP_vminpd 

IA-32/AMD64 vminpd opcode.

OP_vminsd 

IA-32/AMD64 vminsd opcode.

OP_vdivps 

IA-32/AMD64 vdivps opcode.

OP_vdivss 

IA-32/AMD64 vdivss opcode.

OP_vdivpd 

IA-32/AMD64 vdivpd opcode.

OP_vdivsd 

IA-32/AMD64 vdivsd opcode.

OP_vmaxps 

IA-32/AMD64 vmaxps opcode.

OP_vmaxss 

IA-32/AMD64 vmaxss opcode.

OP_vmaxpd 

IA-32/AMD64 vmaxpd opcode.

OP_vmaxsd 

IA-32/AMD64 vmaxsd opcode.

OP_vpunpcklbw 

IA-32/AMD64 vpunpcklbw opcode.

OP_vpunpcklwd 

IA-32/AMD64 vpunpcklwd opcode.

OP_vpunpckldq 

IA-32/AMD64 vpunpckldq opcode.

OP_vpacksswb 

IA-32/AMD64 vpacksswb opcode.

OP_vpcmpgtb 

IA-32/AMD64 vpcmpgtb opcode.

OP_vpcmpgtw 

IA-32/AMD64 vpcmpgtw opcode.

OP_vpcmpgtd 

IA-32/AMD64 vpcmpgtd opcode.

OP_vpackuswb 

IA-32/AMD64 vpackuswb opcode.

OP_vpunpckhbw 

IA-32/AMD64 vpunpckhbw opcode.

OP_vpunpckhwd 

IA-32/AMD64 vpunpckhwd opcode.

OP_vpunpckhdq 

IA-32/AMD64 vpunpckhdq opcode.

OP_vpackssdw 

IA-32/AMD64 vpackssdw opcode.

OP_vpunpcklqdq 

IA-32/AMD64 vpunpcklqdq opcode.

OP_vpunpckhqdq 

IA-32/AMD64 vpunpckhqdq opcode.

OP_vmovd 

IA-32/AMD64 vmovd opcode.

OP_vpshufhw 

IA-32/AMD64 vpshufhw opcode.

OP_vpshufd 

IA-32/AMD64 vpshufd opcode.

OP_vpshuflw 

IA-32/AMD64 vpshuflw opcode.

OP_vpcmpeqb 

IA-32/AMD64 vpcmpeqb opcode.

OP_vpcmpeqw 

IA-32/AMD64 vpcmpeqw opcode.

OP_vpcmpeqd 

IA-32/AMD64 vpcmpeqd opcode.

OP_vmovq 

IA-32/AMD64 vmovq opcode.

OP_vcmpps 

IA-32/AMD64 vcmpps opcode.

OP_vcmpss 

IA-32/AMD64 vcmpss opcode.

OP_vcmppd 

IA-32/AMD64 vcmppd opcode.

OP_vcmpsd 

IA-32/AMD64 vcmpsd opcode.

OP_vpinsrw 

IA-32/AMD64 vpinsrw opcode.

OP_vpextrw 

IA-32/AMD64 vpextrw opcode.

OP_vshufps 

IA-32/AMD64 vshufps opcode.

OP_vshufpd 

IA-32/AMD64 vshufpd opcode.

OP_vpsrlw 

IA-32/AMD64 vpsrlw opcode.

OP_vpsrld 

IA-32/AMD64 vpsrld opcode.

OP_vpsrlq 

IA-32/AMD64 vpsrlq opcode.

OP_vpaddq 

IA-32/AMD64 vpaddq opcode.

OP_vpmullw 

IA-32/AMD64 vpmullw opcode.

OP_vpmovmskb 

IA-32/AMD64 vpmovmskb opcode.

OP_vpsubusb 

IA-32/AMD64 vpsubusb opcode.

OP_vpsubusw 

IA-32/AMD64 vpsubusw opcode.

OP_vpminub 

IA-32/AMD64 vpminub opcode.

OP_vpand 

IA-32/AMD64 vpand opcode.

OP_vpaddusb 

IA-32/AMD64 vpaddusb opcode.

OP_vpaddusw 

IA-32/AMD64 vpaddusw opcode.

OP_vpmaxub 

IA-32/AMD64 vpmaxub opcode.

OP_vpandn 

IA-32/AMD64 vpandn opcode.

OP_vpavgb 

IA-32/AMD64 vpavgb opcode.

OP_vpsraw 

IA-32/AMD64 vpsraw opcode.

OP_vpsrad 

IA-32/AMD64 vpsrad opcode.

OP_vpavgw 

IA-32/AMD64 vpavgw opcode.

OP_vpmulhuw 

IA-32/AMD64 vpmulhuw opcode.

OP_vpmulhw 

IA-32/AMD64 vpmulhw opcode.

OP_vcvtdq2pd 

IA-32/AMD64 vcvtdq2pd opcode.

OP_vcvttpd2dq 

IA-32/AMD64 vcvttpd2dq opcode.

OP_vcvtpd2dq 

IA-32/AMD64 vcvtpd2dq opcode.

OP_vmovntdq 

IA-32/AMD64 vmovntdq opcode.

OP_vpsubsb 

IA-32/AMD64 vpsubsb opcode.

OP_vpsubsw 

IA-32/AMD64 vpsubsw opcode.

OP_vpminsw 

IA-32/AMD64 vpminsw opcode.

OP_vpor 

IA-32/AMD64 vpor opcode.

OP_vpaddsb 

IA-32/AMD64 vpaddsb opcode.

OP_vpaddsw 

IA-32/AMD64 vpaddsw opcode.

OP_vpmaxsw 

IA-32/AMD64 vpmaxsw opcode.

OP_vpxor 

IA-32/AMD64 vpxor opcode.

OP_vpsllw 

IA-32/AMD64 vpsllw opcode.

OP_vpslld 

IA-32/AMD64 vpslld opcode.

OP_vpsllq 

IA-32/AMD64 vpsllq opcode.

OP_vpmuludq 

IA-32/AMD64 vpmuludq opcode.

OP_vpmaddwd 

IA-32/AMD64 vpmaddwd opcode.

OP_vpsadbw 

IA-32/AMD64 vpsadbw opcode.

OP_vmaskmovdqu 

IA-32/AMD64 vmaskmovdqu opcode.

OP_vpsubb 

IA-32/AMD64 vpsubb opcode.

OP_vpsubw 

IA-32/AMD64 vpsubw opcode.

OP_vpsubd 

IA-32/AMD64 vpsubd opcode.

OP_vpsubq 

IA-32/AMD64 vpsubq opcode.

OP_vpaddb 

IA-32/AMD64 vpaddb opcode.

OP_vpaddw 

IA-32/AMD64 vpaddw opcode.

OP_vpaddd 

IA-32/AMD64 vpaddd opcode.

OP_vpsrldq 

IA-32/AMD64 vpsrldq opcode.

OP_vpslldq 

IA-32/AMD64 vpslldq opcode.

OP_vmovdqu 

IA-32/AMD64 vmovdqu opcode.

OP_vmovdqa 

IA-32/AMD64 vmovdqa opcode.

OP_vhaddpd 

IA-32/AMD64 vhaddpd opcode.

OP_vhaddps 

IA-32/AMD64 vhaddps opcode.

OP_vhsubpd 

IA-32/AMD64 vhsubpd opcode.

OP_vhsubps 

IA-32/AMD64 vhsubps opcode.

OP_vaddsubpd 

IA-32/AMD64 vaddsubpd opcode.

OP_vaddsubps 

IA-32/AMD64 vaddsubps opcode.

OP_vlddqu 

IA-32/AMD64 vlddqu opcode.

OP_vpshufb 

IA-32/AMD64 vpshufb opcode.

OP_vphaddw 

IA-32/AMD64 vphaddw opcode.

OP_vphaddd 

IA-32/AMD64 vphaddd opcode.

OP_vphaddsw 

IA-32/AMD64 vphaddsw opcode.

OP_vpmaddubsw 

IA-32/AMD64 vpmaddubsw opcode.

OP_vphsubw 

IA-32/AMD64 vphsubw opcode.

OP_vphsubd 

IA-32/AMD64 vphsubd opcode.

OP_vphsubsw 

IA-32/AMD64 vphsubsw opcode.

OP_vpsignb 

IA-32/AMD64 vpsignb opcode.

OP_vpsignw 

IA-32/AMD64 vpsignw opcode.

OP_vpsignd 

IA-32/AMD64 vpsignd opcode.

OP_vpmulhrsw 

IA-32/AMD64 vpmulhrsw opcode.

OP_vpabsb 

IA-32/AMD64 vpabsb opcode.

OP_vpabsw 

IA-32/AMD64 vpabsw opcode.

OP_vpabsd 

IA-32/AMD64 vpabsd opcode.

OP_vpalignr 

IA-32/AMD64 vpalignr opcode.

OP_vpblendvb 

IA-32/AMD64 vpblendvb opcode.

OP_vblendvps 

IA-32/AMD64 vblendvps opcode.

OP_vblendvpd 

IA-32/AMD64 vblendvpd opcode.

OP_vptest 

IA-32/AMD64 vptest opcode.

OP_vpmovsxbw 

IA-32/AMD64 vpmovsxbw opcode.

OP_vpmovsxbd 

IA-32/AMD64 vpmovsxbd opcode.

OP_vpmovsxbq 

IA-32/AMD64 vpmovsxbq opcode.

OP_vpmovsxwd 

IA-32/AMD64 vpmovsxwd opcode.

OP_vpmovsxwq 

IA-32/AMD64 vpmovsxwq opcode.

OP_vpmovsxdq 

IA-32/AMD64 vpmovsxdq opcode.

OP_vpmuldq 

IA-32/AMD64 vpmuldq opcode.

OP_vpcmpeqq 

IA-32/AMD64 vpcmpeqq opcode.

OP_vmovntdqa 

IA-32/AMD64 vmovntdqa opcode.

OP_vpackusdw 

IA-32/AMD64 vpackusdw opcode.

OP_vpmovzxbw 

IA-32/AMD64 vpmovzxbw opcode.

OP_vpmovzxbd 

IA-32/AMD64 vpmovzxbd opcode.

OP_vpmovzxbq 

IA-32/AMD64 vpmovzxbq opcode.

OP_vpmovzxwd 

IA-32/AMD64 vpmovzxwd opcode.

OP_vpmovzxwq 

IA-32/AMD64 vpmovzxwq opcode.

OP_vpmovzxdq 

IA-32/AMD64 vpmovzxdq opcode.

OP_vpcmpgtq 

IA-32/AMD64 vpcmpgtq opcode.

OP_vpminsb 

IA-32/AMD64 vpminsb opcode.

OP_vpminsd 

IA-32/AMD64 vpminsd opcode.

OP_vpminuw 

IA-32/AMD64 vpminuw opcode.

OP_vpminud 

IA-32/AMD64 vpminud opcode.

OP_vpmaxsb 

IA-32/AMD64 vpmaxsb opcode.

OP_vpmaxsd 

IA-32/AMD64 vpmaxsd opcode.

OP_vpmaxuw 

IA-32/AMD64 vpmaxuw opcode.

OP_vpmaxud 

IA-32/AMD64 vpmaxud opcode.

OP_vpmulld 

IA-32/AMD64 vpmulld opcode.

OP_vphminposuw 

IA-32/AMD64 vphminposuw opcode.

OP_vaesimc 

IA-32/AMD64 vaesimc opcode.

OP_vaesenc 

IA-32/AMD64 vaesenc opcode.

OP_vaesenclast 

IA-32/AMD64 vaesenclast opcode.

OP_vaesdec 

IA-32/AMD64 vaesdec opcode.

OP_vaesdeclast 

IA-32/AMD64 vaesdeclast opcode.

OP_vpextrb 

IA-32/AMD64 vpextrb opcode.

OP_vpextrd 

IA-32/AMD64 vpextrd opcode.

OP_vextractps 

IA-32/AMD64 vextractps opcode.

OP_vroundps 

IA-32/AMD64 vroundps opcode.

OP_vroundpd 

IA-32/AMD64 vroundpd opcode.

OP_vroundss 

IA-32/AMD64 vroundss opcode.

OP_vroundsd 

IA-32/AMD64 vroundsd opcode.

OP_vblendps 

IA-32/AMD64 vblendps opcode.

OP_vblendpd 

IA-32/AMD64 vblendpd opcode.

OP_vpblendw 

IA-32/AMD64 vpblendw opcode.

OP_vpinsrb 

IA-32/AMD64 vpinsrb opcode.

OP_vinsertps 

IA-32/AMD64 vinsertps opcode.

OP_vpinsrd 

IA-32/AMD64 vpinsrd opcode.

OP_vdpps 

IA-32/AMD64 vdpps opcode.

OP_vdppd 

IA-32/AMD64 vdppd opcode.

OP_vmpsadbw 

IA-32/AMD64 vmpsadbw opcode.

OP_vpcmpestrm 

IA-32/AMD64 vpcmpestrm opcode.

OP_vpcmpestri 

IA-32/AMD64 vpcmpestri opcode.

OP_vpcmpistrm 

IA-32/AMD64 vpcmpistrm opcode.

OP_vpcmpistri 

IA-32/AMD64 vpcmpistri opcode.

OP_vpclmulqdq 

IA-32/AMD64 vpclmulqdq opcode.

OP_vaeskeygenassist 

IA-32/AMD64 vaeskeygenassist opcode.

OP_vtestps 

IA-32/AMD64 vtestps opcode.

OP_vtestpd 

IA-32/AMD64 vtestpd opcode.

OP_vzeroupper 

IA-32/AMD64 vzeroupper opcode.

OP_vzeroall 

IA-32/AMD64 vzeroall opcode.

OP_vldmxcsr 

IA-32/AMD64 vldmxcsr opcode.

OP_vstmxcsr 

IA-32/AMD64 vstmxcsr opcode.

OP_vbroadcastss 

IA-32/AMD64 vbroadcastss opcode.

OP_vbroadcastsd 

IA-32/AMD64 vbroadcastsd opcode.

OP_vbroadcastf128 

IA-32/AMD64 vbroadcastf128 opcode.

OP_vmaskmovps 

IA-32/AMD64 vmaskmovps opcode.

OP_vmaskmovpd 

IA-32/AMD64 vmaskmovpd opcode.

OP_vpermilps 

IA-32/AMD64 vpermilps opcode.

OP_vpermilpd 

IA-32/AMD64 vpermilpd opcode.

OP_vperm2f128 

IA-32/AMD64 vperm2f128 opcode.

OP_vinsertf128 

IA-32/AMD64 vinsertf128 opcode.

OP_vextractf128 

IA-32/AMD64 vextractf128 opcode.

OP_vcvtph2ps 

IA-32/AMD64 vcvtph2ps opcode.

OP_vcvtps2ph 

IA-32/AMD64 vcvtps2ph opcode.

OP_vfmadd132ps 

IA-32/AMD64 vfmadd132ps opcode.

OP_vfmadd132pd 

IA-32/AMD64 vfmadd132pd opcode.

OP_vfmadd213ps 

IA-32/AMD64 vfmadd213ps opcode.

OP_vfmadd213pd 

IA-32/AMD64 vfmadd213pd opcode.

OP_vfmadd231ps 

IA-32/AMD64 vfmadd231ps opcode.

OP_vfmadd231pd 

IA-32/AMD64 vfmadd231pd opcode.

OP_vfmadd132ss 

IA-32/AMD64 vfmadd132ss opcode.

OP_vfmadd132sd 

IA-32/AMD64 vfmadd132sd opcode.

OP_vfmadd213ss 

IA-32/AMD64 vfmadd213ss opcode.

OP_vfmadd213sd 

IA-32/AMD64 vfmadd213sd opcode.

OP_vfmadd231ss 

IA-32/AMD64 vfmadd231ss opcode.

OP_vfmadd231sd 

IA-32/AMD64 vfmadd231sd opcode.

OP_vfmaddsub132ps 

IA-32/AMD64 vfmaddsub132ps opcode.

OP_vfmaddsub132pd 

IA-32/AMD64 vfmaddsub132pd opcode.

OP_vfmaddsub213ps 

IA-32/AMD64 vfmaddsub213ps opcode.

OP_vfmaddsub213pd 

IA-32/AMD64 vfmaddsub213pd opcode.

OP_vfmaddsub231ps 

IA-32/AMD64 vfmaddsub231ps opcode.

OP_vfmaddsub231pd 

IA-32/AMD64 vfmaddsub231pd opcode.

OP_vfmsubadd132ps 

IA-32/AMD64 vfmsubadd132ps opcode.

OP_vfmsubadd132pd 

IA-32/AMD64 vfmsubadd132pd opcode.

OP_vfmsubadd213ps 

IA-32/AMD64 vfmsubadd213ps opcode.

OP_vfmsubadd213pd 

IA-32/AMD64 vfmsubadd213pd opcode.

OP_vfmsubadd231ps 

IA-32/AMD64 vfmsubadd231ps opcode.

OP_vfmsubadd231pd 

IA-32/AMD64 vfmsubadd231pd opcode.

OP_vfmsub132ps 

IA-32/AMD64 vfmsub132ps opcode.

OP_vfmsub132pd 

IA-32/AMD64 vfmsub132pd opcode.

OP_vfmsub213ps 

IA-32/AMD64 vfmsub213ps opcode.

OP_vfmsub213pd 

IA-32/AMD64 vfmsub213pd opcode.

OP_vfmsub231ps 

IA-32/AMD64 vfmsub231ps opcode.

OP_vfmsub231pd 

IA-32/AMD64 vfmsub231pd opcode.

OP_vfmsub132ss 

IA-32/AMD64 vfmsub132ss opcode.

OP_vfmsub132sd 

IA-32/AMD64 vfmsub132sd opcode.

OP_vfmsub213ss 

IA-32/AMD64 vfmsub213ss opcode.

OP_vfmsub213sd 

IA-32/AMD64 vfmsub213sd opcode.

OP_vfmsub231ss 

IA-32/AMD64 vfmsub231ss opcode.

OP_vfmsub231sd 

IA-32/AMD64 vfmsub231sd opcode.

OP_vfnmadd132ps 

IA-32/AMD64 vfnmadd132ps opcode.

OP_vfnmadd132pd 

IA-32/AMD64 vfnmadd132pd opcode.

OP_vfnmadd213ps 

IA-32/AMD64 vfnmadd213ps opcode.

OP_vfnmadd213pd 

IA-32/AMD64 vfnmadd213pd opcode.

OP_vfnmadd231ps 

IA-32/AMD64 vfnmadd231ps opcode.

OP_vfnmadd231pd 

IA-32/AMD64 vfnmadd231pd opcode.

OP_vfnmadd132ss 

IA-32/AMD64 vfnmadd132ss opcode.

OP_vfnmadd132sd 

IA-32/AMD64 vfnmadd132sd opcode.

OP_vfnmadd213ss 

IA-32/AMD64 vfnmadd213ss opcode.

OP_vfnmadd213sd 

IA-32/AMD64 vfnmadd213sd opcode.

OP_vfnmadd231ss 

IA-32/AMD64 vfnmadd231ss opcode.

OP_vfnmadd231sd 

IA-32/AMD64 vfnmadd231sd opcode.

OP_vfnmsub132ps 

IA-32/AMD64 vfnmsub132ps opcode.

OP_vfnmsub132pd 

IA-32/AMD64 vfnmsub132pd opcode.

OP_vfnmsub213ps 

IA-32/AMD64 vfnmsub213ps opcode.

OP_vfnmsub213pd 

IA-32/AMD64 vfnmsub213pd opcode.

OP_vfnmsub231ps 

IA-32/AMD64 vfnmsub231ps opcode.

OP_vfnmsub231pd 

IA-32/AMD64 vfnmsub231pd opcode.

OP_vfnmsub132ss 

IA-32/AMD64 vfnmsub132ss opcode.

OP_vfnmsub132sd 

IA-32/AMD64 vfnmsub132sd opcode.

OP_vfnmsub213ss 

IA-32/AMD64 vfnmsub213ss opcode.

OP_vfnmsub213sd 

IA-32/AMD64 vfnmsub213sd opcode.

OP_vfnmsub231ss 

IA-32/AMD64 vfnmsub231ss opcode.

OP_vfnmsub231sd 

IA-32/AMD64 vfnmsub231sd opcode.

OP_movq2dq 

IA-32/AMD64 movq2dq opcode.

OP_movdq2q 

IA-32/AMD64 movdq2q opcode.

OP_fxsave64 

IA-32/AMD64 fxsave64 opcode.

OP_fxrstor64 

IA-32/AMD64 fxrstor64 opcode.

OP_xsave64 

IA-32/AMD64 xsave64 opcode.

OP_xrstor64 

IA-32/AMD64 xrstor64 opcode.

OP_xsaveopt64 

IA-32/AMD64 xsaveopt64 opcode.

OP_rdrand 

IA-32/AMD64 rdrand opcode.

OP_rdfsbase 

IA-32/AMD64 rdfsbase opcode.

OP_rdgsbase 

IA-32/AMD64 rdgsbase opcode.

OP_wrfsbase 

IA-32/AMD64 wrfsbase opcode.

OP_wrgsbase 

IA-32/AMD64 wrgsbase opcode.

OP_rdseed 

IA-32/AMD64 rdseed opcode.

OP_vfmaddsubps 

IA-32/AMD64 vfmaddsubps opcode.

OP_vfmaddsubpd 

IA-32/AMD64 vfmaddsubpd opcode.

OP_vfmsubaddps 

IA-32/AMD64 vfmsubaddps opcode.

OP_vfmsubaddpd 

IA-32/AMD64 vfmsubaddpd opcode.

OP_vfmaddps 

IA-32/AMD64 vfmaddps opcode.

OP_vfmaddpd 

IA-32/AMD64 vfmaddpd opcode.

OP_vfmaddss 

IA-32/AMD64 vfmaddss opcode.

OP_vfmaddsd 

IA-32/AMD64 vfmaddsd opcode.

OP_vfmsubps 

IA-32/AMD64 vfmsubps opcode.

OP_vfmsubpd 

IA-32/AMD64 vfmsubpd opcode.

OP_vfmsubss 

IA-32/AMD64 vfmsubss opcode.

OP_vfmsubsd 

IA-32/AMD64 vfmsubsd opcode.

OP_vfnmaddps 

IA-32/AMD64 vfnmaddps opcode.

OP_vfnmaddpd 

IA-32/AMD64 vfnmaddpd opcode.

OP_vfnmaddss 

IA-32/AMD64 vfnmaddss opcode.

OP_vfnmaddsd 

IA-32/AMD64 vfnmaddsd opcode.

OP_vfnmsubps 

IA-32/AMD64 vfnmsubps opcode.

OP_vfnmsubpd 

IA-32/AMD64 vfnmsubpd opcode.

OP_vfnmsubss 

IA-32/AMD64 vfnmsubss opcode.

OP_vfnmsubsd 

IA-32/AMD64 vfnmsubsd opcode.

OP_vfrczps 

IA-32/AMD64 vfrczps opcode.

OP_vfrczpd 

IA-32/AMD64 vfrczpd opcode.

OP_vfrczss 

IA-32/AMD64 vfrczss opcode.

OP_vfrczsd 

IA-32/AMD64 vfrczsd opcode.

OP_vpcmov 

IA-32/AMD64 vpcmov opcode.

OP_vpcomb 

IA-32/AMD64 vpcomb opcode.

OP_vpcomw 

IA-32/AMD64 vpcomw opcode.

OP_vpcomd 

IA-32/AMD64 vpcomd opcode.

OP_vpcomq 

IA-32/AMD64 vpcomq opcode.

OP_vpcomub 

IA-32/AMD64 vpcomub opcode.

OP_vpcomuw 

IA-32/AMD64 vpcomuw opcode.

OP_vpcomud 

IA-32/AMD64 vpcomud opcode.

OP_vpcomuq 

IA-32/AMD64 vpcomuq opcode.

OP_vpermil2pd 

IA-32/AMD64 vpermil2pd opcode.

OP_vpermil2ps 

IA-32/AMD64 vpermil2ps opcode.

OP_vphaddbw 

IA-32/AMD64 vphaddbw opcode.

OP_vphaddbd 

IA-32/AMD64 vphaddbd opcode.

OP_vphaddbq 

IA-32/AMD64 vphaddbq opcode.

OP_vphaddwd 

IA-32/AMD64 vphaddwd opcode.

OP_vphaddwq 

IA-32/AMD64 vphaddwq opcode.

OP_vphadddq 

IA-32/AMD64 vphadddq opcode.

OP_vphaddubw 

IA-32/AMD64 vphaddubw opcode.

OP_vphaddubd 

IA-32/AMD64 vphaddubd opcode.

OP_vphaddubq 

IA-32/AMD64 vphaddubq opcode.

OP_vphadduwd 

IA-32/AMD64 vphadduwd opcode.

OP_vphadduwq 

IA-32/AMD64 vphadduwq opcode.

OP_vphaddudq 

IA-32/AMD64 vphaddudq opcode.

OP_vphsubbw 

IA-32/AMD64 vphsubbw opcode.

OP_vphsubwd 

IA-32/AMD64 vphsubwd opcode.

OP_vphsubdq 

IA-32/AMD64 vphsubdq opcode.

OP_vpmacssww 

IA-32/AMD64 vpmacssww opcode.

OP_vpmacsswd 

IA-32/AMD64 vpmacsswd opcode.

OP_vpmacssdql 

IA-32/AMD64 vpmacssdql opcode.

OP_vpmacssdd 

IA-32/AMD64 vpmacssdd opcode.

OP_vpmacssdqh 

IA-32/AMD64 vpmacssdqh opcode.

OP_vpmacsww 

IA-32/AMD64 vpmacsww opcode.

OP_vpmacswd 

IA-32/AMD64 vpmacswd opcode.

OP_vpmacsdql 

IA-32/AMD64 vpmacsdql opcode.

OP_vpmacsdd 

IA-32/AMD64 vpmacsdd opcode.

OP_vpmacsdqh 

IA-32/AMD64 vpmacsdqh opcode.

OP_vpmadcsswd 

IA-32/AMD64 vpmadcsswd opcode.

OP_vpmadcswd 

IA-32/AMD64 vpmadcswd opcode.

OP_vpperm 

IA-32/AMD64 vpperm opcode.

OP_vprotb 

IA-32/AMD64 vprotb opcode.

OP_vprotw 

IA-32/AMD64 vprotw opcode.

OP_vprotd 

IA-32/AMD64 vprotd opcode.

OP_vprotq 

IA-32/AMD64 vprotq opcode.

OP_vpshlb 

IA-32/AMD64 vpshlb opcode.

OP_vpshlw 

IA-32/AMD64 vpshlw opcode.

OP_vpshld 

IA-32/AMD64 vpshld opcode.

OP_vpshlq 

IA-32/AMD64 vpshlq opcode.

OP_vpshab 

IA-32/AMD64 vpshab opcode.

OP_vpshaw 

IA-32/AMD64 vpshaw opcode.

OP_vpshad 

IA-32/AMD64 vpshad opcode.

OP_vpshaq 

IA-32/AMD64 vpshaq opcode.

OP_bextr 

IA-32/AMD64 bextr opcode.

OP_blcfill 

IA-32/AMD64 blcfill opcode.

OP_blci 

IA-32/AMD64 blci opcode.

OP_blcic 

IA-32/AMD64 blcic opcode.

OP_blcmsk 

IA-32/AMD64 blcmsk opcode.

OP_blcs 

IA-32/AMD64 blcs opcode.

OP_blsfill 

IA-32/AMD64 blsfill opcode.

OP_blsic 

IA-32/AMD64 blsic opcode.

OP_t1mskc 

IA-32/AMD64 t1mskc opcode.

OP_tzmsk 

IA-32/AMD64 tzmsk opcode.

OP_llwpcb 

IA-32/AMD64 llwpcb opcode.

OP_slwpcb 

IA-32/AMD64 slwpcb opcode.

OP_lwpins 

IA-32/AMD64 lwpins opcode.

OP_lwpval 

IA-32/AMD64 lwpval opcode.

OP_andn 

IA-32/AMD64 andn opcode.

OP_blsr 

IA-32/AMD64 blsr opcode.

OP_blsmsk 

IA-32/AMD64 blsmsk opcode.

OP_blsi 

IA-32/AMD64 blsi opcode.

OP_tzcnt 

IA-32/AMD64 tzcnt opcode.

OP_bzhi 

IA-32/AMD64 bzhi opcode.

OP_pext 

IA-32/AMD64 pext opcode.

OP_pdep 

IA-32/AMD64 pdep opcode.

OP_sarx 

IA-32/AMD64 sarx opcode.

OP_shlx 

IA-32/AMD64 shlx opcode.

OP_shrx 

IA-32/AMD64 shrx opcode.

OP_rorx 

IA-32/AMD64 rorx opcode.

OP_mulx 

IA-32/AMD64 mulx opcode.

OP_getsec 

IA-32/AMD64 getsec opcode.

OP_vmfunc 

IA-32/AMD64 vmfunc opcode.

OP_invpcid 

IA-32/AMD64 invpcid opcode.

OP_xabort 

IA-32/AMD64 xabort opcode.

OP_xbegin 

IA-32/AMD64 xbegin opcode.

OP_xend 

IA-32/AMD64 xend opcode.

OP_xtest 

IA-32/AMD64 xtest opcode.

OP_vpgatherdd 

IA-32/AMD64 vpgatherdd opcode.

OP_vpgatherdq 

IA-32/AMD64 vpgatherdq opcode.

OP_vpgatherqd 

IA-32/AMD64 vpgatherqd opcode.

OP_vpgatherqq 

IA-32/AMD64 vpgatherqq opcode.

OP_vgatherdps 

IA-32/AMD64 vgatherdps opcode.

OP_vgatherdpd 

IA-32/AMD64 vgatherdpd opcode.

OP_vgatherqps 

IA-32/AMD64 vgatherqps opcode.

OP_vgatherqpd 

IA-32/AMD64 vgatherqpd opcode.

OP_vbroadcasti128 

IA-32/AMD64 vbroadcasti128 opcode.

OP_vinserti128 

IA-32/AMD64 vinserti128 opcode.

OP_vextracti128 

IA-32/AMD64 vextracti128 opcode.

OP_vpmaskmovd 

IA-32/AMD64 vpmaskmovd opcode.

OP_vpmaskmovq 

IA-32/AMD64 vpmaskmovq opcode.

OP_vperm2i128 

IA-32/AMD64 vperm2i128 opcode.

OP_vpermd 

IA-32/AMD64 vpermd opcode.

OP_vpermps 

IA-32/AMD64 vpermps opcode.

OP_vpermq 

IA-32/AMD64 vpermq opcode.

OP_vpermpd 

IA-32/AMD64 vpermpd opcode.

OP_vpblendd 

IA-32/AMD64 vpblendd opcode.

OP_vpsllvd 

IA-32/AMD64 vpsllvd opcode.

OP_vpsllvq 

IA-32/AMD64 vpsllvq opcode.

OP_vpsravd 

IA-32/AMD64 vpsravd opcode.

OP_vpsrlvd 

IA-32/AMD64 vpsrlvd opcode.

OP_vpsrlvq 

IA-32/AMD64 vpsrlvq opcode.

OP_vpbroadcastb 

IA-32/AMD64 vpbroadcastb opcode.

OP_vpbroadcastw 

IA-32/AMD64 vpbroadcastw opcode.

OP_vpbroadcastd 

IA-32/AMD64 vpbroadcastd opcode.

OP_vpbroadcastq 

IA-32/AMD64 vpbroadcastq opcode.

OP_xsavec32 

IA-32/AMD64 xsavec opcode.

OP_xsavec64 

IA-32/AMD64 xsavec64 opcode.

OP_adox 

IA-32/AMD64 adox opcode.

OP_adcx 

IA-32/AMD64 adox opcode.

OP_kmovw 

IA-32/AMD64 AVX-512 kmovw opcode.

OP_kmovb 

IA-32/AMD64 AVX-512 kmovb opcode.

OP_kmovq 

IA-32/AMD64 AVX-512 kmovq opcode.

OP_kmovd 

IA-32/AMD64 AVX-512 kmovd opcode.

OP_kandw 

IA-32/AMD64 AVX-512 kandw opcode.

OP_kandb 

IA-32/AMD64 AVX-512 kandb opcode.

OP_kandq 

IA-32/AMD64 AVX-512 kandq opcode.

OP_kandd 

IA-32/AMD64 AVX-512 kandd opcode.

OP_kandnw 

IA-32/AMD64 AVX-512 kandnw opcode.

OP_kandnb 

IA-32/AMD64 AVX-512 kandnb opcode.

OP_kandnq 

IA-32/AMD64 AVX-512 kandnq opcode.

OP_kandnd 

IA-32/AMD64 AVX-512 kandnd opcode.

OP_kunpckbw 

IA-32/AMD64 AVX-512 kunpckbw opcode.

OP_kunpckwd 

IA-32/AMD64 AVX-512 kunpckwd opcode.

OP_kunpckdq 

IA-32/AMD64 AVX-512 kunpckdq opcode.

OP_knotw 

IA-32/AMD64 AVX-512 knotw opcode.

OP_knotb 

IA-32/AMD64 AVX-512 knotb opcode.

OP_knotq 

IA-32/AMD64 AVX-512 knotq opcode.

OP_knotd 

IA-32/AMD64 AVX-512 knotd opcode.

OP_korw 

IA-32/AMD64 AVX-512 korw opcode.

OP_korb 

IA-32/AMD64 AVX-512 korb opcode.

OP_korq 

IA-32/AMD64 AVX-512 korq opcode.

OP_kord 

IA-32/AMD64 AVX-512 kord opcode.

OP_kxnorw 

IA-32/AMD64 AVX-512 kxnorw opcode.

OP_kxnorb 

IA-32/AMD64 AVX-512 kxnorb opcode.

OP_kxnorq 

IA-32/AMD64 AVX-512 kxnorq opcode.

OP_kxnord 

IA-32/AMD64 AVX-512 kxnord opcode.

OP_kxorw 

IA-32/AMD64 AVX-512 kxorw opcode.

OP_kxorb 

IA-32/AMD64 AVX-512 kxorb opcode.

OP_kxorq 

IA-32/AMD64 AVX-512 kxorq opcode.

OP_kxord 

IA-32/AMD64 AVX-512 kxord opcode.

OP_kaddw 

IA-32/AMD64 AVX-512 kaddw opcode.

OP_kaddb 

IA-32/AMD64 AVX-512 kaddb opcode.

OP_kaddq 

IA-32/AMD64 AVX-512 kaddq opcode.

OP_kaddd 

IA-32/AMD64 AVX-512 kaddd opcode.

OP_kortestw 

IA-32/AMD64 AVX-512 kortestw opcode.

OP_kortestb 

IA-32/AMD64 AVX-512 kortestb opcode.

OP_kortestq 

IA-32/AMD64 AVX-512 kortestq opcode.

OP_kortestd 

IA-32/AMD64 AVX-512 kortestd opcode.

OP_kshiftlw 

IA-32/AMD64 AVX-512 kshiftlw opcode.

OP_kshiftlb 

IA-32/AMD64 AVX-512 kshiftlb opcode.

OP_kshiftlq 

IA-32/AMD64 AVX-512 kshiftlq opcode.

OP_kshiftld 

IA-32/AMD64 AVX-512 kshiftld opcode.

OP_kshiftrw 

IA-32/AMD64 AVX-512 kshiftrw opcode.

OP_kshiftrb 

IA-32/AMD64 AVX-512 kshiftrb opcode.

OP_kshiftrq 

IA-32/AMD64 AVX-512 kshiftrq opcode.

OP_kshiftrd 

IA-32/AMD64 AVX-512 kshiftrd opcode.

OP_ktestw 

IA-32/AMD64 AVX-512 ktestd opcode.

OP_ktestb 

IA-32/AMD64 AVX-512 ktestd opcode.

OP_ktestq 

IA-32/AMD64 AVX-512 ktestd opcode.

OP_ktestd 

IA-32/AMD64 AVX-512 ktestd opcode.

OP_valignd 

IA-32/AMD64 AVX-512 OP_valignd opcode.

OP_valignq 

IA-32/AMD64 AVX-512 OP_valignq opcode.

OP_vblendmpd 

IA-32/AMD64 AVX-512 OP_vblendmpd opcode.

OP_vblendmps 

IA-32/AMD64 AVX-512 OP_vblendmps opcode.

OP_vbroadcastf32x2 

IA-32/AMD64 AVX-512 OP_vbroadcastf32x2 opcode.

OP_vbroadcastf32x4 

IA-32/AMD64 AVX-512 OP_vbroadcastf32x4 opcode.

OP_vbroadcastf32x8 

IA-32/AMD64 AVX-512 OP_vbroadcastf32x8 opcode.

OP_vbroadcastf64x2 

IA-32/AMD64 AVX-512 OP_vbroadcastf64x2 opcode.

OP_vbroadcastf64x4 

IA-32/AMD64 AVX-512 OP_vbroadcastf64x4 opcode.

OP_vbroadcasti32x2 

IA-32/AMD64 AVX-512 OP_vbroadcasti32x2 opcode.

OP_vbroadcasti32x4 

IA-32/AMD64 AVX-512 OP_vbroadcasti32x4 opcode.

OP_vbroadcasti32x8 

IA-32/AMD64 AVX-512 OP_vbroadcasti32x8 opcode.

OP_vbroadcasti64x2 

IA-32/AMD64 AVX-512 OP_vbroadcasti64x2 opcode.

OP_vbroadcasti64x4 

IA-32/AMD64 AVX-512 OP_vbroadcasti64x4 opcode.

OP_vcompresspd 

IA-32/AMD64 AVX-512 OP_vcompresspd opcode.

OP_vcompressps 

IA-32/AMD64 AVX-512 OP_vcompressps opcode.

OP_vcvtpd2qq 

IA-32/AMD64 AVX-512 OP_vcvtpd2qq opcode.

OP_vcvtpd2udq 

IA-32/AMD64 AVX-512 OP_vcvtpd2udq opcode.

OP_vcvtpd2uqq 

IA-32/AMD64 AVX-512 OP_vcvtpd2uqq opcode.

OP_vcvtps2qq 

IA-32/AMD64 AVX-512 OP_vcvtps2qq opcode.

OP_vcvtps2udq 

IA-32/AMD64 AVX-512 OP_vcvtps2udq opcode.

OP_vcvtps2uqq 

IA-32/AMD64 AVX-512 OP_vcvtps2uqq opcode.

OP_vcvtqq2pd 

IA-32/AMD64 AVX-512 OP_vcvtqq2pd opcode.

OP_vcvtqq2ps 

IA-32/AMD64 AVX-512 OP_vcvtqq2ps opcode.

OP_vcvtsd2usi 

IA-32/AMD64 AVX-512 OP_vcvtsd2usi opcode.

OP_vcvtss2usi 

IA-32/AMD64 AVX-512 OP_vcvtss2usi opcode.

OP_vcvttpd2qq 

IA-32/AMD64 AVX-512 OP_vcvttpd2qq opcode.

OP_vcvttpd2udq 

IA-32/AMD64 AVX-512 OP_vcvttpd2udq opcode.

OP_vcvttpd2uqq 

IA-32/AMD64 AVX-512 OP_vcvttpd2uqq opcode.

OP_vcvttps2qq 

IA-32/AMD64 AVX-512 OP_vcvttps2qq opcode.

OP_vcvttps2udq 

IA-32/AMD64 AVX-512 OP_vcvttps2udq opcode.

OP_vcvttps2uqq 

IA-32/AMD64 AVX-512 OP_vcvttps2uqq opcode.

OP_vcvttsd2usi 

IA-32/AMD64 AVX-512 OP_vcvttsd2usi opcode.

OP_vcvttss2usi 

IA-32/AMD64 AVX-512 OP_vcvttss2usi opcode.

OP_vcvtudq2pd 

IA-32/AMD64 AVX-512 OP_vcvtudq2pd opcode.

OP_vcvtudq2ps 

IA-32/AMD64 AVX-512 OP_vcvtudq2ps opcode.

OP_vcvtuqq2pd 

IA-32/AMD64 AVX-512 OP_vcvtuqq2pd opcode.

OP_vcvtuqq2ps 

IA-32/AMD64 AVX-512 OP_vcvtuqq2ps opcode.

OP_vcvtusi2sd 

IA-32/AMD64 AVX-512 OP_vcvtusi2sd opcode.

OP_vcvtusi2ss 

IA-32/AMD64 AVX-512 OP_vcvtusi2ss opcode.

OP_vdbpsadbw 

IA-32/AMD64 AVX-512 OP_vdbpsadbw opcode.

OP_vexp2pd 

IA-32/AMD64 AVX-512 OP_vexp2pd opcode.

OP_vexp2ps 

IA-32/AMD64 AVX-512 OP_vexp2ps opcode.

OP_vexpandpd 

IA-32/AMD64 AVX-512 OP_vexpandpd opcode.

OP_vexpandps 

IA-32/AMD64 AVX-512 OP_vexpandps opcode.

OP_vextractf32x4 

IA-32/AMD64 AVX-512 OP_vextractf32x4 opcode.

OP_vextractf32x8 

IA-32/AMD64 AVX-512 OP_vextractf32x8 opcode.

OP_vextractf64x2 

IA-32/AMD64 AVX-512 OP_vextractf64x2 opcode.

OP_vextractf64x4 

IA-32/AMD64 AVX-512 OP_vextractf64x4 opcode.

OP_vextracti32x4 

IA-32/AMD64 AVX-512 OP_vextracti32x4 opcode.

OP_vextracti32x8 

IA-32/AMD64 AVX-512 OP_vextracti32x8 opcode.

OP_vextracti64x2 

IA-32/AMD64 AVX-512 OP_vextracti64x2 opcode.

OP_vextracti64x4 

IA-32/AMD64 AVX-512 OP_vextracti64x4 opcode.

OP_vfixupimmpd 

IA-32/AMD64 AVX-512 OP_vfixupimmpd opcode.

OP_vfixupimmps 

IA-32/AMD64 AVX-512 OP_vfixupimmps opcode.

OP_vfixupimmsd 

IA-32/AMD64 AVX-512 OP_vfixupimmsd opcode.

OP_vfixupimmss 

IA-32/AMD64 AVX-512 OP_vfixupimmss opcode.

OP_vfpclasspd 

IA-32/AMD64 AVX-512 OP_vfpclasspd opcode.

OP_vfpclassps 

IA-32/AMD64 AVX-512 OP_vfpclassps opcode.

OP_vfpclasssd 

IA-32/AMD64 AVX-512 OP_vfpclasssd opcode.

OP_vfpclassss 

IA-32/AMD64 AVX-512 OP_vfpclassss opcode.

OP_vgatherpf0dpd 

IA-32/AMD64 AVX-512 OP_vgatherpf0dps opcode.

OP_vgatherpf0dps 

IA-32/AMD64 AVX-512 OP_vgatherpf0dps opcode.

OP_vgatherpf0qpd 

IA-32/AMD64 AVX-512 OP_vgatherpf0qpd opcode.

OP_vgatherpf0qps 

IA-32/AMD64 AVX-512 OP_vgatherpf0qps opcode.

OP_vgatherpf1dpd 

IA-32/AMD64 AVX-512 OP_vgatherpf1dpd opcode.

OP_vgatherpf1dps 

IA-32/AMD64 AVX-512 OP_vgatherpf1dps opcode.

OP_vgatherpf1qpd 

IA-32/AMD64 AVX-512 OP_vgatherpf1qpd opcode.

OP_vgatherpf1qps 

IA-32/AMD64 AVX-512 OP_vgatherpf1qps opcode.

OP_vgetexppd 

IA-32/AMD64 AVX-512 OP_vgetexppd opcode.

OP_vgetexpps 

IA-32/AMD64 AVX-512 OP_vgetexpps opcode.

OP_vgetexpsd 

IA-32/AMD64 AVX-512 OP_vgetexpsd opcode.

OP_vgetexpss 

IA-32/AMD64 AVX-512 OP_vgetexpss opcode.

OP_vgetmantpd 

IA-32/AMD64 AVX-512 OP_vgetmantpd opcode.

OP_vgetmantps 

IA-32/AMD64 AVX-512 OP_vgetmantps opcode.

OP_vgetmantsd 

IA-32/AMD64 AVX-512 OP_vgetmantsd opcode.

OP_vgetmantss 

IA-32/AMD64 AVX-512 OP_vgetmantss opcode.

OP_vinsertf32x4 

IA-32/AMD64 AVX-512 OP_vinsertf32x4 opcode.

OP_vinsertf32x8 

IA-32/AMD64 AVX-512 OP_vinsertf32x8 opcode.

OP_vinsertf64x2 

IA-32/AMD64 AVX-512 OP_vinsertf64x2 opcode.

OP_vinsertf64x4 

IA-32/AMD64 AVX-512 OP_vinsertf64x4 opcode.

OP_vinserti32x4 

IA-32/AMD64 AVX-512 OP_vinserti32x4 opcode.

OP_vinserti32x8 

IA-32/AMD64 AVX-512 OP_vinserti32x8 opcode.

OP_vinserti64x2 

IA-32/AMD64 AVX-512 OP_vinserti64x2 opcode.

OP_vinserti64x4 

IA-32/AMD64 AVX-512 OP_vinserti64x4 opcode.

OP_vmovdqa32 

IA-32/AMD64 AVX-512 OP_vmovdqa32 opcode.

OP_vmovdqa64 

IA-32/AMD64 AVX-512 OP_vmovdqa64 opcode.

OP_vmovdqu16 

IA-32/AMD64 AVX-512 OP_vmovdqu16 opcode.

OP_vmovdqu32 

IA-32/AMD64 AVX-512 OP_vmovdqu32 opcode.

OP_vmovdqu64 

IA-32/AMD64 AVX-512 OP_vmovdqu64 opcode.

OP_vmovdqu8 

IA-32/AMD64 AVX-512 OP_vmovdqu8 opcode.

OP_vpabsq 

IA-32/AMD64 AVX-512 OP_vpabsq opcode.

OP_vpandd 

IA-32/AMD64 AVX-512 OP_vpandd opcode.

OP_vpandnd 

IA-32/AMD64 AVX-512 OP_vpandnd opcode.

OP_vpandnq 

IA-32/AMD64 AVX-512 OP_vpandnq opcode.

OP_vpandq 

IA-32/AMD64 AVX-512 OP_vpandq opcode.

OP_vpblendmb 

IA-32/AMD64 AVX-512 OP_vpblendmb opcode.

OP_vpblendmd 

IA-32/AMD64 AVX-512 OP_vpblendmd opcode.

OP_vpblendmq 

IA-32/AMD64 AVX-512 OP_vpblendmq opcode.

OP_vpblendmw 

IA-32/AMD64 AVX-512 OP_vpblendmw opcode.

OP_vpbroadcastmb2q 

IA-32/AMD64 AVX-512 OP_vpbroadcastmb2q opcode.

OP_vpbroadcastmw2d 

IA-32/AMD64 AVX-512 OP_vpbroadcastmw2d opcode.

OP_vpcmpb 

IA-32/AMD64 AVX-512 OP_vpcmpb opcode.

OP_vpcmpd 

IA-32/AMD64 AVX-512 OP_vpcmpd opcode.

OP_vpcmpq 

IA-32/AMD64 AVX-512 OP_vpcmpq opcode.

OP_vpcmpub 

IA-32/AMD64 AVX-512 OP_vpcmpub opcode.

OP_vpcmpud 

IA-32/AMD64 AVX-512 OP_vpcmpud opcode.

OP_vpcmpuq 

IA-32/AMD64 AVX-512 OP_vpcmpuq opcode.

OP_vpcmpuw 

IA-32/AMD64 AVX-512 OP_vpcmpuw opcode.

OP_vpcmpw 

IA-32/AMD64 AVX-512 OP_vpcmpw opcode.

OP_vpcompressd 

IA-32/AMD64 AVX-512 OP_vpcompressd opcode.

OP_vpcompressq 

IA-32/AMD64 AVX-512 OP_vpcompressq opcode.

OP_vpconflictd 

IA-32/AMD64 AVX-512 OP_vpconflictd opcode.

OP_vpconflictq 

IA-32/AMD64 AVX-512 OP_vpconflictq opcode.

OP_vpermb 

IA-32/AMD64 AVX-512 OP_vpermb opcode.

OP_vpermi2b 

IA-32/AMD64 AVX-512 OP_vpermi2b opcode.

OP_vpermi2d 

IA-32/AMD64 AVX-512 OP_vpermi2d opcode.

OP_vpermi2pd 

IA-32/AMD64 AVX-512 OP_vpermi2pd opcode.

OP_vpermi2ps 

IA-32/AMD64 AVX-512 OP_vpermi2ps opcode.

OP_vpermi2q 

IA-32/AMD64 AVX-512 OP_vpermi2q opcode.

OP_vpermi2w 

IA-32/AMD64 AVX-512 OP_vpermi2w opcode.

OP_vpermt2b 

IA-32/AMD64 AVX-512 OP_vpermt2b opcode.

OP_vpermt2d 

IA-32/AMD64 AVX-512 OP_vpermt2d opcode.

OP_vpermt2pd 

IA-32/AMD64 AVX-512 OP_vpermt2pd opcode.

OP_vpermt2ps 

IA-32/AMD64 AVX-512 OP_vpermt2ps opcode.

OP_vpermt2q 

IA-32/AMD64 AVX-512 OP_vpermt2q opcode.

OP_vpermt2w 

IA-32/AMD64 AVX-512 OP_vpermt2w opcode.

OP_vpermw 

IA-32/AMD64 AVX-512 OP_vpermw opcode.

OP_vpexpandd 

IA-32/AMD64 AVX-512 OP_vpexpandd opcode.

OP_vpexpandq 

IA-32/AMD64 AVX-512 OP_vpexpandq opcode.

OP_vpextrq 

IA-32/AMD64 AVX-512 OP_vpextrq opcode.

OP_vpinsrq 

IA-32/AMD64 AVX-512 OP_vpinsrq opcode.

OP_vplzcntd 

IA-32/AMD64 AVX-512 OP_vplzcntd opcode.

OP_vplzcntq 

IA-32/AMD64 AVX-512 OP_vplzcntq opcode.

OP_vpmadd52huq 

IA-32/AMD64 AVX-512 OP_vpmadd52huq opcode.

OP_vpmadd52luq 

IA-32/AMD64 AVX-512 OP_vpmadd52luq opcode.

OP_vpmaxsq 

IA-32/AMD64 AVX-512 OP_vpmaxsq opcode.

OP_vpmaxuq 

IA-32/AMD64 AVX-512 OP_vpmaxuq opcode.

OP_vpminsq 

IA-32/AMD64 AVX-512 OP_vpminsq opcode.

OP_vpminuq 

IA-32/AMD64 AVX-512 OP_vpminuq opcode.

OP_vpmovb2m 

IA-32/AMD64 AVX-512 OP_vpmovb2m opcode.

OP_vpmovd2m 

IA-32/AMD64 AVX-512 OP_vpmovd2m opcode.

OP_vpmovdb 

IA-32/AMD64 AVX-512 OP_vpmovdb opcode.

OP_vpmovdw 

IA-32/AMD64 AVX-512 OP_vpmovdw opcode.

OP_vpmovm2b 

IA-32/AMD64 AVX-512 OP_vpmovm2b opcode.

OP_vpmovm2d 

IA-32/AMD64 AVX-512 OP_vpmovm2d opcode.

OP_vpmovm2q 

IA-32/AMD64 AVX-512 OP_vpmovm2q opcode.

OP_vpmovm2w 

IA-32/AMD64 AVX-512 OP_vpmovm2w opcode.

OP_vpmovq2m 

IA-32/AMD64 AVX-512 OP_vpmovq2m opcode.

OP_vpmovqb 

IA-32/AMD64 AVX-512 OP_vpmovqb opcode.

OP_vpmovqd 

IA-32/AMD64 AVX-512 OP_vpmovqd opcode.

OP_vpmovqw 

IA-32/AMD64 AVX-512 OP_vpmovqw opcode.

OP_vpmovsdb 

IA-32/AMD64 AVX-512 OP_vpmovsdb opcode.

OP_vpmovsdw 

IA-32/AMD64 AVX-512 OP_vpmovsdw opcode.

OP_vpmovsqb 

IA-32/AMD64 AVX-512 OP_vpmovsqb opcode.

OP_vpmovsqd 

IA-32/AMD64 AVX-512 OP_vpmovsqd opcode.

OP_vpmovsqw 

IA-32/AMD64 AVX-512 OP_vpmovsqw opcode.

OP_vpmovswb 

IA-32/AMD64 AVX-512 OP_vpmovswb opcode.

OP_vpmovusdb 

IA-32/AMD64 AVX-512 OP_vpmovusdb opcode.

OP_vpmovusdw 

IA-32/AMD64 AVX-512 OP_vpmovusdw opcode.

OP_vpmovusqb 

IA-32/AMD64 AVX-512 OP_vpmovusqb opcode.

OP_vpmovusqd 

IA-32/AMD64 AVX-512 OP_vpmovusqd opcode.

OP_vpmovusqw 

IA-32/AMD64 AVX-512 OP_vpmovusqw opcode.

OP_vpmovuswb 

IA-32/AMD64 AVX-512 OP_vpmovuswb opcode.

OP_vpmovw2m 

IA-32/AMD64 AVX-512 OP_vpmovw2m opcode.

OP_vpmovwb 

IA-32/AMD64 AVX-512 OP_vpmovwb opcode.

OP_vpmullq 

IA-32/AMD64 AVX-512 OP_vpmullq opcode.

OP_vpord 

IA-32/AMD64 AVX-512 OP_vpord opcode.

OP_vporq 

IA-32/AMD64 AVX-512 OP_vporq opcode.

OP_vprold 

IA-32/AMD64 AVX-512 OP_vprold opcode.

OP_vprolq 

IA-32/AMD64 AVX-512 OP_vprolq opcode.

OP_vprolvd 

IA-32/AMD64 AVX-512 OP_vprolvd opcode.

OP_vprolvq 

IA-32/AMD64 AVX-512 OP_vprolvq opcode.

OP_vprord 

IA-32/AMD64 AVX-512 OP_vprord opcode.

OP_vprorq 

IA-32/AMD64 AVX-512 OP_vprorq opcode.

OP_vprorvd 

IA-32/AMD64 AVX-512 OP_vprorvd opcode.

OP_vprorvq 

IA-32/AMD64 AVX-512 OP_vprorvq opcode.

OP_vpscatterdd 

IA-32/AMD64 AVX-512 OP_vpscatterdd opcode.

OP_vpscatterdq 

IA-32/AMD64 AVX-512 OP_vpscatterdq opcode.

OP_vpscatterqd 

IA-32/AMD64 AVX-512 OP_vpscatterqd opcode.

OP_vpscatterqq 

IA-32/AMD64 AVX-512 OP_vpscatterqq opcode.

OP_vpsllvw 

IA-32/AMD64 AVX-512 OP_vpsllvw opcode.

OP_vpsraq 

IA-32/AMD64 AVX-512 OP_vpsraq opcode.

OP_vpsravq 

IA-32/AMD64 AVX-512 OP_vpsravq opcode.

OP_vpsravw 

IA-32/AMD64 AVX-512 OP_vpsravw opcode.

OP_vpsrlvw 

IA-32/AMD64 AVX-512 OP_vpsrlvw opcode.

OP_vpternlogd 

IA-32/AMD64 AVX-512 OP_vpternlogd opcode.

OP_vpternlogq 

IA-32/AMD64 AVX-512 OP_vpternlogd opcode.

OP_vptestmb 

IA-32/AMD64 AVX-512 OP_vptestmb opcode.

OP_vptestmd 

IA-32/AMD64 AVX-512 OP_vptestmd opcode.

OP_vptestmq 

IA-32/AMD64 AVX-512 OP_vptestmq opcode.

OP_vptestmw 

IA-32/AMD64 AVX-512 OP_vptestmw opcode.

OP_vptestnmb 

IA-32/AMD64 AVX-512 OP_vptestnmb opcode.

OP_vptestnmd 

IA-32/AMD64 AVX-512 OP_vptestnmd opcode.

OP_vptestnmq 

IA-32/AMD64 AVX-512 OP_vptestnmq opcode.

OP_vptestnmw 

IA-32/AMD64 AVX-512 OP_vptestnmw opcode.

OP_vpxord 

IA-32/AMD64 AVX-512 OP_vpxordvpxord opcode.

OP_vpxorq 

IA-32/AMD64 AVX-512 OP_vpxorq opcode.

OP_vrangepd 

IA-32/AMD64 AVX-512 OP_vrangepd opcode.

OP_vrangeps 

IA-32/AMD64 AVX-512 OP_vrangeps opcode.

OP_vrangesd 

IA-32/AMD64 AVX-512 OP_vrangesd opcode.

OP_vrangess 

IA-32/AMD64 AVX-512 OP_vrangess opcode.

OP_vrcp14pd 

IA-32/AMD64 AVX-512 OP_vrcp14pd opcode.

OP_vrcp14ps 

IA-32/AMD64 AVX-512 OP_vrcp14ps opcode.

OP_vrcp14sd 

IA-32/AMD64 AVX-512 OP_vrcp14sd opcode.

OP_vrcp14ss 

IA-32/AMD64 AVX-512 OP_vrcp14ss opcode.

OP_vrcp28pd 

IA-32/AMD64 AVX-512 OP_vrcp28pd opcode.

OP_vrcp28ps 

IA-32/AMD64 AVX-512 OP_vrcp28ps opcode.

OP_vrcp28sd 

IA-32/AMD64 AVX-512 OP_vrcp28sd opcode.

OP_vrcp28ss 

IA-32/AMD64 AVX-512 OP_vrcp28ss opcode.

OP_vreducepd 

IA-32/AMD64 AVX-512 OP_vreducepd opcode.

OP_vreduceps 

IA-32/AMD64 AVX-512 OP_vreduceps opcode.

OP_vreducesd 

IA-32/AMD64 AVX-512 OP_vreducesd opcode.

OP_vreducess 

IA-32/AMD64 AVX-512 OP_vreducess opcode.

OP_vrndscalepd 

IA-32/AMD64 AVX-512 OP_vrndscalepd opcode.

OP_vrndscaleps 

IA-32/AMD64 AVX-512 OP_vrndscaleps opcode.

OP_vrndscalesd 

IA-32/AMD64 AVX-512 OP_vrndscalesd opcode.

OP_vrndscaless 

IA-32/AMD64 AVX-512 OP_vrndscaless opcode.

OP_vrsqrt14pd 

IA-32/AMD64 AVX-512 OP_vrsqrt14pd opcode.

OP_vrsqrt14ps 

IA-32/AMD64 AVX-512 OP_vrsqrt14ps opcode.

OP_vrsqrt14sd 

IA-32/AMD64 AVX-512 OP_vrsqrt14sd opcode.

OP_vrsqrt14ss 

IA-32/AMD64 AVX-512 OP_vrsqrt14ss opcode.

OP_vrsqrt28pd 

IA-32/AMD64 AVX-512 OP_vrsqrt28pd opcode.

OP_vrsqrt28ps 

IA-32/AMD64 AVX-512 OP_vrsqrt28ps opcode.

OP_vrsqrt28sd 

IA-32/AMD64 AVX-512 OP_vrsqrt28sd opcode.

OP_vrsqrt28ss 

IA-32/AMD64 AVX-512 OP_vrsqrt28ss opcode.

OP_vscalefpd 

IA-32/AMD64 AVX-512 OP_vscalepd opcode.

OP_vscalefps 

IA-32/AMD64 AVX-512 OP_vscaleps opcode.

OP_vscalefsd 

IA-32/AMD64 AVX-512 OP_vscalesd opcode.

OP_vscalefss 

IA-32/AMD64 AVX-512 OP_vscalesss opcode.

OP_vscatterdpd 

IA-32/AMD64 AVX-512 OP_vscatterdpd opcode.

OP_vscatterdps 

IA-32/AMD64 AVX-512 OP_vscatterdps opcode.

OP_vscatterqpd 

IA-32/AMD64 AVX-512 OP_vscatterqpd opcode.

OP_vscatterqps 

IA-32/AMD64 AVX-512 OP_vscatterqps opcode.

OP_vscatterpf0dpd 

IA-32/AMD64 AVX-512 OP_vscatterpf0dpd opcode.

OP_vscatterpf0dps 

IA-32/AMD64 AVX-512 OP_vscatterpf0dps opcode.

OP_vscatterpf0qpd 

IA-32/AMD64 AVX-512 OP_vscatterpf0qpd opcode.

OP_vscatterpf0qps 

IA-32/AMD64 AVX-512 OP_vscatterpf0qps opcode.

OP_vscatterpf1dpd 

IA-32/AMD64 AVX-512 OP_vscatterpf1dpd opcode.

OP_vscatterpf1dps 

IA-32/AMD64 AVX-512 OP_vscatterpf1dps opcode.

OP_vscatterpf1qpd 

IA-32/AMD64 AVX-512 OP_vscatterpf1qpd opcode.

OP_vscatterpf1qps 

IA-32/AMD64 AVX-512 OP_vscatterpf1qps opcode.

OP_vshuff32x4 

IA-32/AMD64 AVX-512 OP_vshuff32x4 opcode.

OP_vshuff64x2 

IA-32/AMD64 AVX-512 OP_vshuff64x2 opcode.

OP_vshufi32x4 

IA-32/AMD64 AVX-512 OP_vshufi32x4 opcode.

OP_vshufi64x2 

IA-32/AMD64 AVX-512 OP_vshufi64x2 opcode.

OP_sha1msg1 

IA-32/AMD64 SHA OP_sha1msg1 opcode.

OP_sha1msg2 

IA-32/AMD64 SHA OP_sha1msg2 opcode.

OP_sha1nexte 

IA-32/AMD64 SHA OP_sha1nexte opcode.

OP_sha1rnds4 

IA-32/AMD64 SHA OP_sha1rnds4 opcode.

OP_sha256msg1 

IA-32/AMD64 SHA OP_sha2msg1 opcode.

OP_sha256msg2 

IA-32/AMD64 SHA OP_sha2msg2 opcode.

OP_sha256rnds2 

IA-32/AMD64 SHA OP_sha2rnds2 opcode.

OP_bndcl 

IA-32/AMD64 MPX OP_bndcl opcode.

OP_bndcn 

IA-32/AMD64 MPX OP_bndcn opcode.

OP_bndcu 

IA-32/AMD64 MPX OP_bndcu opcode.

OP_bndldx 

IA-32/AMD64 MPX OP_bndldx opcode.

OP_bndmk 

IA-32/AMD64 MPX OP_bndmk opcode.

OP_bndmov 

IA-32/AMD64 MPX OP_bndmov opcode.

OP_bndstx 

IA-32/AMD64 MPX OP_bndstx opcode.

OP_ptwrite 

IA-32/AMD64 PT OP_ptwrite opcode.

OP_monitorx 

AMD64 monitorx opcode.

OP_mwaitx 

AMD64 mwaitx opcode.

OP_rdpkru 

IA-32/AMD64 MPK rdpkru opcode.

OP_wrpkru 

IA-32/AMD64 MPK wrpkru opcode.

OP_encls 

IA-32/AMD64 SGX encls opcode.

OP_enclu 

IA-32/AMD64 SGX enclu opcode.

OP_enclv 

IA-32/AMD64 SGX enclv opcode.

OP_vpdpbusd 

IA-32/AMD64 vpdpbusd opcode.

OP_vpdpbusds 

IA-32/AMD64 vpdpbusds opcode.

OP_vpdpwssd 

IA-32/AMD64 vpdpwssd opcode.

OP_vpdpwssds 

IA-32/AMD64 vpdpwssds opcode.

OP_vcvtne2ps2bf16 

IA-32/AMD64 vcvtne2ps2bf16 opcode.

OP_vcvtneps2bf16 

IA-32/AMD64 vcvtneps2bf16 opcode.

OP_vdpbf16ps 

IA-32/AMD64 vdpbf16ps opcode.

OP_FIRST 

First real opcode.

OP_LAST 

Last real opcode.

OPSZ_NA 

Sentinel value: not a valid size.

OPSZ_0 

0 bytes, for "sizeless" operands (for Intel, code 'm': used for both start addresses (lea, invlpg) and implicit constants (rol, fldl2e, etc.)

OPSZ_1 

1 byte (for Intel, code 'b')

OPSZ_2 

2 bytes (for Intel, code 'w')

OPSZ_4 

4 bytes (for Intel, code 'd','si')

OPSZ_6 

6 bytes (for Intel, code 'p','s')

OPSZ_8 

8 bytes (for Intel, code 'q','pi')

OPSZ_10 

Intel 's' 64-bit, or double extended precision floating point (latter used by fld, fstp, fbld, fbstp)

OPSZ_16 

16 bytes (for Intel, code 'dq','ps','pd','ss','sd', or AMD 'o')

OPSZ_14 

FPU operating environment with short data size (fldenv, fnstenv)

OPSZ_28 

FPU operating environment with normal data size (fldenv, fnstenv)

OPSZ_94 

FPU state with short data size (fnsave, frstor)

OPSZ_108 

FPU state with normal data size (fnsave, frstor)

OPSZ_512 

FPU, MMX, XMM state (fxsave, fxrstor)

OPSZ_2_short1 

The following sizes (OPSZ_*_short*) vary according to the cs segment and the operand size prefix. This IR assumes that the cs segment is set to the default operand size. The operand size prefix then functions to shrink the size. The IR does not explicitly mark the prefix; rather, a shortened size is requested in the operands themselves, with the IR adding the prefix at encode time. Normally the fixed sizes above should be used rather than these variable sizes, which are used internally by the IR and should only be externally specified when building an operand in order to be flexible and allow other operands to decide the size for the instruction (the prefix applies to the entire instruction). Intel 'c': 2/1 bytes ("2/1" means 2 bytes normally, but if another operand requests a short size then this size can accommodate by shifting to its short size, which is 1 byte).

OPSZ_4_short2 

Intel 'z': 4/2 bytes

OPSZ_4_rex8_short2 

Intel 'v': 8/4/2 bytes

OPSZ_4_rex8 

Intel 'd/q' (like 'v' but never 2 bytes) or 'y'.

OPSZ_6_irex10_short4 

Intel 'p': On Intel processors this is 10/6/4 bytes for segment selector + address. On AMD processors this is 6/4 bytes for segment selector + address (rex is ignored).

OPSZ_8_short2 

partially resolved 4x8_short2

OPSZ_8_short4 

Intel 'a': pair of 4_short2 (bound)

OPSZ_28_short14 

FPU operating env variable data size (fldenv, fnstenv)

OPSZ_108_short94 

FPU state with variable data size (fnsave, frstor)

OPSZ_4x8 

Varies by 32-bit versus 64-bit processor mode. Full register size with no variation by prefix. Used for control and debug register moves and for Intel MPX.

OPSZ_6x10 

Intel 's': 6-byte (10-byte for 64-bit mode) table base + limit

OPSZ_4x8_short2 

Stack operands not only vary by operand size specifications but also by 32-bit versus 64-bit processor mode. Intel 'v'/'d64' for stack operations. Also 64-bit address-size specified operands, which are short4 rather than short2 in 64-bit mode (but short2 in 32-bit mode). Note that this IR does not distinguish extra stack operations performed by OP_enter w/ non-zero immed.

OPSZ_4x8_short2xi8 

Intel 'f64': 4_short2 for 32-bit, 8_short2 for 64-bit AMD, always 8 for 64-bit Intel

OPSZ_4_short2xi4 

Intel 'f64': 4_short2 for 32-bit or 64-bit AMD, always 4 for 64-bit Intel

OPSZ_1_reg4 

The following 3 sizes differ based on whether the modrm chooses a register or memory. Intel Rd/Mb: zero-extends if reg; used by pextrb

OPSZ_2_reg4 

Intel Rd/Mw: zero-extends if reg; used by pextrw

OPSZ_4_reg16 

Intel Udq/Md: 4 bytes of xmm or 4 bytes of memory; used by insertps.

OPSZ_xsave 

Size is > 512 bytes: use cpuid to determine. Used for FPU, MMX, XMM, etc. state by xsave and xrstor.

OPSZ_12 

12 bytes: 32-bit iret

OPSZ_32 

32 bytes: pusha/popa Also Intel 'qq','pd','ps','x': 32 bytes (256 bits)

OPSZ_40 

40 bytes: 64-bit iret

OPSZ_32_short16 

unresolved pusha/popa

OPSZ_8_rex16 

cmpxcgh8b/cmpxchg16b

OPSZ_8_rex16_short4 

Intel 'v' * 2 (far call/ret)

OPSZ_12_rex40_short6 

unresolved iret

OPSZ_16_vex32 

16 or 32 bytes depending on VEX.L (AMD/Intel 'x').

OPSZ_15 

All but one byte of an xmm register (used by OP_vpinsrb).

OPSZ_3 

3 bytes

OPSZ_1b 

1 bit

OPSZ_2b 

2 bits

OPSZ_3b 

3 bits

OPSZ_4b 

4 bits

OPSZ_5b 

5 bits

OPSZ_6b 

6 bits

OPSZ_7b 

7 bits

OPSZ_9b 

9 bits

OPSZ_10b 

10 bits

OPSZ_11b 

11 bits

OPSZ_12b 

12 bits

OPSZ_20b 

20 bits

OPSZ_25b 

25 bits

OPSZ_VAR_REGLIST 

At encode or decode time, the size will match the size of the register list operand in the containing instruction's operands.

OPSZ_20 

20 bytes. Needed for load/store of register lists.

OPSZ_24 

24 bytes. Needed for load/store of register lists.

OPSZ_36 

36 bytes. Needed for load/store of register lists.

OPSZ_44 

44 bytes. Needed for load/store of register lists.

OPSZ_48 

48 bytes. Needed for load/store of register lists.

OPSZ_52 

52 bytes. Needed for load/store of register lists.

OPSZ_56 

56 bytes. Needed for load/store of register lists.

OPSZ_60 

60 bytes. Needed for load/store of register lists.

OPSZ_64 

64 bytes. Needed for load/store of register lists. Also Intel: 64 bytes (512 bits)

OPSZ_68 

68 bytes. Needed for load/store of register lists.

OPSZ_72 

72 bytes. Needed for load/store of register lists.

OPSZ_76 

76 bytes. Needed for load/store of register lists.

OPSZ_80 

80 bytes. Needed for load/store of register lists.

OPSZ_84 

84 bytes. Needed for load/store of register lists.

OPSZ_88 

88 bytes. Needed for load/store of register lists.

OPSZ_92 

92 bytes. Needed for load/store of register lists.

OPSZ_96 

96 bytes. Needed for load/store of register lists.

OPSZ_100 

100 bytes. Needed for load/store of register lists.

OPSZ_104 

104 bytes. Needed for load/store of register lists.

OPSZ_112 

112 bytes. Needed for load/store of register lists.

OPSZ_116 

116 bytes. Needed for load/store of register lists.

OPSZ_120 

120 bytes. Needed for load/store of register lists.

OPSZ_124 

124 bytes. Needed for load/store of register lists.

OPSZ_128 

128 bytes. Needed for load/store of register lists.

OPSZ_SCALABLE 

Scalable size for SVE vector registers.

OPSZ_SCALABLE_PRED 

Scalable size for SVE predicate registers.

OPSZ_16_vex32_evex64 

16, 32, or 64 bytes depending on EVEX.L and EVEX.LL'.

OPSZ_vex32_evex64 

32 or 64 bytes depending on EVEX.L and EVEX.LL'.

OPSZ_16_of_32_evex64 

128 bits: half of YMM or quarter of ZMM depending on EVEX.LL'.

OPSZ_32_of_64 

256 bits: half of ZMM.

OPSZ_4_of_32_evex64 

32 bits: can be part of YMM or ZMM register.

OPSZ_8_of_32_evex64 

64 bits: can be part of YMM or ZMM register.

OPSZ_8x16 

8 or 16 bytes, but not based on rex prefix, instead dependent on 32-bit/64-bit mode.

VENDOR_INTEL 

proc_get_vendor() processor identification: Intel

VENDOR_AMD 

proc_get_vendor() processor identification: AMD

VENDOR_ARM 

proc_get_vendor() processor identification: ARM

VENDOR_UNKNOWN 

proc_get_vendor() processor identification: unknown

DR_MAP_PRIVATE 

If set, changes to mapped memory are private to the mapping process and are not reflected in the underlying file. If not set, changes are visible to other processes that map the same file, and will be propagated to the file itself.

DR_MAP_FIXED 

If set, indicates that the passed-in start address is required rather than a hint. On Linux, this has the same semantics as mmap with MAP_FIXED: i.e., any existing mapping in [addr,addr+size) will be unmapped. This flag is not supported on Windows.

DR_MAP_IMAGE 

If set, loads the specified file as an executable image, rather than a data file. This flag is not supported on Linux.

DR_MAP_CACHE_REACHABLE 

If set, loads the specified file at a location that is reachable from the code cache and client libraries by a 32-bit displacement. If not set, the mapped file is not guaranteed to be reachable from the cache.

DRMGR_PRIORITY_APP2APP_DRBBDUP 

Priority of drbbdup's app2app stage.

DRMGR_PRIORITY_INSERT_DRBBDUP 

Priority of drbbdup's insert stage.

DRMGR_PRIORITY_INSERT_DRREG_HIGH 

Priority of drreg analysis and pre-insert

DRMGR_PRIORITY_INSERT_DRREG_LOW 

Priority of drreg post-insert

DRMGR_PRIORITY_FAULT_DRREG 

Priority of drreg fault handling event

DRSYM_TYPE_OTHER 

Unknown type, cannot downcast.

DRSYM_TYPE_INT 

Integer, cast to drsym_int_type_t.

DRSYM_TYPE_PTR 

Pointer, cast to drsym_ptr_type_t.

DRSYM_TYPE_FUNC 

Function, cast to drsym_func_type_t.

DRSYM_TYPE_VOID 

Void. No further information.

DRSYM_TYPE_COMPOUND 

Struct, union, or class; cast to drsym_compound_type_t.

DRMGR_PRIORITY_APP2APP_DRWRAP 

Priority of drwrap_replace()

DRMGR_PRIORITY_INSERT_DRWRAP 

Priority of drwrap_wrap()

DRMGR_PRIORITY_FAULT_DRWRAP 

Priority of fault handling event

DRMGR_PRIORITY_FAULT_DRX 

Priority of drx fault handling event.

OP_orn
@ OP_orn
Definition: dr_ir_opcodes_arm.h:186
OP_vst3_lane_16
@ OP_vst3_lane_16
Definition: dr_ir_opcodes_arm.h:939
OP_stmib_priv
@ OP_stmib_priv
Definition: dr_ir_opcodes_arm.h:314
OP_ldrh
@ OP_ldrh
Definition: dr_ir_opcodes_arm.h:150
OP_vld1_lane_16
@ OP_vld1_lane_16
Definition: dr_ir_opcodes_arm.h:556
OP_vld1_64
@ OP_vld1_64
Definition: dr_ir_opcodes_arm.h:551
OP_vst4_8
@ OP_vst4_8
Definition: dr_ir_opcodes_arm.h:944
opnd_add_flags
DR_API opnd_t opnd_add_flags(opnd_t opnd, dr_opnd_flags_t flags)
OP_ldrb
@ OP_ldrb
Definition: dr_ir_opcodes_arm.h:143
OP_mvns
@ OP_mvns
Definition: dr_ir_opcodes_arm.h:184
OP_strd
@ OP_strd
Definition: dr_ir_opcodes_arm.h:318
OP_strt
@ OP_strt
Definition: dr_ir_opcodes_arm.h:325
OP_vst3_8
@ OP_vst3_8
Definition: dr_ir_opcodes_arm.h:938
OP_vst1_lane_32
@ OP_vst1_lane_32
Definition: dr_ir_opcodes_arm.h:928
DR_ISA_ARM_THUMB
@ DR_ISA_ARM_THUMB
Definition: dr_ir_encode.h:51
INSTR_CREATE_orr_shimm
#define INSTR_CREATE_orr_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1709
OP_vst4_lane_32
@ OP_vst4_lane_32
Definition: dr_ir_opcodes_arm.h:946
OP_rfeib
@ OP_rfeib
Definition: dr_ir_opcodes_arm.h:212
OP_vst4_32
@ OP_vst4_32
Definition: dr_ir_opcodes_arm.h:943
OP_subs
@ OP_subs
Definition: dr_ir_opcodes_arm.h:327
OP_stc
@ OP_stc
Definition: dr_ir_opcodes_arm.h:296
INSTR_CREATE_rsc_shimm
#define INSTR_CREATE_rsc_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1731
OP_vst4_lane_16
@ OP_vst4_lane_16
Definition: dr_ir_opcodes_arm.h:945
INSTR_CREATE_bics_shimm
#define INSTR_CREATE_bics_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1689
OP_vld4_16
@ OP_vld4_16
Definition: dr_ir_opcodes_arm.h:577
OP_srsda
@ OP_srsda
Definition: dr_ir_opcodes_arm.h:288
OP_vstmdb
@ OP_vstmdb
Definition: dr_ir_opcodes_arm.h:949
OP_stmdb_priv
@ OP_stmdb_priv
Definition: dr_ir_opcodes_arm.h:312
instr_create_2dst_2src
DR_API instr_t * instr_create_2dst_2src(void *drcontext, int opcode, opnd_t dst1, opnd_t dst2, opnd_t src1, opnd_t src2)
INSTR_CREATE_cmn_shimm
#define INSTR_CREATE_cmn_shimm(dc, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1628
INSTR_CREATE_and_shimm
#define INSTR_CREATE_and_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1677
INSTR_CREATE_eors_shimm
#define INSTR_CREATE_eors_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1697
OP_vld3_dup_32
@ OP_vld3_dup_32
Definition: dr_ir_opcodes_arm.h:572
OP_rfe
@ OP_rfe
Definition: dr_ir_opcodes_arm.h:209
OP_rsb
@ OP_rsb
Definition: dr_ir_opcodes_arm.h:217
OP_vst3_lane_32
@ OP_vst3_lane_32
Definition: dr_ir_opcodes_arm.h:940
OP_strb
@ OP_strb
Definition: dr_ir_opcodes_arm.h:316
OP_vld4_dup_32
@ OP_vld4_dup_32
Definition: dr_ir_opcodes_arm.h:581
OP_teq
@ OP_teq
Definition: dr_ir_opcodes_arm.h:340
OP_usat
@ OP_usat
Definition: dr_ir_opcodes_arm.h:367
INSTR_CREATE_subs_shimm
#define INSTR_CREATE_subs_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1751
OP_vst3_32
@ OP_vst3_32
Definition: dr_ir_opcodes_arm.h:937
OP_stc2
@ OP_stc2
Definition: dr_ir_opcodes_arm.h:297
INSTR_CREATE_mvn
#define INSTR_CREATE_mvn(dc, Rd, Rm_or_imm)
Definition: dr_ir_macros_arm.h:1050
OPND_CREATE_MEMPTR
#define OPND_CREATE_MEMPTR
Definition: dr_ir_macros.h:92
INSTR_CREATE_adc_shimm
#define INSTR_CREATE_adc_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1661
OP_rsbs
@ OP_rsbs
Definition: dr_ir_opcodes_arm.h:218
INSTR_CREATE_rsb_shimm
#define INSTR_CREATE_rsb_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1723
INSTR_CREATE_str_wbimm
#define INSTR_CREATE_str_wbimm(dc, mem, Rt, imm)
Definition: dr_ir_macros_arm.h:2177
OP_strbt
@ OP_strbt
Definition: dr_ir_opcodes_arm.h:317
instr_create_1dst_1src
DR_API instr_t * instr_create_1dst_1src(void *drcontext, int opcode, opnd_t dst, opnd_t src)
INSTR_CREATE_b_short
#define INSTR_CREATE_b_short(dc, pc)
Definition: dr_ir_macros_arm.h:596
OP_ldr
@ OP_ldr
Definition: dr_ir_opcodes_arm.h:142
INSTR_CREATE_ands_shimm
#define INSTR_CREATE_ands_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1681
OP_and
@ OP_and
Definition: dr_ir_opcodes_arm.h:76
OP_vld2_dup_8
@ OP_vld2_dup_8
Definition: dr_ir_opcodes_arm.h:564
DR_REG_XSP
#define DR_REG_XSP
Definition: dr_ir_opnd.h:1303
INSTR_CREATE_bic_shimm
#define INSTR_CREATE_bic_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1685
OP_vld1_lane_32
@ OP_vld1_lane_32
Definition: dr_ir_opcodes_arm.h:557
OP_vst1_lane_16
@ OP_vst1_lane_16
Definition: dr_ir_opcodes_arm.h:927
OP_vst2_lane_32
@ OP_vst2_lane_32
Definition: dr_ir_opcodes_arm.h:934
INSTR_CREATE_eor_shimm
#define INSTR_CREATE_eor_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1693
instr_create_1dst_4src
DR_API instr_t * instr_create_1dst_4src(void *drcontext, int opcode, opnd_t dst, opnd_t src1, opnd_t src2, opnd_t src3, opnd_t src4)
OP_vld4_8
@ OP_vld4_8
Definition: dr_ir_opcodes_arm.h:579
OP_vld2_lane_8
@ OP_vld2_lane_8
Definition: dr_ir_opcodes_arm.h:567
OP_add
@ OP_add
Definition: dr_ir_opcodes_arm.h:69
OP_ldrsb
@ OP_ldrsb
Definition: dr_ir_opcodes_arm.h:152
OP_vst2_lane_8
@ OP_vst2_lane_8
Definition: dr_ir_opcodes_arm.h:935
OP_vst1_8
@ OP_vst1_8
Definition: dr_ir_opcodes_arm.h:926
OP_vld3_lane_8
@ OP_vld3_lane_8
Definition: dr_ir_opcodes_arm.h:576
OP_ldrsht
@ OP_ldrsht
Definition: dr_ir_opcodes_arm.h:155
OP_vld4_32
@ OP_vld4_32
Definition: dr_ir_opcodes_arm.h:578
INSTR_CREATE_sbc_shimm
#define INSTR_CREATE_sbc_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1739
OP_vld3_dup_8
@ OP_vld3_dup_8
Definition: dr_ir_opcodes_arm.h:573
OP_ldmib_priv
@ OP_ldmib_priv
Definition: dr_ir_opcodes_arm.h:141
OP_vst1_64
@ OP_vst1_64
Definition: dr_ir_opcodes_arm.h:925
OPND_CREATE_INT8
#define OPND_CREATE_INT8(val)
Definition: dr_ir_macros.h:136
OP_bic
@ OP_bic
Definition: dr_ir_opcodes_arm.h:84
instr_create_Ndst_Msrc_varsrc
DR_API instr_t * instr_create_Ndst_Msrc_varsrc(void *drcontext, int opcode, uint fixed_dsts, uint fixed_srcs, uint var_srcs, uint var_ord,...)
OP_vld4_dup_16
@ OP_vld4_dup_16
Definition: dr_ir_opcodes_arm.h:580
INSTR_CREATE_sub_shimm
#define INSTR_CREATE_sub_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1747
OP_srs
@ OP_srs
Definition: dr_ir_opcodes_arm.h:287
OP_stm
@ OP_stm
Definition: dr_ir_opcodes_arm.h:307
INSTR_CREATE_sbcs_shimm
#define INSTR_CREATE_sbcs_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1743
INSTR_CREATE_mvns_shimm
#define INSTR_CREATE_mvns_shimm(dc, Rd, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1608
OP_vst1_lane_8
@ OP_vst1_lane_8
Definition: dr_ir_opcodes_arm.h:929
OP_vld4_dup_8
@ OP_vld4_dup_8
Definition: dr_ir_opcodes_arm.h:582
OP_vld2_dup_32
@ OP_vld2_dup_32
Definition: dr_ir_opcodes_arm.h:563
OP_vst2_8
@ OP_vst2_8
Definition: dr_ir_opcodes_arm.h:932
OP_vld1_dup_8
@ OP_vld1_dup_8
Definition: dr_ir_opcodes_arm.h:555
OPND_CREATE_INT16
#define OPND_CREATE_INT16(val)
Definition: dr_ir_macros.h:130
instr_create_0dst_2src
DR_API instr_t * instr_create_0dst_2src(void *drcontext, int opcode, opnd_t src1, opnd_t src2)
OP_srsdb
@ OP_srsdb
Definition: dr_ir_opcodes_arm.h:289
OP_cmn
@ OP_cmn
Definition: dr_ir_opcodes_arm.h:98
INSTR_CREATE_rsbs_shimm
#define INSTR_CREATE_rsbs_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1727
OP_orrs
@ OP_orrs
Definition: dr_ir_opcodes_arm.h:189
OP_vst1_32
@ OP_vst1_32
Definition: dr_ir_opcodes_arm.h:924
OP_ldc2l
@ OP_ldc2l
Definition: dr_ir_opcodes_arm.h:132
OP_vst3_lane_8
@ OP_vst3_lane_8
Definition: dr_ir_opcodes_arm.h:941
OP_vcmp_f32
@ OP_vcmp_f32
Definition: dr_ir_opcodes_arm.h:469
OP_vld3_8
@ OP_vld3_8
Definition: dr_ir_opcodes_arm.h:570
OP_stmda_priv
@ OP_stmda_priv
Definition: dr_ir_opcodes_arm.h:310
OP_adc
@ OP_adc
Definition: dr_ir_opcodes_arm.h:67
OP_ldmda_priv
@ OP_ldmda_priv
Definition: dr_ir_opcodes_arm.h:137
OP_eors
@ OP_eors
Definition: dr_ir_opcodes_arm.h:117
OP_pkhbt
@ OP_pkhbt
Definition: dr_ir_opcodes_arm.h:190
OP_adds
@ OP_adds
Definition: dr_ir_opcodes_arm.h:70
OP_ldmda
@ OP_ldmda
Definition: dr_ir_opcodes_arm.h:136
OP_vst2_16
@ OP_vst2_16
Definition: dr_ir_opcodes_arm.h:930
INSTR_CREATE_add_shimm
#define INSTR_CREATE_add_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1669
OP_vst4_lane_8
@ OP_vst4_lane_8
Definition: dr_ir_opcodes_arm.h:947
OP_vld3_32
@ OP_vld3_32
Definition: dr_ir_opcodes_arm.h:569
OP_tst
@ OP_tst
Definition: dr_ir_opcodes_arm.h:341
OP_vld1_32
@ OP_vld1_32
Definition: dr_ir_opcodes_arm.h:550
OP_vld2_dup_16
@ OP_vld2_dup_16
Definition: dr_ir_opcodes_arm.h:562
DR_OPND_IS_SHIFT
@ DR_OPND_IS_SHIFT
Definition: dr_ir_opnd.h:1682
OP_vcmpe_f32
@ OP_vcmpe_f32
Definition: dr_ir_opcodes_arm.h:471
OP_ldrsbt
@ OP_ldrsbt
Definition: dr_ir_opcodes_arm.h:153
INSTR_CREATE_b
#define INSTR_CREATE_b(dc, pc)
Definition: dr_ir_macros_arm.h:595
INSTR_CREATE_orns_shimm
#define INSTR_CREATE_orns_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1705
opnd_create_reg
DR_API INSTR_INLINE opnd_t opnd_create_reg(reg_id_t r)
OP_pkhtb
@ OP_pkhtb
Definition: dr_ir_opcodes_arm.h:191
OP_vld4_lane_8
@ OP_vld4_lane_8
Definition: dr_ir_opcodes_arm.h:585
OP_srsib
@ OP_srsib
Definition: dr_ir_opcodes_arm.h:290
OP_vstm
@ OP_vstm
Definition: dr_ir_opcodes_arm.h:948
OP_vld1_8
@ OP_vld1_8
Definition: dr_ir_opcodes_arm.h:552
instr_create_3dst_3src
DR_API instr_t * instr_create_3dst_3src(void *drcontext, int opcode, opnd_t dst1, opnd_t dst2, opnd_t dst3, opnd_t src1, opnd_t src2, opnd_t src3)
opnd_get_base
DR_API reg_id_t opnd_get_base(opnd_t opnd)
OP_vld3_lane_16
@ OP_vld3_lane_16
Definition: dr_ir_opcodes_arm.h:574
OP_vld4_lane_16
@ OP_vld4_lane_16
Definition: dr_ir_opcodes_arm.h:583
instr_create_1dst_2src
DR_API instr_t * instr_create_1dst_2src(void *drcontext, int opcode, opnd_t dst, opnd_t src1, opnd_t src2)
OP_vst3_16
@ OP_vst3_16
Definition: dr_ir_opcodes_arm.h:936
instr_create_Ndst_Msrc_vardst
DR_API instr_t * instr_create_Ndst_Msrc_vardst(void *drcontext, int opcode, uint fixed_dsts, uint fixed_srcs, uint var_dsts, uint var_ord,...)
DR_OPND_SHIFTED
@ DR_OPND_SHIFTED
Definition: dr_ir_opnd.h:1671
OP_vld1_dup_16
@ OP_vld1_dup_16
Definition: dr_ir_opcodes_arm.h:553
OP_ldm
@ OP_ldm
Definition: dr_ir_opcodes_arm.h:134
OP_ldmdb
@ OP_ldmdb
Definition: dr_ir_opcodes_arm.h:138
INSTR_CREATE_ldr_wbimm
#define INSTR_CREATE_ldr_wbimm(dc, Rd, mem, imm)
Definition: dr_ir_macros_arm.h:2132
OP_str
@ OP_str
Definition: dr_ir_opcodes_arm.h:315
OP_ldmdb_priv
@ OP_ldmdb_priv
Definition: dr_ir_opcodes_arm.h:139
OP_vst2_32
@ OP_vst2_32
Definition: dr_ir_opcodes_arm.h:931
OP_rfedb
@ OP_rfedb
Definition: dr_ir_opcodes_arm.h:211
OP_vld1_lane_8
@ OP_vld1_lane_8
Definition: dr_ir_opcodes_arm.h:558
OP_vld3_dup_16
@ OP_vld3_dup_16
Definition: dr_ir_opcodes_arm.h:571
DR_SHIFT_LSL
@ DR_SHIFT_LSL
Definition: dr_ir_opnd.h:1616
OP_vldm
@ OP_vldm
Definition: dr_ir_opcodes_arm.h:586
INSTR_CREATE_rscs_shimm
#define INSTR_CREATE_rscs_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1735
DR_SHIFT_NONE
@ DR_SHIFT_NONE
Definition: dr_ir_opnd.h:1633
opnd_is_reg
DR_API bool opnd_is_reg(opnd_t opnd)
OP_eor
@ OP_eor
Definition: dr_ir_opcodes_arm.h:116
OP_vtbx_8
@ OP_vtbx_8
Definition: dr_ir_opcodes_arm.h:974
INSTR_CREATE_mvn_shimm
#define INSTR_CREATE_mvn_shimm(dc, Rd, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1604
OP_cmp
@ OP_cmp
Definition: dr_ir_opcodes_arm.h:99
INSTR_CREATE_cmp_shimm
#define INSTR_CREATE_cmp_shimm(dc, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1632
OP_strh
@ OP_strh
Definition: dr_ir_opcodes_arm.h:323
OP_cdp
@ OP_cdp
Definition: dr_ir_opcodes_arm.h:94
OP_bics
@ OP_bics
Definition: dr_ir_opcodes_arm.h:85
OP_adcs
@ OP_adcs
Definition: dr_ir_opcodes_arm.h:68
OP_sbc
@ OP_sbc
Definition: dr_ir_opcodes_arm.h:224
OP_orns
@ OP_orns
Definition: dr_ir_opcodes_arm.h:187
OP_sub
@ OP_sub
Definition: dr_ir_opcodes_arm.h:326
INSTR_CREATE_tst_shimm
#define INSTR_CREATE_tst_shimm(dc, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1640
OP_vcmpe_f64
@ OP_vcmpe_f64
Definition: dr_ir_opcodes_arm.h:472
OP_vst4_16
@ OP_vst4_16
Definition: dr_ir_opcodes_arm.h:942
instr_create_0dst_4src
DR_API instr_t * instr_create_0dst_4src(void *drcontext, int opcode, opnd_t src1, opnd_t src2, opnd_t src3, opnd_t src4)
OP_stm_priv
@ OP_stm_priv
Definition: dr_ir_opcodes_arm.h:308
OP_ldc2
@ OP_ldc2
Definition: dr_ir_opcodes_arm.h:131
INSTR_CREATE_adcs_shimm
#define INSTR_CREATE_adcs_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1665
OP_vld1_16
@ OP_vld1_16
Definition: dr_ir_opcodes_arm.h:549
INSTR_CREATE_teq_shimm
#define INSTR_CREATE_teq_shimm(dc, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1636
OP_vld2_16
@ OP_vld2_16
Definition: dr_ir_opcodes_arm.h:559
instr_create_2dst_4src
DR_API instr_t * instr_create_2dst_4src(void *drcontext, int opcode, opnd_t dst1, opnd_t dst2, opnd_t src1, opnd_t src2, opnd_t src3, opnd_t src4)
OP_sbcs
@ OP_sbcs
Definition: dr_ir_opcodes_arm.h:225
OP_stmda
@ OP_stmda
Definition: dr_ir_opcodes_arm.h:309
OP_ands
@ OP_ands
Definition: dr_ir_opcodes_arm.h:77
opnd_get_immed_int
DR_API ptr_int_t opnd_get_immed_int(opnd_t opnd)
OP_stcl
@ OP_stcl
Definition: dr_ir_opcodes_arm.h:299
OP_vcmp_f64
@ OP_vcmp_f64
Definition: dr_ir_opcodes_arm.h:470
OP_vld2_lane_16
@ OP_vld2_lane_16
Definition: dr_ir_opcodes_arm.h:565
OP_vld1_dup_32
@ OP_vld1_dup_32
Definition: dr_ir_opcodes_arm.h:554
instr_create_1dst_5src
DR_API instr_t * instr_create_1dst_5src(void *drcontext, int opcode, opnd_t dst, opnd_t src1, opnd_t src2, opnd_t src3, opnd_t src4, opnd_t src5)
OP_stmib
@ OP_stmib
Definition: dr_ir_opcodes_arm.h:313
INSTR_CREATE_adds_shimm
#define INSTR_CREATE_adds_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1673
OP_mvn
@ OP_mvn
Definition: dr_ir_opcodes_arm.h:183
OP_ldm_priv
@ OP_ldm_priv
Definition: dr_ir_opcodes_arm.h:135
OP_ldc
@ OP_ldc
Definition: dr_ir_opcodes_arm.h:130
OP_ssat
@ OP_ssat
Definition: dr_ir_opcodes_arm.h:291
OP_vld4_lane_32
@ OP_vld4_lane_32
Definition: dr_ir_opcodes_arm.h:584
OP_vldmdb
@ OP_vldmdb
Definition: dr_ir_opcodes_arm.h:587
OP_rfeda
@ OP_rfeda
Definition: dr_ir_opcodes_arm.h:210
instr_create_1dst_3src
DR_API instr_t * instr_create_1dst_3src(void *drcontext, int opcode, opnd_t dst, opnd_t src1, opnd_t src2, opnd_t src3)
OP_vld3_16
@ OP_vld3_16
Definition: dr_ir_opcodes_arm.h:568
OP_vst1_16
@ OP_vst1_16
Definition: dr_ir_opcodes_arm.h:923
instr_create_2dst_3src
DR_API instr_t * instr_create_2dst_3src(void *drcontext, int opcode, opnd_t dst1, opnd_t dst2, opnd_t src1, opnd_t src2, opnd_t src3)
INSTR_CREATE_orrs_shimm
#define INSTR_CREATE_orrs_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1713
OP_ldrd
@ OP_ldrd
Definition: dr_ir_opcodes_arm.h:145
OP_vld2_32
@ OP_vld2_32
Definition: dr_ir_opcodes_arm.h:560
INSTR_CREATE_movw
#define INSTR_CREATE_movw(dc, Rd, imm)
Definition: dr_ir_macros_arm.h:976
OP_rsc
@ OP_rsc
Definition: dr_ir_opcodes_arm.h:219
opnd_get_reg
DR_API reg_id_t opnd_get_reg(opnd_t opnd)
OP_strht
@ OP_strht
Definition: dr_ir_opcodes_arm.h:324
dr_get_isa_mode
DR_API dr_isa_mode_t dr_get_isa_mode(void *drcontext)
OP_ldrsh
@ OP_ldrsh
Definition: dr_ir_opcodes_arm.h:154
OP_ldmib
@ OP_ldmib
Definition: dr_ir_opcodes_arm.h:140
OP_ldcl
@ OP_ldcl
Definition: dr_ir_opcodes_arm.h:133
OP_stmdb
@ OP_stmdb
Definition: dr_ir_opcodes_arm.h:311
OP_vld2_lane_32
@ OP_vld2_lane_32
Definition: dr_ir_opcodes_arm.h:566
OP_vst2_lane_16
@ OP_vst2_lane_16
Definition: dr_ir_opcodes_arm.h:933
opnd_create_reg_ex
DR_API INSTR_INLINE opnd_t opnd_create_reg_ex(reg_id_t r, opnd_size_t subsize, dr_opnd_flags_t flags)
OP_ldrt
@ OP_ldrt
Definition: dr_ir_opcodes_arm.h:156
OP_vld3_lane_32
@ OP_vld3_lane_32
Definition: dr_ir_opcodes_arm.h:575
OP_ldrht
@ OP_ldrht
Definition: dr_ir_opcodes_arm.h:151
OP_stc2l
@ OP_stc2l
Definition: dr_ir_opcodes_arm.h:298
OP_rscs
@ OP_rscs
Definition: dr_ir_opcodes_arm.h:220
INSTR_CREATE_orn_shimm
#define INSTR_CREATE_orn_shimm(dc, Rd, Rn, Rm, shift, imm)
Definition: dr_ir_macros_arm.h:1701
instr_create_2dst_5src
DR_API instr_t * instr_create_2dst_5src(void *drcontext, int opcode, opnd_t dst1, opnd_t dst2, opnd_t src1, opnd_t src2, opnd_t src3, opnd_t src4, opnd_t src5)
OP_vld2_8
@ OP_vld2_8
Definition: dr_ir_opcodes_arm.h:561
OP_ldrbt
@ OP_ldrbt
Definition: dr_ir_opcodes_arm.h:144
OP_vtbl_8
@ OP_vtbl_8
Definition: dr_ir_opcodes_arm.h:973
OPND_CREATE_INTPTR
#define OPND_CREATE_INTPTR
Definition: dr_ir_macros.h:110
OP_orr
@ OP_orr
Definition: dr_ir_opcodes_arm.h:188